aida annual meeting,vienna, 26th march 2014václav vrba, institute of physics, prague 1 design of...
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AIDA annual meeting,Vienna, 26th March 2014 Václav Vrba, Institute of Physics, Prague1
design of sensors for production submission design of the readout chain plans for near future
ON Semiconductor
AIDA annual meeting,Vienna, 26th March 2014 Václav Vrba, Institute of Physics, Prague2
• ON Semiconductor: 6” wafers stepping mask projection machines, the stitching technique is needed some problem inside ON Semi with man power to be
dedicated to that task we are continuing the discussion with ON Semi, but
no date fixed in meanwhile we are we are looking for other sensor
providers we received few quotation, the price (confidential)
significantly overrides our expectations despite of that we believe to come to the acceptable
solution
Development of a full read out chain
AIDA annual meeting,Vienna, 26th March 2014 Václav Vrba, Institute of Physics, Prague3
the chain was tested on the pixel sensor array with the RO MediPix chip
but in principle any RO chip can be used
AIDA meeting
DAQ Interface card with CoaXPress interface.
AIDA meeting 25.3.2014
•AIDA annual meeting,Vienna, 26th March 2014
•Václav Vrba, Institute of Physics,
Prague
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•Václav Vrba, Institute of Physics,
Prague
Suitable communication protocol for HEP experiments pixel detector DAQ?
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•Václav Vrba, Institute of Physics,
Prague
Overview of possible detector readout communication protocols
NamePCIe 10GbE USB3.0 CoaXPress
Speed 16 x 3.125Gbps
10Gbps (=6Gbps
ef.)
5Gbps(=4Gbps
ef.)
4 x 6.25 Gbps
Max distance
2m Cu 100m 2m (5m) 100m
IP core Avail. / free
Avail. / $$ Avail. / $Soon free
Avail / $$
Optical No Yes optional
No No
Cost 10$ 100$+ 10$ 50$
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•Václav Vrba, Institute of Physics,
Prague
CoaXPress
- Emerging communication standard for for machine vision applications.
- Serial communication standard over standard coaxial cable.
- High data throughput, downstream up to 6.25 Gbps.
- Asymmetric, upstream 20 Mbps.
- Provides 13 W of power.
- Trigger signal - 4 ns resolution.
- Low cost, no royalties.
- Just one coaxial cable! •AIDA annual meeting,Vienna, 26th March 2014
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•Václav Vrba, Institute of Physics,
Prague
Can CoaXPress be used in HEP experiments pixel detectors?
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•Václav Vrba, Institute of Physics,
Prague
CoaXPress for pixel detectors:
- CoaXPress is frame based, good for X-ray imaging applications. Readout with zero suppression (vertex
detector) is possible, but user needs to implement wrapper protocol on top of CXP.
- FPGA soft-core available for a reasonable price.
- CoaXPress needs a PHY ASIC (EQC062T20 ~25$), radiation hardness yet not characterized.
- Currently no rad hard IP cells for direct ASIC integration.
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•Václav Vrba, Institute of Physics,
Prague
What we are aiming at:
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•Václav Vrba, Institute of Physics,
Prague
Block schematic:
FPGAXC6SLX45TSPARTAN 6
DDR3
Boot flashMicro SD card
uPMSP430
2 x Expansion connector 3.125Gbps – 60 pin.
Medipix Quad
[email protected] Low ripple
Power1uA@200V Low ripple
12.8Gbps
6 X LVDS 200Mbps
4 x full duplex 3.125Gbps
4 x LVDS 800Mbps / 8 CMOS< 100Mbps
JTAG
MT41J64M16 1Gbit
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•Václav Vrba, Institute of Physics,
Prague
Final layout of interface card
- 12 copper layers (6 signal, 4 GND reference, 2 power)- FLEX-RIGID technology- class 7 PCB, no buried vias
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•Václav Vrba, Institute of Physics,
Prague
CoaXPress daughter board
Motivation
- Main interface card PCB contains no physical communication layer.- Main interface card PCB can be extended via daughter board. - Daughter board implements physical layer of communication bus.- Communication standards possible - CXP, Ethernet, USB, PCIe...- Daughter board is simple to redesign, cheap & fast to manufacture -> we are flexible.
CoaXPress daugther board designed in May 2013
- Implements CoaXPress PHY, 1 lane 3.1245 Gbps- JTAG debug interfaces- Main system power connector- Debug GPIOs, Reset button, debug LEDs,... - 6 layers PCB.
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•Václav Vrba, Institute of Physics,
Prague
Layout of CoaXPress PHY daughter board
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•Václav Vrba, Institute of Physics,
Prague
PCBs have been manufactured and assembly was done
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•Václav Vrba, Institute of Physics,
Prague
PCBs have been manufactured and assembly was done
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•Václav Vrba, Institute of Physics,
Prague
PCBs have been manufactured and assembly was done
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Testing environment
AIDA annual meeting,Vienna, 26th March 2014 Václav Vrba, Institute of Physics, Prague18
tested with radiation sources
•Václav Vrba, Institute of Physics,
Prague
Current status:
- Designed, manufactured and tested HW of main board and CXP daughter board.
- Developed firmware HDL stack, all subsystems are working and are debugged (DDR3, Coaxpress, Medipix controllers).
- Developed PC side software stack the receive and display the video stream.
- Wirebonded Medipix quad to PCB and made first radiation tests.
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•Václav Vrba, Institute of Physics,
Prague
Show video
uranite (from Joachimsthal, CZ)α – 241Am
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Further steps
AIDA annual meeting,Vienna, 26th March 2014 Václav Vrba, Institute of Physics, Prague21
still one iteration of design of PCB board – it will very flexible for the use of large scale of (practically any) read out chips (- after some coding)
sensor producer tender and sensor prototype production
Thank you
AIDA annual meeting,Vienna, 26th March 2014 Václav Vrba, Institute of Physics, Prague22