High performance parity based low complexity fault detection scheme for the

AES using the S-box

AJAL A JMAIL: ec2reach@gmail.com

Mob: 8907305642

SUNIL RAJAP/ ECE

PRESENTATION OVERVIEW1999

Based on 4 different operations

Based on 4 different operations

S- box S- box analysisanalysis

• INTRODUCTION• RIJNDAEL ALGORITHM• SYSTEM ARCHITECTURE• SIMULATION RESULTS• FUTURE DEVELOPMENT• CONCLUSION

fault detection scheme

Critical N/W Security Elements

identity

authorization availability

integrity

confidentiality

The Rijndael Chip

4

1. Rijndael2. Serpent3. Two fish4. RC 65. MARS

AES 128bit implementation

Selected by AES (Advanced Encryption Standard, part of NIST) as the new private-key encryption standard.

EncryptionPath

DecryptionPath

SubBytes

Inv SubBytes

Inv

Aff

Tra

ns

Mul

t Inv

erse

Aff

Tra

ns

Rijndael S-box consists of two operations

Parallel impletation of S-Boxes

Multiplicative inverse can be shared

Mul

t Inv

erse

Comparison of s- box

Design Area Delay Power

LUT-Based 262144 31.824ns 35mw

Composite Field Based 28514 8.129ns 34mw

Output Waveform for composite field s-box without error

Output wave form of encryption algorithm for composite field s-box without error

Output wave form decryption algorithm for composite field s-box without error

Output wave form decryption algorithm for composite field s-box with error

Map report--------------

• Number of errors: 0• Number of warnings: 0

HDL SYNTHESIS REPORT

Macro Statistics# ROMs : 5616x128-bit ROM : 56# Multiplexers : 668-bit 10-to-1 MUX : 108-bit 16-to-1 MUX : 56# XORs : 171128-bit xor2 : 118-bit xor2 : 1508-bit xor3 : 10

Implementation Encryption Speed

Software implementation (ANSI C) 27Mb/s

Visual C++ 70.5Mb/s

Hardware Implementation (Altra) 268Mb/s

Proposed VHDL (Virtex II) 2.18Gb/s

Performance Comparison

FUTURE WORK

Conclusion

In this paper, a VLSI implementation for the Rijndael encryption algorithm is presented .The combination of security, and high speed implementation, makes it a very good choice for wireless systems

The whole design was captured entirely in VHDL language using a bottom-up design and verification methodology

•An optimized coding for the implementation of Rijndael algorithm for 128 bits has been developed

REFERENCES

[1] S.-Y. Wu and H.-T. Yen, “On the S-box architectures with concurrent error detection for the advanced encryption standard,” IEICE Trans. Fundam. Electron., Commun. Comput. Sci., vol. E89-A, no. 10, pp. 2583–2588, Oct. 2006.

[2] A. E. Cohen, “Architectures for Cryptography Accelerators,” Ph.D. dissertation, Univ. Minnesota, Twin Cities, Sep. 2007.

[3] M. Mozaffari-Kermani and A. Reyhani-Masoleh, “A lightweight concurrent fault detection scheme for the AES S-boxes using normal basis,” in Proc. CHES, Aug. 2008, pp. 113–129.

[4] D. Canright, “A very compact S-box for AES,” in Proc. CHES, Aug. 2005, pp. 441–455.

[5] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, “A compact Rijndael hardware architecture with S-box optimization,” in Proc. ASIACRYPT, Dec. 2001, pp. 239–254.

[6] J.Wolkerstorfer, E. Oswald, and M. Lamberger, “An ASIC implementation of the AES SBoxes,” in Proc. CT-RSA, 2002, pp. 67–78.

[7] V. Rijmen, Dept. ESAT, Katholieke Universiteit Leuven, Leuven, Belgium, Efficient Implementation of the Rijndael S-Box, 2000.

[8] X. Zhang and K. K. Parhi, “High-speed VLSI architectures for the AES algorithm,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. VLSI-12, no. 9, pp. 957–967, Sep. 2004.

[9] X. Zhang and K. K. Parhi, “On the optimum constructions of composite field for the AES algorithm,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, pp. 1153–1157, Oct. 2006.

[10] N. Mentens, L. Batina, B. Preneel, and I. Verbauwhede, “A systematic evaluation of compact hardware implementations for the Rijndael S-box,” in Proc. CT-RSA, Feb. 2005, pp. 323–333.

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