akira lh185s92dt manual de servicio lcd

LH185S92DT SERVICE MANUAL

INDEX:

PART 1Brief Introduction Of The LH185S92DTSchematic Diagram Block Printed Circuit

PART 2: Exploded view

PART 3IC Introduction

PART 4: Detailed Circuit

PART 5: Components List

PART6: Debug Instruction

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

J3CON8 J14

KEY&IR CONNECTOR LVDS CONNECTORAMPLIFER CONNECTOR

SPV7100

PANEL

KEY&IR BOARD

GND R GND L5V IR GND K0 R G GND K1 K2 K3 K4 K5 K6 K7

J4INVERTER CON

NECT

OR12V 12V EN ADJ

GND

GND

INVERTER B

OARD

HDMI PC AVYUV

SCART SVHSPCMCIA

USBTUNER

PCAUDIOINEarphone

Schematic Diagram

Part1:Part1:Part1:Part1:Part1:Part1:Part1:Part1:Part1:

Part1:

Printed CircuitPrinted CircuitPrinted CircuitPrinted CircuitPrinted Circuit

Printed Circuit

TV Main Board (Top View)

TV Main Board Bottom view

IC IntroductionPart3:

Page 1 - 9 Rev. 1.1 May.22, 2007

OCP2030

SWITCHING BUCK REGULATOR General Description The OCP2030 is a buck topology of switching regulator for wide operating voltage applications field. The OCP2030 includes a high current P-MOSFET, high precision reference (0.5V) for comparing output voltage with feedback amplifier, an internal dead-time controller and oscillator for controlling the maximum duty cycle and PWM frequency, and has power-on programmable soft start time and short circuit PMOS turn-off and auto re-start protection functions. Features z Precision feedback reference voltage: 0.5V (2%) z Wide supply voltage operating range: 3.6 to 20V z Low current consumption: 3mA z Internal fixed oscillator frequency: Typ. 360KHz z Programmable Soft-Start function (SS) z Short Circuit Shutdown and Auto Re-start function(ARSCP) z Built-in P-MOSFET for 3A loading capability z Package: SOP8 Pin Configuration

Top View Block Diagram

Name No. Status Description VCC 1 P IC Power Supply (PMOS Source)

SS/SCP 2 I Connecting with a Soft-start & ARSCP timing capacitor IN- 3 I Error Amplifier Inverting Input

FB 4 O Error Amplifier Compensation Output 5 GND 6 P IC Ground

7 LX 8 O PMOS High Current Output

8

7

6

5

1

2

3

4

OCP2030

Oscillator

0.5V500

ReferenceRegulator

36K

85

ThermalShuntdown

6

4

1.25V

1

0.8V

7

3

Soft start&Auto Re-startS.C.P Circuits

2

Output drivecontrol circuits

Philips Semiconductors Product data

CBT3257Quad 1-of-2 multiplexer/demultiplexer

FEATURES 5 switch connection between two ports

TTL-compatible input levels

Minimal propagation delay through the switch

Latch-up protection exceeds 500 mA per JESD78

ESD protection exceeds 2000 V HBM per JESD22-A114,200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

DESCRIPTIONThe CBT3257 is a quad 1-of-2 high-speed TTL-compatiblemultiplexer/demultiplexer. The low on resistance of the switch allowsinputs to be connected to outputs without adding propagation delayor generating additional ground bounce noise.Output Enable (OE) and select-control (S) inputs select theappropriate B1 and B2 outputs for the A-input data.

The CBT3257 is characterized for operation from -40 to +85 C.

PIN CONFIGURATION

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16S

1B1

1B2

1A

2B1

2B2

2A

GND

VCC

OE

4B1

4B2

4A

3B1

3B2

3A

SA00533

PIN DESCRIPTIONPIN NUMBER SYMBOL NAME AND FUNCTION

1 S Select-control input2, 3,5, 6,

10, 11,13, 14

1B1, 1B2,2B1, 2B23B1, 3B24B1, 4B2

B outputs

4, 7, 9, 12 1A, 2A, 3A, 4A A inputs8 GND Ground (0 V)15 OE Output enable16 VCC Positive supply voltage

ORDERING INFORMATIONPACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DWG NUMBER

16-pin plastic SO -40 to 85 C CBT3257D CBT3257D SOT109-116-pin plastic SSOP -40 to 85 C CBT3257DB CT3257 SOT338-116-pin plastic SSOP (QSOP) -40 to 85 C CBT3257DS CBT3257 SOT519-116-pin plastic TSSOP -40 to 85 C CBT3257PW CBT3257 SOT403-1

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.

Si2301BDSVishay Siliconix

P-Channel 2.5-V (G-S) MOSFET

PRODUCT SUMMARY

VDS (V) rDS(on) () ID (A)b

200.100 @ VGS = -4.5 V -2.4

-200.150 @ VGS = -2.5 V -2.0

G

TO-236(SOT-23)

S

D

Top View

2

3

1

Si2301 BDS (L1)*

*Marking Code

Ordering Information: Si2301BDS-T1

ABSOLUTE MAXIMUM RATINGS (TA = 25C UNLESS OTHERWISE NOTED)

Parameter Symbol 5 sec Steady State Unit

Drain-Source Voltage VDS -20V

Gate-Source Voltage VGS 8V

Continuous Drain Current (TJ = 150C)bTA= 25C

ID-2.4 -2.2

Continuous Drain Current (TJ = 150C)bTA= 70C

ID-1.9 -1.8

APulsed Drain Currenta IDM -10

A

Continuous Source Current (Diode Conduction)b IS -0.72 -0.6

Power DissipationbTA= 25C

PD0.9 0.7

WPower DissipationbTA= 70C

PD0.57 0.45

W

Operating Junction and Storage Temperature Range TJ, Tstg -55 to 150 C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambientb

R120 145

C/WMaximum Junction-to-Ambientc

RthJA140 175

C/W

Notesa. Pulse width limited by maximum junction temperature.b. Surface Mounted on FR4 Board, t 5 sec.c. Surface Mounted on FR4 Board.

AP1084

5A Low Dropout Positive Adjustable or Fixed-Mode Regulator

Features 1.4V maximum dropout at full load current Built-in thermal shutdown Output current limiting Adjustable output voltage or fixed 1.5V, 1.8V, 2.5V, 3.3V, 5.0V

Fast transient response Good noise rejection Package : TO252, TO263, TO220 Ordering Information

General Description AP1084 is a low dropout positive adjustable or fixed-mode regulator with minimum of 5.0A output current capability. The product is specifically designed to provide well-regulated supply for low voltage IC applications such as high-speed bus termination and low current 3.3V logic supply. AP1084 is also well suited for other applications such as VGA cards. AP1084 is guaranteed to have lower than 1.4V dropout at full load current making it ideal to provide well-regulated outputs of 1.25 to 3.3V with 4.7 to 12V input supply.

AP1084 X X X X

Low Dropout Regulator Package Vout

D : TO252-3LK : TO263-3LT : TO220-3L

Blank : Adj15 = 1.5V18 = 1.8V25 = 2.5V33 = 3.3V50 = 5.0V

Packing

Blank : TubeA : Taping

Lead Free

Blank : NormalL : Lead Free Package

Typical Circuit

5.0V to 3.3V Fixed Mode Regulator

C2100uF

5V

3.3V/5A

Tab is Vout

Vin

Vout

GND

C1100uF

Adjustable Regulator

R1

R2

C2100uF

5V

2.5V/5A

Tab is Vout

Vin

Vout

Adj

C1100uF

121

121

)1

2REFo R

R(1VV +=Note:

1A Low Dropout Positive Adjustable or Fixed-Mode Regulator

AP1117

Features - 1.4V maximum dropout at full load current - Fast transient response - Output current limiting - Built-in thermal shutdown - Packages: SOT223, TO263, TO252, TO220, SOT89

- Good noise rejection - 3-Terminal Adjustable or Fixed 1.5V, 1.8V, 1.9V, 2.5V, 3.3V, 5.0V

Applications - PC peripheral - Communication

General Description AP1117 is a low dropout positive adjustable or fixed-mode regulator with minimum of 1A output current capability. The product is specifically designed to provide well-regulated supply for low voltage IC applications such as high-speed bus termination and low current 3.3V logic supply. AP1117 is also well suited for other applications such as VGA cards. AP1117 is guaranteed to have lower than 1.4V dropout at full load current making it ideal to provide well-regulated outputs of 1.25 to 5.0 with 6.4V to 12V input supply.

Ordering Information

AP 1117 X XX X X

Low Dropout Regulator Package VoutE : SOT223-3LK : TO263-3LD : TO252-3LT : TO220-3LY : SOT89-3L

Blank : ADJ15 : 1.5V18 : 1.8V19: 1.9V25 : 2.5V33 : 3.3V50 : 5.0V

PackingBlank : TubeA : Taping

Lead Free

Blank : NormalL : Lead Free Package

Typical Circuit

C2100uF

5V

3.3V/1A

Tab is Vout

Vin

Vout

GND

C1100uF

( 5V/3.3V fixed output )

R1121R2

121

C2100uF

5V

2.5V/1A

Tab is Vout

Vin

Vout

Adj

C1100uF

oV

( 5V/2.5V ADJ output )

)1

2REFo R

R(1 VV +=Note:

Advanced Power P-CHANNEL ENHANCEMENT MODE Electronics Corp. POWER MOSFET

Simple Drive Requirement BVDSS -30V Low On-resistance RDS(ON) 50m Fast Switching ID -5.3A

Description

Absolute Maximum RatingsSymbol Units

VDS VVGS VID@TA=25 A

ID@TA=70 AIDM APD@TA=25 W

W/TSTG TJ

Symbol Value UnitRthj-amb Thermal Resistance Junction-ambient3 Max. 50 /W

Thermal DataParameter

Total Power Dissipation 2.5

-55 to 150Operating Junction Temperature Range -55 to 150

Linear Derating Factor 0.02Storage Temperature Range

Continuous Drain Current3 -4.7Pulsed Drain Current1 -20

ParameterDrain-Source VoltageGate-Source VoltageContinuous Drain Current3

AP9435M

Rating-30

-5.3 20

The Advanced Power MOSFETs from APEC provide thedesigner with the best combination of fast switching,ruggedized device design, low on-resistance and cost-effectiveness.

The SO-8 package is universally preferred for all commercial-industrialsurface mount applications and suited for low voltage applicationssuch as DC/DC converters.

SS

SG

DD

DD

SO-8

G

D

S

N o v e m b e r 1 9 9 5

2N7000 / 2N7002 / NDS7002A N-Channel Enhancement Mode Field Effect Transistor

General Description Features

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Absolute Maximum Ratings T A = 25C unless otherwise notedSymbol Parameter 2N7000 2N7002 NDS7002A Units

V DSS Drain-Source Voltage 60 V

V DGR D r a i n - G a t e V o l t a g e ( R G S < 1 M W ) 60 V

V GSS Gate-Source Voltage - Continuous 20 V

- Non Repetitive (tp < 50s) 40I D Maximum Drain Current - Continuous 200 115 280 m A

- Pulsed 500 800 1500

P D Maximum Power Dissipation 400 200 300 m W

Derated above 25 o C 3.2 1.6 2.4 m W / C

T J , T STG Operating and Storage Temperature Range -55 to 150 -65 to 150 C

T L Maximum Lead Temperature for SolderingP u r p o s e s , 1 / 1 6 " f r o m C a s e f o r 1 0 S e c o n d s

300 C

THERMAL CHARACTERISTICS

R qJ AT h e r m a l R e s i s t a n c e , J u n c t i o n - t o - A m b i e n t 312.5 625 417 C / W

These N -C h a n n e l e n h a n c e m e n t m o d e f i e l d e f f e c t t r a n s i s t o r sare produced using Fairchild's proprietary, high cell density,DMOS technology. These products have been designed tominimize on-state resistance while provide rugged, reliable,and fast switching performance. They can be used in mostapplications requiring up to 400mA DC and can deliverpulsed currents up to 2A. These products are particularlysuited for low voltage, low current applications such as smallservo motor control, power MOSFET gate drivers, and otherswitching applications.

High density cell design for low R DS(ON) .

V o l t a g e c o n t r o l l e d s m a l l s i g n a l s w i t c h .

Rugged and reliable.

High saturation current capability.

S

D

G

SG

D

TO-92 2N7000

(TO-236AB) 2N7002/NDS7002A

Philips Semiconductors Product specification

2 6 W stereo power amplifier TDA1517; TDA1517P

FEATURES Requires very few external components High output power Fixed gain Good ripple rejection Mute/standby switch AC and DC short-circuit safe to ground and VP Thermally protected Reverse polarity safe Capability to handle high energy on outputs (VP = 0 V) No switch-on/switch-off plop Electrostatic discharge protection.

GENERAL DESCRIPTIONThe TDA1517 is an integrated class-B dual outputamplifier in a plastic single in-line medium power packagewith fin (SIL9MPF) and a plastic heat-dissipating dualin-line package (HDIP18). The device is primarilydeveloped for multi-media applications.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITVP supply voltage 6.0 14.4 18.0 VIORM repetitive peak output current 2.5 AIq(tot) total quiescent current 40 80 mAIsb standby current 0.1 100 AIsw switch-on current 40 A|ZI| input impedance 50 kPo output power RL = 4 ; THD = 0.5% 5 W

RL = 4 ; THD = 10% 6 WSVRR supply voltage ripple rejection fi = 100 Hz to 10 kHz 48 dBcs channel separation 40 dBGv closed loop voltage gain 19 20 21 dBVno(rms) noise output voltage (RMS value) 50 VTc crystal temperature 150 C

TYPENUMBER

PACKAGE

NAME DESCRIPTION VERSIONTDA1517 SIL9MPF plastic single in-line medium power package with fin; 9 leads SOT110-1TDA1517P HDIP18 plastic heat-dissipating dual in-line package; 18 leads SOT398-1


2 6 W stereo power amplifier TDA1517; TDA1517P

PINNING

SYMBOL PIN DESCRIPTIONINV1 1 non-inverting input 1SGND 2 signal groundSVRR 3 supply voltage ripple rejection outputOUT1 4 output 1PGND 5 power groundOUT2 6 output 2VP 7 supply voltageM/SS 8 mute/standby switch inputINV2 9 non-inverting input 2

Fig.2 Pin configuration for SOT110-1.

ndbook, halfpage

MLC352

1

2

3

4

5

6

7

8

9

PV

OUT2

SGND

INV1

INV2

TDA1517

OUT1

M/SS

SVRR

PGND

Fig.3 Pin configuration for SOT398-1.

Pins 10 to 18 should be connected to GND or floating.

ndbook, halfpage

MLC353

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

PV

OUT2

SGND

INV1

INV2

TDA1517P

OUT1

M/SS

SVRR

PGND

FUNCTIONAL DESCRIPTIONThe TDA1517 contains two identical amplifiers withdifferential input stages. The gain of each amplifier is fixedat 20 dB. A special feature of the device is themute/standby switch which has the following features: Low standby current (

and

FT24C02 / 04 / 08 / 16 Fremont Micro Devices, Inc. FT24C02A / 04A / 08A / 16A FEATURES

Low voltage and low power operations: FT24C02/04/08/16: VCC = 2.5V to 5.5V FT24C02A/04A/08A/16A: VCC = 1.8V to 5.5V

Maximum Standby current < 1A (typically 0.02A and 0.06A @ 1.8V and 5.5V respectively). 16 bytes page write mode. Partial page write operation allowed. Internally organized: 256 8 (2K), 512 8 (4K), 1024 8 (8K), 2048 8 (16K). Standard 2-wire bi-directional serial interface. Schmitt trigger, filtered inputs for noise protection. Self-timed programming cycle (5ms maximum). Automatic erase before write operation. Write protect pin for hardware data protection. High reliability: typically 800,000 cycles endurance. 100 years data retention. Industrial temperature range (-40o C to 85o C). Standard 8-pin PDIP/SOIC/TSSOP Pb-free packages.

DESCRIPTION The FT24C02/04/08/16 series are 2048/4096/8192/16384 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 256/512/1024/2048 words of 8 bits (1 byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications.

PIN CONFIGURATION

Pin Name Pin Function A2, A1, A0 Device Address Inputs

SDA Serial Data Input / Open Drain Output SCL Serial Clock Input WP Write Protect NC No-Connect

All three packaging types come in conventional or Pb-free certified.

Rev. 0.03 /Jun. 2006 3

HY5DU281622FT(P) Series

DESCRIPTION

The HY5DU281622FT(P) is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for themain memory applications which requires large memory density and high bandwidth.

This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of theclock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatiblewith SSTL_2.

FEATURES

VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333)

VDD, VDDQ = 2.4V min ~ 2.7V max (Typical 2.6V Operation +0.1/- 0.2V for DDR400 and 400Mbps/pin product)

All inputs and outputs are compatible with SSTL_2 interface

Fully differential clock inputs (CK, /CK) operation

Double data rate interface

Source synchronous - data transaction aligned to bidirectional data strobe (DQS)

x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O

Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)

On chip DLL align DQ and DQS transition with CK transition

DM mask write data-in at the both rising and falling edges of the data strobe

All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

Programmable CAS latency 2/2.5 (DDR266, 333) and 3 (DDR400 and 400Mbps/pin product) sup-ported

Programmable burst length 2/4/8 with both sequen-tial and interleave mode

Internal four bank operations with single pulsed /RAS

Auto refresh and self refresh supported

tRAS lock out function supported

4096 refresh cycles/64ms

JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch

Lead free (*ROHS Compliant)

ORDERING INFORMATION

* X means speed grade** Lead-free product

Part No. Configuration Package

HY5DU281622F(L)TP-X* 8Mx16400mil66pin

TSOP-II**

OPERATING FREQUENCY

Grade Clock Rate Remark

-5 200MHz@CL3400Mbps/pin (maxi-

mum Date rate)

-D43 200MHz@CL3 DDR400B (3-3-3)

-D4 200MHz@CL3 DDR400 (3-4-4)

- J 133MHz@CL2166MHz @CL2.5

& @CL3DDR333 (2.5-3-3) DDR333 (3-3-3)

- K 133MHz@CL2 [email protected] DDR266A (2-3-3)

- H 100MHz@CL2 [email protected] DDR266B (2.5-3-3)*ROHS (Restriction Of Hazardous Substances)

Rev. 0.03 /Jun. 2006 4

HY5DU281622FT(P) Series

PIN CONFIGURATION

ROW AND COLUMN ADDRESS INFORMATION

Organization : 2M x 16 x 4banks

Row Address : A0 - A11

Column Address : A0 - A8

Bank Address : BA0, BA1

Auto Precharge Flag : A10

Refresh : 4K

123456789101112131415161718192021222324252627282930313233

666564636261605958575655545352515049484746454443424140393837363534

400mil x 875mil66pin TSOP-II

0.65mm pin pitch

VDDDQ0

VDDQDQ1DQ2

VSSQDQ3DQ4

VDDQDQ5DQ6

VSSQDQ7NC

VDDQLDQS

NCVDDNC

LDM/WE/CAS/RAS/CSNC

BA0BA1

A10/APA0A1A2A3

VDD

VSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8NCVSSQUDQSNCVREFVSSUDM/CKCKCKENCNCA11A9A8A7A6A5A4VSS

4

DEFINITION OF TERMINALS / SUPPLY DATA

CDT-9DT33C-00,CDT-9DT23C-00 , CDT-9DT13C-00

Terminal Function Remark

1 DC-power option for tuners with P-extension Max. permissible current: 100mA

2 External RF-gain control voltage (0.5V - 4.0V) Source impedance limited to 1kohms 3 PLL chip address select (I2C / tuner) see application notes 4 SCL (I2C / tuner) 5 SDA (I2C / tuner) 6 4MHz reference frequency output; AC coupled 7 +5V r 5% supply tuner (VTU)8 'broadband' IF - output AC coupled

9 IF-gain control voltage max. gain at 3V min. gain at 0V (see application notes)

10 'narrowband' IF - output AC coupled 11 'narrowband' IF - output AC coupled

1110

98

7 12

34

56

.

.

.

.

MODELCDT-9DT33C-00


Dual 4-channel analog multiplexer,demultiplexer 74HC4052; 74HCT4052

FEATURES Wide analog input voltage range from 5 V to +5 V Low ON-resistance:

80 (typical) at VCC VEE = 4.5 V 70 (typical) at VCC VEE = 6.0 V 60 (typical) at VCC VEE = 9.0 V

Logic level translation: to enable 5 V logic tocommunicate with 5 V analog signals

Typical break before make built in Complies with JEDEC standard no. 7A ESD protection:

HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.

Specified from 40 C to +85 C and 40 C to +125 C.

APPLICATIONS Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating.

DESCRIPTIONThe 74HC4052 and 74HCT4052 are high-speed Si-gateCMOS devices and are pin compatible with theHEF4052B. They are specified in compliance with JEDECstandard no. 7A.

The 74HC4052 and 74HCT4052 are dual 4-channelanalog multiplexers or demultiplexers with common selectlogic. Each multiplexer has four independentinputs/outputs (pins nY0 to nY3) and a commoninput/output (pin nZ). The common channel select logicsinclude two digital select inputs (pins S0 and S1) and anactive LOW enable input (pin E). When pin E = LOW, oneof the four switches is selected (low-impedance ON-state)with pins S0 and S1. When pin E = HIGH, all switches arein the high-impedance OFF-state, independent of pins S0and S1.VCC and GND are the supply voltage pins for the digitalcontrol inputs (pins S0, S1, and E). The VCC to GNDranges are 2.0 V to 10.0 V for 74HC4052 and4.5 V to 5.5 V for 74HCT4052. The analog inputs/outputs(pins nY0 to nY3 and nZ) can swing between VCC as apositive limit and VEE as a negative limit. VCC VEE maynot exceed 10.0 V.

For operation as a digital multiplexer/demultiplexer, VEE isconnected to GND (typically ground).

FUNCTION TABLE

Note1. H = HIGH voltage level

L = LOW voltage levelX = dont care.

INPUT(1)CHANNEL BETWEEN

E S1 S0L L L nY0 and nZL L H nY1 and nZL H L nY2 and nZL H H nY3 and nZH X X none

or modifications due to changes in technical specifications. Rev. E, Issue Date: 2007/5/3

PPrreelliimmiinnaarryy

SPV7100A

HIGHLY INTEGRATED LCD TV PROCESSOR

1. GENERAL DESCRIPTION The SPV7100A is a highly integrated solution for the mainstream

LCD TV applications. The SPV7100A provides on-chip functions

including a high-speed triple-ADC and PLL, HDMI PanelLinkTM

Cinema receiver, TV decoder with 3-D comb filter, 4-pair Audio

Line-In, 2-pair Audio Line-Out, one SIF demodulator and audio

decoder, 3D motion adaptive de-interlacing, 2:2/3:2 film mode

detection, video on graphic PIP/POP, SDRAM/DDR controller,

color management control, sRGB color management,

bitmap-based and font-based OSD engine, embedded CPU and a

dual channels LVDS transmitter. The chip could support LCD TV

up to 1080P input resolution and 1080p output resolution.

Note: PanelLink is the Trade Mark of Silicon Image Inc.

2. FEATURES 2.1. Graphics and Video Input Port

Integrate 150MHz 10-bit ADC/PLL Dual CCIR656 digital video ports to support 2 input or 1 input/1

output

Support SDTV at 480i/576i and 480p/576p Support HDTV at 720p and 1080i and1080p Support PC graphics VGA, SVGA, XGA, WXGA, SXGA@75Hz

(135MHz)

Build-in sync. processor for separate, composite or sync on Y/G

Support Video/Graphics PIP/DW Channel swap for any source input Image Format Detection/Auto Image Positioning/Auto Phase

Detection

Full SCART support including RGB fast blank

2.2. HDMI

HDMI 1.2 compliant and DVI 1.0 compliant receiver HDCP 1.1 compliant receiver Support DTV resolutions

(480i/576i/480p/576p/720p/1080i/1080p)

S/PDIF output supports PCM, Dolby Digital, DTS digital audio with bypass mode

Four I2S audio outputs to SSD(Stereo Sound Decoder) with bypass mode

Auto audio error detection with programmable soft mute Build-in OTP for HDCP key

2.3. 3D Video Decoder

NTSC/PAL/SECAM video decoder 3D comb filter for NTSC, PAL I (B,G,H,D,N), PAL-M, PAL-N Enhanced NTSC/PAL/SECAM auto detection 4 analog inputs and one analog video output Cross-color reduction for NTSC by 3-line comb filtering Cross-color reduction for PAL by 5-line comb filtering Motion adaptive 3D Y/C separation comb filter for NTSC/PAL

system

Multi-standard VBI data decoder, Teletext 2.5, WSS, VPS, Closed-caption and V-chip

Macrovision detection VBI data (C.C, TTX2.5, V-chip) overlay display

2.4. High Quality Video Processing

Enhanced Pixel-based 3D motion adaptive de-interlacing (SDTV/HDTV)

Enhanced 2:2/3:2 film mode detection Support Graphics mode frame rate conversion Support Video mode frame rate conversion 2D Edge enhancement Dynamic Peaking Filter Enhanced Digital Luminance Transient Improvement (DLTI) Digital Color Transient Improvement (DCTI) Black/White Level Expansion and Dynamic Contrast RGBYMC color adjustment Dark and Gray area UV Suppression Enhanced 3D motion adaptive noise reduction De-blocking and de-mosquito filters Color management/Color temperature adjustment Brightness/Contrast/hue/Saturation adjustment Support sRGB color correction Build-in three 256-point gamma tables with 10 bits resolution Color space conversion, both YCbCr to RGB and RGB to

YCbCr

Build-in temporal/spatial color dithering 10-bit video/image processing

2.5. High Quality Video Scaling Engine

Advanced third-generation scaling engine Support 4:3 / 16:9 with non-linear scaling Support Moir Canceling

PPrreelliimmiinnaarryy

SPV7100A

Sunplus Technology Co., Ltd. Proprietary & Confidential

5 MAR. 23, 2007Preliminary Version: 0.1

2.6. Multi-standard TV Sound Decoder

Field proven TV sound decoder Support BTSC, A2/Zweiton, NICAM, EIAJ, SECAM, FM stereo Automatic TV-standard detection (ASD) Non-standard carrier compatible SAP decoding where applicable Auto fallback from NICAM where applicable

2.7. Embedded OSD and VBI Controller

Build-in programmable OSD engine for two OSD windows (bit map OSD)

1,2,4 and 8-bit per pixel (bit-map OSD) Support hardware cursor Support programmable 512 font-based OSD and

graphics-based OSD

Support VBI decoder (CC,V-Chip and Teletext) Support VBI CC/TTX/Menu with more than 1000 char-fonts

2.8. Embedded DDR/SDRAM Controller

Integrated DDR/SDRAM controller with DLL (DDR) Support 32-bit DRAM bus with memory size from 16Mb (limited

functions) to 256Mb

2.9. Programmable Digital Output for LCD

Support output sequence mapping for TI and Thine Build-in dual channels 8-bit LVDS Tx or single channel 10-bit

LVDS Tx

Support display output up to 1920x1200 @60Hz (165Mhz WUXGA reduced blanking)

Support Power Down Sequence 4-ch PWM backlight intensity control

2.10. CPU

Powerful 32-bit RISC CPU Simple memory management stub (SMMU)

MIPS-I instruction with DSP instruction set extension 2K bytes 2-way instruction cache 4K bytes direct-mapped data cache 8K bytes data memory for DMA operation EJTAG interface One UART up to 115200 baud rate Four 24-bit up/down timers 3K Bytes IMem for power saving mode

2.11. Audio Processor

Support SPDIF input Support SPDIF output (signal could come from SPDIF input or

SSD)

Support up to 8 channels I2S I/O 4 channels audio DAC output 4 channels audio ADC input Channel: L, R, C, S, Sub, Aux1, 2 and 3 @ 32 kHz 5- band Equalizer 3-D surround sound Bass management Volume control Support sub-woofer output Sample rate conversion SSD could output up to 3 sources Virtual Dolby Surround (VDSII 422 and 423) (support by

SPV7100AxD)

SRS TruSurround (XT, WOW, 3D Sound) (support by SPV7100 AxS)

2.12. Misc

Build-in TV remote control 1 infra-red receiver interface 2-channels 6-bits ADC for key scan function Build-in pattern generator for auto testing 256-pin LQFP for LCD application

SPV7100A

4.3. List of Packages and Pins

4.3.1. 256- LQFP Package

Figure 4-1 SPV7100A Pin Configuration

SPV7100A

4.3. List of Packages and Pins

4.3.1. 256- LQFP Package

Figure 4-1 SPV7100A Pin Configuration

This Data Sheet may be revised by subsequent versions 2004 Eon Silicon Solution, Inc., www.essi.com.tw or modifications due to changes in technical specifications.

1

EN25B16

Rev. C, Issue Date: 2006/12/22

FEATURES x Single power supply operation - Full voltage range: 2.7-3.6 volt

x 16 M-bit Serial Flash - 16 M-bit/2048 K-byte/8192 pages - 256 bytes per programmable page

x High performance - 75MHz clock rate

x Low power consumption - 5 mA typical active current - 1 PA typical power down current

x Flexible Sector Architecture: - Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one

32-Kbyte, and thirty one 64-Kbyte sectors

x Software and Hardware Write Protection: - Write Protect all or portion of memory via

software - Enable/Disable protection with WP# pin

x High performance program/erase speed - Byte program time: 7s typical - Page program time: 1.5ms typical - Sector erase time: 300 to 800ms typical - Chip erase time: 18 Seconds typical

x Minimum 100K endurance cycle

x Package Options - 8 pins SOP 200mil body width - 8 contact VDFN - 16 pin SOP 300mil body width - All Pb-free packages are RoHS compliant

x Commercial and industrial temperature Range

GENERAL DESCRIPTION

The EN25B16 is a 16M-bit (2048K-byte) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.

The EN25B16 has thirty six sectors including thirty one sectors of 64KB, one sector of 32KB, one sector of 16KB, one sector of 8KB and two sectors of 4KB. This device is designed to allow either single Sector at a time or full chip erase operation. The EN25B16 can protect boot code stored in the small sectors for either bottom or top boot configurations. The device can sustain a minimum of 100K program/erase cycles on each sector.

EN25B16 16 Mbit Serial Flash Memory with Boot and Parameter Sectors


2

EN25B16


Figure.1 CONNECTION DIAGRAMS

8 - CONTACT VDFN8 - LEAD SOP

16 - LEAD SOP


3

EN25B16


Figure 2. BLOCK DIAGRAM

SDRAM 64Mb H-die (x4, x8, x16) CMOS SDRAM

Rev. 1.5 February 2004

Part No. Orgainization Max Freq. Interface Package K4S640432H-TC(L)75 16Mb x 4 133MHz(CL=3)

LVTTL 54pin TSOP(II) K4S640832H-TC(L)75 8Mb x 8 133MHz(CL=3) K4S641632H-TC(L)60

4Mb x 16166MHz(CL=3)

K4S641632H-TC(L)70 143MHz(CL=3) K4S641632H-TC(L)75 133MHz(CL=3)

The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNGcs high perfor-mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possibleon every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device tobe useful for a variety of high bandwidth, high performance memory system applications.

JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM (x4,x8) & L(U)DQM (x16) for masking Auto & self refresh 64ms refresh period (4K cycle)

GENERAL DESCRIPTION

FEATURES

Ordering Information

4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks SDRAM

Row & Column address configuration

Organization Row Address Column Address16Mx4 A0~A11 A0-A9

8Mx8 A0~A11 A0-A8

4Mx16 A0~A11 A0-A7



11.7

6r0.

20

0.46

3r0.

008

0.0020.05 MIN

0.0080.21

r0.002r0.05

0.02

00.

50(

)

0.005 -0.001+0.0030.125 -0.035

+0.075

0.40

010

.16

0.45

~0.7

50.

018~

0.03

0

0.0100.25 TYP

0~8qC

#54 #28

#1 #27

0.0040.10 MAX

0.0280.71

( )0.012 0.30

0.03150.80

0.0471.20 MAX0.039

1.00r0.004r0.10

0.89122.62 MAX

0.87522.22

r0.004

r0.10

+0.10-0.050.004-0.002

54Pin TSOP(II) Package Dimension

Package Physical Dimension



FUNCTIONAL BLOCK DIAGRAM

Bank Select

Data Input Register

4M x 4 / 2M x 8 / 1M x 16

4M x 4 / 2M x 8 / 1M x 16

Sense A

MP

Output B

ufferI/O

Control

Column Decoder

Latency & Burst Length

Programming Register

Address R

egister

Row

BufferR

efresh Counter

Row

Decoder

Col. Buffer

LRA

S

LCB

R

LCKE

LRAS LCBR LWE LDQM

CLK CKE CS RAS CAS WE L(U)DQM

LWE

LDQM

DQi

CLK

ADD

LCAS LWCBR

4M x 4 / 2M x 8 / 1M x 16

4M x 4 / 2M x 8 / 1M x 16

Timing Register

Samsung Electronics reserves the right to change products or specification without notice. *

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AOUT1R

AOUT1L

MUTE_AMP

+12V_IN

AOUT1L

MUTE_C

AOUT1R

PHONE_OUTR

PHONE_OUTL

HPD_ PHONE

MUTE_C

MUTE_AMP

AOUT1R

AOUT1L

A_ POWER

MUTE_C

SPEAKER_LOUT

SPEAKER_ROUT

R IN

SPEAKER_ROUT

SPEAKER_LOUT

AOUT1_RAOUT1R

AOUT1_LAOUT1L

MUTE_AMP

LIN

HPD_ PHONE

+12V_IN

+12V_IN1,5,10

G ND1 ,2 ,3,4,5,6,7,8,9,10,12,13,14,15

+12V_IN1,4,9

G ND1 ,2 ,3,4,5,6,7,8,9,10

+12V_IN

+12V_IN

PVCC6

PVCC12

GND_AMP

PVCC6

PVCC12

PVCC12 PVCC6+12V_IN

GND_AMP

+12V_IN

GND_AMPGND_AMP

+12V_IN

GND_AMP

GND_AMP

GND_AMP

G ND

G ND

G ND

+12V_IN

GND_AMP

GND_AMP

GND_AMP

GND_AMP

GND_AMP

GND_AMP

GND_AMP

GND_AMP

+12V_IN

GNDTA

GNDTA

GNDTA

GNDTAGNDTA

GNDTA

GNDTA

GNDTA

+5VSB1

AOUT1R7

AOUT1L7

MUTE_AMP7

AOUT1R6

AOUT1L6

MUTE_AMP6

MUTE_AMP7

SPEAKER OUT

SPEAKER OUT

PHONE OUT

+

EC88NC/4 7uF16V

+ E147uF

C367

10uF

R449NC/8.2K

C357100pF

Q592N3904

R379N C

12

R283 75R

R26810R

EC76220uF/16V

C3680.1uF

C36410uF

R451470

U27

TDA1517P

-INV11

SGND2

SVRR3

OUT14

PGND5

OUT26

VP7

M/SS8

-INV29

GND10 GND 11GND 12GND 13GND 14GND 15GND 16GND 17GND 18GND 19GND 20s

ink

21si

nk22

R46110R

R447100K

J14

DIP /P IN4/2.0

1234

EC78220uF/16V

R454470K

R3846.8K

12

C3521uF

R46447K

R450470K

D60BAV99L

31 2

R4581K

+ EC8710uF16V

C3632.2uF

EC79470uF/16V

R284

20K

R140R

D2

1N4148

D-1206

1 2

R44547k

1 2

+

-

U6BNJM4558

5

67

84

R4678.2K

Q602N3904

R45947K

R456100K

R441 0

C371NC/10uF

C3512.2uF

R442nc

12

R498220

+

-

U6ANJM4558

3

21

84

Q632N3906 3

2

1

R466 10K

R90R

C366

10uF

R460 10K

+ EC802.2uF

R440NC/8.2K

C3501uF

R45522K

C1010nF

C362

820pF

R44347k

12

R44422K

C361

1uF

R465 20K

CON9PHONE

12345

C360100pF

R4461k

1 2

C36510uF

C1110nF

C359820pF

R2821K

Q622N3904

R29

2K

Q612N3904

EC75100uF/16V

R448 0

C358

1uF

R462100K

R457100K

R463100K

PDF "pdfFactory Pro" www.fineprint.cn

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+3V3

+1V8

+5VSB

+5V_SW

+12V_IN

POWER_ONPOWER_ON

STB_CONPICVPP

SCL_M

SDA_M

SCL_MSDA_M

RTC_inter

STB_CON

STB_CON

STB_AC_ON

SCL_M

SDA_M

STB_AC_ON

POWER_ON

DVD_ POWER_SW

+3V3 2,3,7,8,9,10,13,14,15

+1V8 8

+5VSB 5,9,10,13

+12V_IN 5,10,11

+5V_SW 3,4,12,13,15

GND 2 ,3 ,4,5,6,7,8,9,10,11,12,13,14,15

+12V_IN

+2V5+5VSB

+3V3

+1V8

+5VSB

+12V_IN

+5V_SW

GND_ PWRGND_TMDSGNDV

+5VSB +3V3

+1V8_ADCA

+1V8

+5V_SW

+5V_DC +3V3

+12V_IN

+5VSB

+5V_DC +5VSB

+3V3_SW7100

+3V3_SW7100

+5VSB1

+5V_SW_1003+3V3

+3V3_SW_1003

GND

+5VSB1

+12V_power

G ND

+5VSB1

+12V_IN

+5V_USB

+5VSB1

+5VSB1

+5V_DC

+12V_power

+5VSB1 +5V_DC

+12V_DVD

+12V_power

+5V_DVD

+12V_power

+5V_USB

+5V_DVD

+12V_DVD+5V_USB

G ND

G ND

GND

G ND

G ND

MCU_IOIR

STB_CON 7

SCL_M 7

SDA_M 7KPD_ POWER

STB_AC_ON7

POWER_ON7

DVD_ POWER_SW7

Title

Size Do cu ment Number R e v

Date: Sheet o fSPTV05-13-V1 1.0

System PowerC

1 15Monday, April 13, 2009

SUNPLUS

FOR SPV7100 ONLY 3.3V 1.8V 2.5V

10/26 Add

11/30 Modify

RTC

RTC

close

R7100K

R568

1.3K

C770.1uF

R3191.3K

R53nc/100K

C12

10uF

C402

1uF

+

EC8

10uF/16V

C7

0.1uF

L2 22uH/2A

U28

XS3045

VDD1

GP5/T1CKI/OSC1/CLKIN2

GP4/AN3/T1G/OSC2/CLKOUT3

GP3/MCLR/VPP4

GP2/AN2/T0CKI/INT/COUT 5GP1/AN1/CIN-/VREF/ICSPCLK 6

GP0/AN0/CIN+/ICSPDAT 7VSS 8

R1247K

R567100K

R43 130

U1AX3101

VCC4

OCSET3 EN

2

VS

S7

FB 1

OUTPUT 5

OUTPUT 6

VS

S8

Q722N3904

C2200.1uF

C404

1uF

C14

0603-10nF

+EC21

470uF/16V

R318

6.8K

C218

10uF EC52

2200uF/16V

C40.1uF

R143220R+ EC33

100uF/16V

R50110k

Q12N3904

1

2

3

R55447K

R52347K

R44 120

EC63

470uF/25V

R52100K

R437N C

U30

AMI8563

X11

X22

/INTA3GND4 SDA 5

SCL 6SQW/INTB 7

VCC 8

D3SK34/SOPD-2216

R481K

R3203.9K

C4090.1uF

R41390

R262.2R

Q23AP2301

2

31

R13N C

R51110K

R505 10

U2978D05

in1 out 3

GN

D2

GN

D4

R525 33R

R471K

R138100R

O U T

A D J

I N UP3AP1084-3V3/256TOP-263+3.3V Regulator

3

2

1

4

R52133

EC37470uF/25V

R1271K

L19 NC/2 2uH/3A_12mmX12mm

ADJ/GND

O U T

I NUP2

AP1117-ADJ/SOT-223SOT-223

3

2

1

4

C3941uF

C3850603-10nF

R33

2K

R488100K

CN27

CON6 /2.0mm

123456

C22

10uF

+EC10

470uF/16V

U4AX3101

VCC4

OCSET3 EN

2

VS

S7

FB 1

OUTPUT 5

OUTPUT 6

VS

S8

C5

NC/0 603-10nF

C4061uF

C2210.1uF

C17NC/0603-10nF

R504 10

Q712N3904

C3951uF

Q73NC/2 N3904

SOT-23

1

2

3

R23 47K

Q15AP2301SOT-23

2

31

C190.1uF

D5SK34

Q42N3904

1

2

3

D33SK34/SOPD-2216

C4101000pF

R4380ohm-0805

R5071K

R50010k

R27NC/2 .2R

C20.1uF

Q742N3904

R25

NC/2 .2R

R551 NC/1K

L5NC/OR

Q3AP2301SOT-23

2

31

R556NC/47K

L18NC/0 R

Q682N3906

3

2

1

C2220.1uF

Q2AP2301SOT-23

2

31

EC9

470uF/16V

L46

22uH/4A

1 2

R553100K

+ EC34

100uF/16V

R51210K

EC62

470uF/25V

R581K

C2174.7nF

R61K3

R52033

Y132.768KHz

CN3DC-JACK-2mm

123

R5551K

F15A/12V

R5661K3

+ EC12

100uF/16V

C11000pF

C397 20pF

R45 47K

R4247K

L20

22uH/4A

1 2

L4222uH/2A1 2

O U T

A D J

I N

UP41117-ADJSOT-223

3

2

1

4

C24

2.2uF

R4392K2

R5706.8K

C N2

DIP /P IN4/2.0

1234

U21

FSP3131/AP1510

VCC4

OCSET3 EN

2

VS

S7

FB 1

OUTPUT 5OUTPUT 6

VS

S8

R50947K EC50

470uF/25V

R52447K

R447K

C396 20pF

C37

0.1uF

Q70

NDS9435A/SO

2345 76 8

1

R50810K


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RXM1

RXP1

RXCM

RXP2

RXM2

RXM0R XCP

RXP0

RXM1RXP1

RXM2RXP2

RXCM

RXM0

R XCP

RXP0

/WP

P C-GIN

SCL_VGA2

P C -RIN R_ IN

G _IN

PC-BIN

P C -RIN

VS_VGA

P C-GIN

P C -RIN

HS_VGA

B _INPC-BIN

SDA_VGASCL_VGA

VS_VGAHS_VGA

G _IN

R_ IN

B _IN

SOG_IN

PC-BIN

P C-GIN

VGA_BIN

VGA_GIN

VGA_RIN

SDA_VGA2

ISP_TRAP

+5V_DDC

SCL_VGA/WP

SCL_VGA2SDA_VGA2

RXP2 RXM2 RXP1 RXM1

RXP0 RXM0 R XCP RXCM

ASCL

ASDA

ISP_TRAP

HOLD_FLASH

HPD_PC

/WP

+5V_DC

+3V3

ASCL

HPD_PC

ASDA

H PD_HDMI

ASCLASDA

SDA_VGA

+3V3 1,3,7,8,9,10,13,14,15

+5V_DC 1,3,9,10,13

G ND 1,3,4,5,6,7,8,9,10,11,12,13,14,15

GND_CASE

+5V_HDMI_A

+5V_DC

+5V_HDMI_A

GND_TMDSGND_TMDS

+5V_VGA

G ND_ADC

G ND_ADC G ND_ADC

G ND_ADC

G ND_ADC

G ND_ADC

GND_TMDS

G ND_ADCG ND_ADC

G ND_ADC

G ND_ADCG ND_ADC

G ND_ADC

+5V_DDC

+5V_DC

+5V_VGA

G ND_ADC G ND_ADC

GND_TMDS GND_TMDS GND_TMDS GND_TMDS

GND_TMDS GND_TMDS GND_TMDS GND_TMDSGND_TMDS

GND_TMDS

GND_CASE GND_TMDS GND_TMDSG ND_ADCGND_CASE

+3V3

G ND_ADCG ND_ADC

+3V3

+5V_DC

+5V_DDC

5v_hdmi

G ND_ADC

G ND_ADC

5v_hdmi

GND_TMDS

5v_hdmi

RXP0 7RXM0 7RXP1 7RXM1 7RXP2 7RXM2 7RXCP 7RXCM 7

SCL_VGA 7SDA_VGA 7VS_VGA 7HS_VGA 7

B _IN 7G _IN 7

R_ IN 7

TXD 7,9RXD 7,9

SOG_IN 3,7

WP# 9

HOLD_FLASH 7

HPD_PC 7

/WP 7

SDA_HDMI 7

SCL_HDMI 7

HPD_HDMI7

Title

Size Document Number R e v


HDMI SwitchCustom

2 15Friday, April 03, 2009

SUNPLUS

INPUT1differential impedance 100ohmLayout Note

EDID Defult: NOT write protect

VGA Analog Input

HDMI Input

PC DDC

ISP FROM VGA

10/25 Modify

DM21N C

R30075R

R252 100

C1520.01uF

R26322R

DM8N C

R309 N C

R114100K

R1594.7K

D6 BAT54C

32

1

FB34

L-060330ohm/100MHz

1 2

DM22N C

R253 100

Q341N7002

1

2

3

DM4N C

R311 10K

R2542K2

R199 100

R208 100

R296

1K

DM7N C

R298nc

R264 22R

R324 33

C213

NC/22pFR2512K2

R211 100R

R209 100R

R206510

DM3N C

D13

5.6V

12

CN5VGA/CON

VGA Con.DSUB 15Pin-3/Female

4

3

2

111

12

13

14

15

6

7

8

9

105

16 17

R207510

D29

BAT54C

32

1

R136

100K

R325 33

C214

NC/22pF

DM10N C

DM6N C

R313100K

D11

nc

12

R15810K

D28

nc

12

R323NC/10K

R30275R

DM9N C

DM2N C

C212

NC/22pF

Q351N7002

1

2

3

R30175R

R210 100R

R1604.7K

U19

24C02DDC EDID DataSOP 8Pin

A01 VCC 8A12 WP 7A23 SCL 6GND4 SDA 5

DM5N C

C149

N C

U14 24C02

A0 1A1 2A2 3

VSS 4SDA5SCK6WP7VCC8

DM20N C

C150

N C

FB35

L-060330ohm/100MHz1 2

FB36

L-060330ohm/100MHz

1 2

Q222N3904

1

2

3

CN4

HDMI CON-SMT

SHELL120SHELL221 D2+ 1

D2 Shield 2D2- 3D1+ 4

D1 Shield 5D1- 6D0+ 7

D0 Shield 8D0- 9

CK+ 10CK Shield 11

CK- 12CE Remote 13

NC 14DDC CLK 15

DDC DATA 16GND 17+5V 18HPD 19SHELL322

SHELL423

D27

nc

12

C105 1uF

C1510.01uF

DM1N C

R2971K

C184

1uF

C1530.01uF

D12

5.6V

12

R105 10K


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SOG_IN

SOY2_IN

AOUT0RAOUT0L

SC1 _AU_ROUT

SC1 _ AU_LIN

SC1_AU_LOUT

av_1_out

SC1 _ AU_RIN

CVBS2_INav_1_in

SC1 _BIN

+5V_SW

Y2 _ IN

PR2 _IN

PB2_IN

SC1_AU_LOUT

SC1 _AU_ROUT AOUT0R

AOUT0L

SOY1_IN

Y1 _ IN

PB1_IN

PR1 _IN

AU_ AIN2R

CVBS0_IN

AU_ AIN1R

AU_AIN1L

AU_ AIN2R

AU_AIN2L

SC1 _ RIN

SC1_FS

SC1_FBSC1 _ RIN

SW_ HD

AU_AIN2L

SCART_ISP

SCART_ISP_TRAP

SCART_ISP

AU_AIN1L

AU_ AIN1R

DTV_Pr_IN1

DT V_Y_IN1

AV_VIN

SC2 _ AU_LIN

SC2 _ AU_RIN

DTV_Pr_IN1

DT V_Y_IN1

DTV_Pb_IN1

DTV_Pb_IN1

SC1 _ AU_LIN

SC1 _ AU_RIN

SC2 _ AU_RIN

SC2 _ AU_LIN

av_1_out

SC1_AU_LOUT

SC1 _AU_ROUT

SC1 _ AU_RIN

SC1 _ AU_LIN

av_1_in

TU_SCART

SC1 _BIN

SC1 _AU_ROUTSC1_AU_LOUT

SC1 _GIN

SC1 _GIN

AV_VIN

+5V_SW1,4,12,13,15

G ND1 ,2 ,4,5,6,7,8,9,10,11,12,13,14,15

GNDVGNDVGNDV

GNDV

GNDV

+5V_SW

GNDV

GNDV

GND_ ADC

GNDV

GNDV

GNDVGNDV

GND_ ADC

GND_ ADC

GND_ ADC

GND_ ADC

+3V3

G ND

GNDV

GNDV GNDV

GNDV GNDV

GNDV GNDV

GND_ ADC

GND_ ADCGND_ ADCGND_ ADC

GNDV

GNDV

+5V_SW_4052

GNDV

+5V_DC

GNDTA GNDTAGNDTA

SOG_IN 7

CVBS2_IN 7

AOUT0L7AOUT0R7

SOY2_IN 7

CVBS0_IN 7

Y2_IN 7

PB2_IN 7

PR2_IN 7

AU_ AIN1L 4

AU_ AIN1R 4

AU_AIN2L 4

AU_ AIN2R 4

Y1_IN 7

SOY1_IN 7

PR1_IN 7

SW_ HD 7

SCART_ISP_TRAP 13

PB1_IN 7

DVD_ Y_IN13DVD_ PB_IN13DVD_ PR_IN13

av_1_out 3av_1_out 3TU_SCART

Title



Input-2 VideoC


SUNPLUS

SCART1 AV+RGB

FS -> S O Y2 / SARIN10-2v: TV Mode -> 0-0.4v5-8v: 16:9 AV -> 1.0-1.6v9.5-12v: 4:3 AV -> 1.9-2.4v

Y Pr Pr CVBS

11/30 Modify

ISP FROM SCART

11/28 Modify

11/28 Modify

11/28 Modify

11/28 Modify

L171.8uH

R561 NC

D18

9.2V

12

R257100R

R2162.4K

R43212K

R30375R

C235220pF

Q582N3904

1

2

3

C1311000pF

R307

6.8K

D25

5.6V

12

DM23N C

C23810uF

R312 10K

C207220pF

C155

NC/10pF

L29120ohm/100MHz

R43068R

DM13NC

C325

2.2uFC-0603

R563 NC

R24475R

R243100R

C232220pF

C2231uF

D19

9.2V

12

R3146.8K

DM24N C

R330 22K

DM14NC

Pb

Pr

Y

Y

Pb

Pr

C N9

AV1-3X2

1

3

5

2

4

6

77

88

99

1010

1111

1212

1313

1414

1515

1616 R32922K

R433220R

CON10N C

2

1

4

3

6

5

R23047K

L141.8uH

C1580.01uF

L211.8uH

R41210R

C1790.01uF

R564 NC

GNDB

GNDVI

AILBIN

VOUT

FunSel

VIN

GNDG

SHILED

N.C.GIN

N.C.GNDR

RIN

AORAIR

RGBSW

AOL

GNDSW

GNDA

GNDVO

CN7

SCART Connector

123456789101112131415161718192021

C236220pF

Q212N3904

1

2

3

DM11NC

L31120ohm/100MHz

C151.5nF

C199220pF

C326

2.2uFC-0603

DM25NC

R24275R

C34510uF

R1866.8K

DM26NC

R431220R

D20

5.6V

12

C233220pF

R128 10K

L231.8uH

L30120ohm/100MHz

R562 NC

C185220pF

C324

2.2uFC-0603

R2130R

DM12NC

R3056.8K

R104100R

C161.5nF

R129100K

DM28NC

C327 1uF

R429470R

R25975R

C237220pF

R246100R

R24575R

R306 10K

R560 NC

R25875R

DM31NC

C234220pF

D24

5.6V

12

R42827K

DM27NC

R308 10K

C328 1uF

R27475R

R29247K

U18

PI5V330

1A2

1B51C11

1D14

2A3

2B6

2C10

2D13

A 4

B 7C 9

D 12

EN 15

S 1

VC

C16

VS

S8

R434220R

R559 NC

R28910K

R190 10K

R30475R

C215220pF

L221.8uH

C1650.01uF

Q572N3906

3

2

1

R27075R


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

A U_AIN1R

AIN2L

A IN2R

AU_AIN2L

A U_AIN2R

A U_SW0A U_SW1

A IN0R

AIN0L

AIN3L

A IN3R

A IN2RAIN2L

A IN3RAIN3L

A U_AIN2R

AU_AIN1LA U_AIN1R

AU_AIN2L

A U_SW1A U_SW0

+3V3

+5V_SWAIN0L

A IN0R

AU_AIN1L

AIN1L

A IN1R

A IN1RAIN1L

+5V_SW1,3,12,13,15

+3V31,2,3,7,8,9,10,13,14,15

GND1,2,3,5,6,7,8,9,10,11,12,13,14,15

GN DV

+5V_SW

+3V3

+5V_SW_4052

+5V_SW_4052

+5V_SW_4052

+5V_SW_4052

+5V_SW_4052

GNDTA

GNDTA GNDTA

GNDTA

GNDTA

DVB_AL_OUT13

DVB_AR_OUT13

AIN2L 7AIN2R 7

AIN3L 7AIN3R 7

AU_AIN1R 3AU_AIN1L 3

AU_SW0 7

AU_AIN2R 3AU_AIN2L 3

AU_SW1 7

AIN1L 5AIN1R 5

Title

Size Docum ent Number R e v

Date: Sheet o fSPTV05-13-V1 1 .0

Input-3 Audio and DTVA3


SUNPLUS

(to SPV7100 & SCART-2)

PC Audio Input

L-OutR-Pho L-Pho

12

R-Out

4

Stereo Audio ConnectorTop Diagram

35

4052 ch0:SCART4052 ch1:YPrPr,CVBS4052 ch2:PC output 4052 ch3:TV MONO

4052-->SPV7100 :CH2

PC-->SPV7100 :NCDVD-->SPV7100 :CH1

DVB-->SPV7100 :CH3

R33147K

C334 1uF

C332 1uF

R19147K

C2390.1uF

R20047K

R33247K

DM16NC

R18747K

R18847K

R2756.8K

R33347K

CN6

PHONEStereo Audio In

54321

R33447K

U16

74HC4052

1Y012

1Y114

1Y215

1Y311

2Y01

2Y15

2Y22

2Y34

1Z 13

2Z 3

VCC 16

VEE 7

GND 8IE6S19S010

R19647K

R276 10K

C330 1uF

R18047K

C335 1uF

R18147K

C329 1uF

C333 1uF

R17347K

R278 10K

DM15NC

R17747K

C331 1uF

R2776.8K

R19247K

C336 1uF

R19847K

R27347K


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

A IN1RA IN 1L

+5V _SW

CV B S 1_IN

C2_IN

DV D_ EN

A IN1RA IN 1L

C2_IN

CV B S 1_IN

D AT

STB

IR_DV D

+5V_SW1,3,4,12,13,15

G N D1,2,3,4,6,7,8,9,10,11,12,13,14,15

+5V _SW

G NDV

GNDV

GNDV

GNDV

GNDV

GNDV G NDV

G NDVGNDV GNDV

G NDV

GNDVGNDV G NDV

G NDV

GNDV GNDV

GNDV GNDV

GNDV GNDV

GND_A DC

GNDV

A IN1L 4A IN1R 4

CV B S1_IN 7

C2_IN 7

DV D_EN 7

D V D_Y _IN 1 3

DV D_P B_IN 1 3

DV D_P R_IN 1 3

IR_DV D 9

S TB_GPIO 4

DA T_GPIO 4

Title


Date: S heet o fSPTV05-13-V1 1.0

Input-2 VideoA


SUNPLUS

s-cs-y

YGNDPB

PRGND

GNDLEFTRIGHTGNDENIR

D 63

5.6V

12

R 234 10K

C339220pF

D 56

5.6V

12

L411.8uH R367

75R

R2336.8K

L391.8uH

C344220pF

R2956.8K

C340220pF

R4277 5R

R 294 10K

C315220pF

R4267 5R

C N32

NC/CON5/2.0mm

12345

C341220pF

L381.8uH

C313NC/220pF

C ON7

CON11/2.0mm

123456789

1011

DM29NC

D 55

5.6V

12

L401.8uH

L373.3uH

R36675R

F B 1120R/100M

C342220pF

DM30NC

241

3

C N 8

S _VIDEO

3124

567

C316220pF

C314330pF

R36575R

C343220pF


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MD 10

MD 11MD 12

MD 13MD 14

MD 15

DQS 0H

DQM 0HW E NCA S NRA S N

B A0B A1M A10MA0MA1MA2MA3 MA4

MA5MA6MA7MA8MA9M A11

M CLKPMCL KNDQ M0L

DQS 0L

MD7

MD6MD5

MD4MD3

MD2MD1

MD0

CK E R

MD8

MD9

CK ES DC LKP

DQ M0L

S DCL KN

DQS 0HDQS 0L

DQM 0H

MA [0..11]

MD[0 ..15]

B A0B A1

W E NCA S NRA S N

MCL KN

M CLKP

CK E RCK E

S DC LKP

S DCL KN

C S N

GNDM

+2V5

GNDM

GNDM GNDM

GNDM

+2V5

+2V5

+2V5

+2V5

+2V5

+2V5

+2V5

+2V5

+2V5

GNDM

GNDM

+2V5

+1.25V

+1.25V

+1.25V

S DCLKN7

DQM0H7DQM0L7

DQS 0L7DQS 0H7

MA [0..11]7

MD[0..15]7

BA07BA17

CA S N7RA S N7

W E N7

S DCLKP7CK E7

Title


Date: S heet o fSPTV05-13-V1 1.0

DDR PARTA


SUNPLUS

*Short these ground planes on PCB

*add

The

se c

ompo

nent

s clo

se to

DD

R

HY5DU281622ETP(128Mb/2Mx16x4B)All traces must have the same length

SDRAM Data Bus

CLOSE TO DDR

CLOSE TO 7100

R 93 1 0R

C 200.1uF

R 87

120

R 86 1 0R

C 211000pFC 36

10uF/10V

C 35

0.1uF

R103 22K

R 99 4 7R

R 70

120

R 95 4 7R

C 180.1uF

R 94 1 0R

U5

8Mx16 DDR-SDRAM-TSOP

VDD1DQ02

DQ14DQ25

DQ37DQ48

DQ510DQ611

DQ713 DQ8 54

DQ9 56DQ10 57

DQ11 59DQ12 60

DQ13 62DQ14 63

DQ15 65

VDD18

VDDQ3

VSSQ6

VDDQ9

VSSQ12

VDDQ15NC14

NC17LDQS16

NC19LDM20WE21CAS22RAS23CS24NC25BA026BA127AP/A1028A029A130A231A332 A4 35

A5 36A6 37A7 38A8 39A9 40

A11 41

VDD33 VSS 34

NC/A12 42NC 43

CKE 44CK 45CK 46

UDM 47VSS 48

VREF 49NC 50

UDQS 51VSSQ 52

NC 53

VDDQ 55

VDDQ 61

VSSQ 58

VSSQ 64

VSS 66

R335NC/75R1%


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HPD_PCHS_VGAVS_VGAMIDSCV

BA1

G_IN

TX1M2

TX1M0

TX1M3

TXCLK1M

TX1M1

TX1P2

TX1P0

TXCLK1P

TX1P1

TX1P3

TX0P1

TX0P0TX0M0

TX0P2

TX0M3

TX0M1

TXCLK0P

TX0M2

TX0P3

TXCLK0M

SIFAIN0

Y2 _ INSOY2_INPB2_INPR2 _IN

POWER_ON

RXCP

SOG_IN

RESETN

SCL_M

AOUT0R

SDCLKN

HPD_ HDMI

AIN

2RA

IN2L

AIN

3RA

IN3L

BL_ADJ

RXM0

R_ IN

SDA_M

AOUT1L

HPD_PC

CL KIN

BL_ON

AOUT1R

FILT

AU_SW0AU_SW1

C2 _ IN

HOL D_FLASH

MA[0..11]

CLKOUT

MUTE_AMP

SD1 _FLASHSD0 _FLASH

SCK_FLASH

RESETN

BL_ADJ

CEN_ FLASH

CLKOUT

RXP0

/WP

CKE

DVD_EN

Y1 _ IN

CV

BS

0_IN

RXDTXD

CVBS0_IN

CV

BS

1_IN

C2_

INC

VB

S2_

INC

VB

S3_

IN

VCM_AUI

MD[0..15]

W ENCASNRASN

MIDSCV

VCM

PANEL_ON

IR_DAT

RXM1RXP1

SOY1_IN

STB_AC_ON

SDA_VGASCL_VGASDA_HDMI

DQ

M0H

HS_VGA

SD1 _FLASHSD0 _FLASH

AIN2LAIN2R

CVBS1_IN

DQ

S0H

CCIR6 5 6 -D[0..7]

CCIR6 56-CLK

PB1_IN

/WP

SCL _HDMI

IR_DAT

CKE

CEN_ FLASHSCK_FLASH

PR1 _IN

DQS0HDQM0H

DQS0LDQM0L

CVBS2_IN

RXM2RXP2

RXCM

BA0

AIN3LAIN3R

CL KIN

B_IN

SARIN0

SDA_VGASCL_VGASDA_HDMISCL _HDMI

CVBS3_IN

AOUT0L

BL_ON

SDCLKP

SIF

AIN

0

HPD_PC

HOL D_FLASH

LED_C

RXDTXD

STB_AC_ON

HPD_ HDMI

DVD_EN

PANEL_ONLED_C

I2 C_SW

SW_ HD

SW_ HD

AOUT1L

AOUT1RAUO_1R

AUO_1L

AOUT0L

AOUT0RAUO_0R

AUO_0L

MUTE_AMP

MUTE_AMPPOWER_ON

POWER_ON

SD

CLK

N

RA

SN

CCIR6 56-D4

TX0M

0

MD

12

MD

10

MD

3

TX1P

3

TX

CLK

1PT

XC

LK1M

TX0M

3

MA7

MA4

VR

P_S

IF

VCM

AIN

2R_I

N

PB

1_IN

MA1

CCIR6 56-D2

WE

N

TX1M

1

SDA_M

TX1M

0

CA

SN

AU

O_1

R

TX0P

1

PR

2_IN

I 2 C_SW

MD

9

MD

2

AIN

3L_I

N

MA0

CCIR6 56-D1

MA6

MA3

MD

8

TX

CLK

0PT

XC

LK0M

TX1P

2

MD

15

MD

6

SO

Y2_

IN

G_I

N

VCM_AUO

BA0

MD

7

DQ

M0L

AIN

3R_I

N

R_I

N

VS_VGA

I2 C_SW

MD

1

SD

CLK

P

TX0M

1

PB

2_IN

MA11

SCL_M

MA2

CCIR6 56-CLK

MA10

MD

14

MD

11

MA9

CCIR6 56-D5

SA

RIN

0

Y1

_IN

B_I

N

DQ

S0L

MD

5

TX1M

2

TX1P

0

TX0P

2

CCIR6 56-D3

Y2

_IN

CCIR6 56-D6

MD

0

CK

E

VR

N_S

IF

TX1M

3

TX0P

3

SO

G_I

N

AU

_SW

1

AU

O_1

L

VC

M_A

UO

MD

13

AU

_SW

0

AU

O_0

R

TX0P

0

MA5

BA1

MA8

MD

4

VC

M_A

UI

TX1P

1

PR

1_IN

SO

Y1_

IN

CCIR6 56-D0

AU

O_0

L

VC

M_S

IF

AIN

2L_I

N

TX0M

2

SW_ HD2

SW_ HD

SW_ HD2

SW_ HD2

AIN3 R_INAIN3L_INAIN2 R_INAIN2L_IN

BL_ON

CCIR6 56-D7

RXCMRXCP

RXM0RXP0

RXM1RXP1

RXM2RXP2

DVD_ IR_SW

+3V3

GND_ ADC

GND_ ADC

GNDM

GND_ AUO

GND_TMDS

+3V3_MPLL

+3V3_IN

+1V8_ADCA

+3V3_AUO+3V3_IN+3V3_ADCB

GND_ ADC

+SVDD

+1 V8_DLLVDD

+3V3_IN

GND_ AUOGND_TMDSGND_ ADC GNDMGNDP

+3V3_LVDS

GNDP

+3V3_LVDS

+DVDD

+3V3_XTAL

+1V8_AUD+3V3_TMDS

+CVDD+3V3_ADCP

GNDM

+3V3

+MVDD

+CVDD

+CVDD

+CVDD

+CVDD

+CVDD+DVDD

GND_ AUO

+1V25

GNDM

+1V25 +MVDD

+5 V_DDC

+CVDD

+3V3 +3V3

+3V3

+3V3

+3V3_AUO

+5V_SW

+5V_SW

CVBS1_IN5CVBS0_IN3

CVBS2_IN3CVBS3_IN12

MD[0..15] 6

W EN 6CASN 6RASN 6

SDCLKP 6CKE 6

MA[0..11] 6

BA1 6BA0 6

SARIN09

AIN2L4AIN2R4

AIN3L4AIN3R4

SIFAIN012

RESETN9,13

RXD2,9TXD2,9

IR_DAT9

SD0 _FLASH9SD1 _FLASH9

CEN_ FLASH 9SCK_ FLASH 9

SDCL KN 6

SDA_VGA2SCL_VGA2SDA_HDMI2SCL _HDMI2

TX0M0 10TX0P0 10TX0M1 10TX0P1 10TX0M2 10TX0P2 10TXCLK0M 10TXCLK0P 10TX0M3 10TX0P3 10

TX1M0 10TX1P0 10TX1M1 10TX1P1 10TX1M2 10TX1P2 10TXCLK1M 10TXCLK1P 10TX1M3 10TX1P3 10

AU_SW1 4AU_SW0 4

HPD_PC 2

/WP 2

AOUT0R 3AOUT0L 3

HPD_ HDMI 2

BL_ON 10BL_ADJ 10POWER_ON 1PANEL_ON 10

MUTE_AMP 11

SDA_M 9,12,13SCL_M 9,12,13

AOUT1R 11AOUT1L 11

DVD_ EN 5

RXCM2RXCP2RXM02RXP02

STB_AC_ON 1

CCIR6 5 6 -D[0..7] 13

CCIR6 56-CLK 13

RXP12RXM12

RXM22RXP22

DQM0H 6DQS0H 6DQM0L 6DQS0L 6

HS_VGA2

B_IN2G_IN2

R_ IN2SOG_IN3

C2 _ IN5

Y1_IN3SOY1_IN3PB1_IN3PR1_IN3

SOY2_IN3Y2_IN3

PB2_IN3PR2_IN3

HOL D_FLASH 2

LED_C9

I2 C_SW 12

SW_ HD 3

VS_VGA2

MCU_IO

PDP_ CONTROL17

SA

RIN

1

9

CV

BS

O9

DVD_ POWER_SW7

DVD_ IR_SWSTB_GPIO 4DAT_GPIO 4

Title



SPV7100 Part-1C


SUNPLUS


LVDS Output

Mem

ory

I/O

MPU

& S

PI

Video Input Audio Input

Default Pull Setting

HD

MI

Inpu

t

(Pin-164)

* change C200-203 nets

Crystal Circuit

VGA/YUV Input

These components close to SPV7100

Memory I/O

IO Trap

DDR VREF


CAFE

Audio Output

10/24 Add

10/25 Add

Close to 7100

11/27 ADD

Close t o 7100

11/30 Note

R18

31K

R476 100R

C157

1uF

C-0603

R2298.2K

C99

33pF

R36910K

C389

5pF

C124

1uF

R36 47R

R85 4.7K

R149 4.7K

R531 10R

R98

0R

C140

0.1uF

C-0603

C3090.047uF

R1705.6K+-1%

R218 180R

R360

200K

C19

02.

2uF

R362

200K

R33

61K

R235 180R

C47

56pFC-0603

C16

02.

2uF

R17910K

C17

00.

1uF

R475 100R

R413 2K

C3100.047uF

R532 10R

R107 33R

R359

200K

R31710K

R33

71K

C91

33pF

R527 10R

C117 390pF+-5%

C18

02.

2uF

X1

27MHz 30ppm 20PX'TAL

C16

82.

2uF

FB10

120/100M

R33

81K

R10

NC

R14210K

R164 2.2K

R219 8.2K

C18

12.

2uF

R106 33R

R533 10R

R299 10K

R33

91K

R41410K

C46

56pFC-0603

C49

22pFC-0603

R162 100R

R528 10R

C242

10uFC-0805

R141

4.7K

R415 2K

C16

72.

2uF

C118

5pF

C16

62.

2uF

R126

4.7K1%

R368 100R

R572 47R

C1640.047uF

C15

92.

2uF

R236 8.2K

R526 10R

SPV7100A-LQFP256

U9A

RXCM232RXCP233

RXM[0]236RXP[0]237

RXM[1]240

RXP[1]241

RXM[2]244

RXP[2]245

HSYNC0254

VSYNC0255

BIN

2

GIN

3S

OG

4

RIN

5

Y1

8

SO

Y1

9

PB

110

PR

111

Y2

15

SO

Y2

16

PB

217

PR

218

CV

BS

023

CV

BS

125

CV

BS

227

CV

BS

328

C1

24

C2

26

TX0M

[0]

189

TX0P

[0]

188

TX0M

[1]

187

TX0P

[1]

186

TX0M

[2]

185

TX0P

[2]

184

TXC

LK0M

183

TXC

LK0P

182

TX0M

[3]

181

TX0P

[3]

180

TX1M

[0]

177

TX1P

[0]

176

TX1M

[1]

175

TX1P

[1]

174

TX1M

[2]

173

TX1P

[2]

172

TXC

LK1M

171

TXC

LK1P

170

TX1M

[3]

169

TX1P

[3]

168

CV

BS

OU

T30

FILT250

MIDSCV256

VC

M13

SA

RIN

033

SA

RIN

134

AIN

0L37

AIN

0R38

AIN

1L39

AIN

1R40

AIN

2L41

AIN

2R42

AIN

3L43

AIN

3R44

VC

M_A

UI

45

VR

P_S

IF50

VC

M_S

IF51

VR

N_S

IF52

SIF

AIN

053

SIF

AIN

154

UA

RT_

RX

192

UART_TX193

RESETN194

IR_DAT197

TESTMODE203

HPD_HDMI214

SDA_VGA215

SCL_VGA216SDA_HDMI217

SCL_HDMI218

AO

UT0

L55

AO

UT0

R56

AO

UT1

L61

AO

UT1

R62

VC

M_A

UO

58

PWM0220PWM1//EXINT2219

SDA_M 66SCL_M 67

XTALI225

XTALO226

I2SWSA/JRSTN212I2SCLKA/JTDI211I2SDA0/JTDO209I2SDA1/JTMS208I2SMCLKA/JCLK207I2SDA2/SPDIFI206I2SDA3/SPDIFO205

HOLD_FLASH202SCK_FLASH201CEN_FLASH200SD0_FLASH199SD1_FLASH198PWM2/WP_FLASH196PWM3/EXINT1195

MA[0] 123

MA[1] 122MA[2] 121

MA[3] 120

MA[4] 119MA[5] 118

MA[6] 117

MA[7] 114

MA[8] 113

MA[9] 112

MA[10] 124

MA[11] 111

BA0 128

BA1 127

RA

SN

133

CA

SN

134

WE

N13

5

CLK

N16

2C

LKP

163

CK

E16

4

VD[0] 76

VD[1] 75VD[2] 74

VD[3] 73

VD[4] 72VD[5] 71

VD[6] 70

VD[7] 69VCLK 68

VR

EF_

012

9V

SS

R_0

130

VREF_1 105VSSR_1 106

MD

[0]

157

MD

[1]

156

MD

[2]

155

MD

[3]

154

MD

[4]

153

MD

[5]

152

MD

[6]

151

MD

[7]

150

MD

[8]

147

MD

[9]

146

MD

[10]

145

MD

[11]

144

MD

[12]

143

MD

[13]

142

MD

[14]

141

MD

[15]

140

DQ

M0L

161

DQ

S0L

160

DQ

M0H

136

DQ

S0H

137

I2SWSB/MD[16] 102I2SCKB/MD[17] 101

I2SDB0/MD[18] 100

I2SDB1/MD[19] 99

I2SMCLKB/MD[20] 96

I2SDB2/MD[21] 95I2SDB3/MD[22] 94

PWM2/MD[23] 93

VDO[0]/MD[24] 91

VDO[1]/MD[25] 90

VDO[2]/MD[26] 89VDO[3]/MD[27] 88

VDO[4]/MD[28] 85VDO[5]/MD[29] 84

VDO[6]/MD[30] 83

VDO[7]/MD[31] 82

GPIO/DQM1L 104

GPIO/DQS1L 103

GPIO/DQM1H 80VCLKO/DQS1H 81

AV

DD

18_A

DC

1

AV

DD

18_A

DC

7

AV

DD

18_A

DC

14

AV

DD

18_A

DC

22

AV

SS

18_A

DC

6

AV

SS

18_A

DC

12

AV

SS

18_A

DC

19

AV

SS

18_A

DC

29

BV

DD

33_A

DC

21B

VS

S33

_AD

C20

AV

DD

33_S

AR

35

AV

SS

33_S

AR

36

AV

DD

33_A

UI

46

AV

SS

33_A

UI

47

AV

DD

33_S

IF49

AV

SS

33_S

IF48

AV

DD

33_A

UO

57

AV

SS

33_A

UO

59

AV

SS

33_A

UO

60

PVDD33_TMDS230PVSS33_TMDS229

AVDD33_TMDS231

AVDD33_TMDS235

AVDD33_TMDS239

AVDD33_TMDS243

AVSS33_TMDS234

AVSS33_TMDS238

AVSS33_TMDS242

AVSS33_TMDS246

DVDD18_TMDS248DVSS18_TMDS247

PVDD33_ADC249

PVSS33_ADC251

AVDD33_REG223

AVDD33_XTL224

PVDD18_AUD228PVSS18_AUD227

DPLLVDD33222DPLLVSS33221

MPLLVDD33 108

MPLLVSS33 107

AV

DD

33_L

VD

S19

0

AV

DD

33_L

VD

S17

8

AV

SS

33_L

VD

S19

1

AV

SS

33_L

VD

S17

9

PV

DD

33_L

VD

S16

6P

VS

S33

_LV

DS

167

SVDD 87

SVDD 98

SVSS 86

SVSS 97

DLLVDD18 109DLLVSS18 110

DVDD33 77

DVDD33210

DVSS 78

DVSS33204

DV

DD

1832

DVDD18 65

DVDD18 79

DVDD18 92

DV

DD

1813

2

DV

DD

1816

5

DVDD18213

DV

SS

1831

CLK

24P

63C

LK24

N/E

XIN

T064

DV

SS

1813

1

SV

DD

2515

9

SV

DD

2514

9

SV

DD

2513

9

SVDD25 126

SVDD25 116

SV

SS

2515

8

SV

SS

2514

8

SV

SS

2513

8

SVSS25 125

SVSS25 115

HSYNC1252VSYNC1253

C63

56pF

C16

90.

1uF

C18

92.

2uF

R534 10R

C1720.047uF

C14

256

pF

C1238200pF+-5%

R132

4.7K1%

R37010K

R529 10R

R90

0R

C113

5pF

R2038.2K

R15310K

R15410K

C13

80.

1uF

C76

56pF

R15NC

R150 22R

R35 47R

C61

56pF

R121 33R

C243

10uFC-0805

R152 100R

C137

0.1uF

C-0603

R361

200K

C64

0.1uF


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+3V3

+1V8

+3V31,2,3,7,9,10,13,14,15

G ND,3,4,5,6,7,9,10,11,12,13,14,15

+1V81

GND_AUO

GND_ ADC

GND_ ADCGND_TMDS

GNDM

GNDP

+3V3_MPLL

+3V3_XTAL

+1 V8_DLLVDD

+3V3_TMDS

+3V3_ADCP

+3V3_ADCB

+3V3_AUO

+3V3_LVDS

+3V3

+1V8

+3V3_SW7100

+3V3

+3V3

+3V3_SW7100

+3V3_SW7100

+1V8 +CVDD

+2V5 +MVDD

+3V3+DVDD

+3V3

+1V8

GND_AUO GND_TMDSGNDPGNDMGND_ ADC

GND_ ADC

+1V8_AUD+1V8

+3V3 +SVDD

+1V8_ADCA

+3V3

GND_ AUO

+3V3_IN+3V3_SW7100

Title



SPV7100 Part-2Cu stom


SUNPLUS

PLL POWER/GND (3.3V/1.8V)

ADC POWER/GND (1.8V/3.3V)

SARADC/SIF/AUDIO POWER/GND (3.3V)

TMDS POWER/GND (1.8V/3.3V)

SOURCE POWER/GND (1.8V/2.5V/3.3V)

XTAL POWER/GND (3.3V)

LVDS POWER/GND (3.3V)

Pin235 Pin239 Pin243

SPV7100 E-Pad

Pin231

Pin7 Pin14 Pin22Pin1

Pin65 Pin79 Pin92Pin32

Pin126 Pin139 Pin149Pin116 Pin159

Pin165 Pin213Pin132

Pin77


Power Plane : +5V, +5VSB, +3V3, +3V3_SPV ,+3V3_MC, +2V5,+1V8, +VCC_PNL,+AVDD_ADC

Ground Plane: GND, GND_ADC, GND_TMDS, GNDV, GNDM, GNDP, ND_LVDS, GND_AUO, GND_AMP

Power Line : +12V, +3V3_ADCP , +3V3_ADCB, +3V3_MPLL , +3V3_DPLL , +1V8_DLLVDD, +1V8_TMDSP, +1V8_TMDS, +1V8_AUD

Fe rri te Be e d S pec:FB : Rdc=0.2 , Z=300/100MHz , Idc=500mA ~ MCB2012S301HFB_L : Rdc=0.015 , Z=120/100MHz , Idc=6000mA ~ MHC3216S121WFB_S : Rdc=0.35 , Z=75/100MHz , Idc=300mA ~ MCB1608U750F

TMDS AUD PLL POWER/GND (1.8V)

*add

10/25 ADD

10/25 ADD

11/30 Modify

11/30 Modify

Pin21

Pin249

Close t o 7100

11/30 ModifyEC84470uF/16V

EC85470uF/16V

C250

10uF

C307

10uF

FB22

120/100M

C50

0.1uFC381

0.1uF

C246

10uF/10V

C251

10uF

C66

0.1uF

C54

0.1uF

FB24

120/100M

FB13

120/100M

C101

0.1uF

FB8

120/100MC62

0.1uF

FB3

120/100M

E-Pad

U9B

SPV7100A-LQFP256

EPad257

EPad258EPad259

EPad260

EPad261

EPad262EPad263

EPad264

EPad265EPad266

EPad267

EPad268EPad269

EPad270

EPad271

EPad272EPad273

EPad274

EPad275EPad276

EPad277

EPad278EPad279

EPad280

Epad281

EPad282EPad283

EPad284

EPad285EPad286

EPad287

EPad288EPad289

EPad290

EPad291

EPad292EPad293

EPad294

EPad295EPad296

EPad297

EPad 298

EPad 299EPad 300

EPad 301

EPad 302

EPad 303EPad 304

EPad 305

EPad 306EPad 307

EPad 308

EPad 309EPad 310

EPad 311

EPad 312

EPad 313EPad 314

EPad 315

EPad 316EPad 317

EPad 318

EPad 319EPad 320

EPad 321

EPad 322

EPad 323EPad 324

EPad 325

EPad 326EPad 327

EPad 328

EPad 329EPad 330

EPad 331

EPad 332

EPad 333EPad 334

EPad 335

EPad 336EPad 337

C121

0.1uF

C244

10uF

C67

0.1uF

FB5

120/100M

C378

10uF

C40

0.1uF

C111

0.1uF

FB15

120/100M

C247

10uF

FB12

0R

C39

0.1uF

FB332.2R

FB17

0R

C135

0.1uF

C95

0.1uF

C80

0.1uF

C133

0.1uF

C68

0.1uF

FB26

120/100M C379

0.1uF

C254

10uF

FB21

120/100M

C248

10uF

C130

0.1uF

C308

10uF/10V

C93

0.1uF

C134

0.1uF

C53

0.1uF

C109

0.1uF

C120

0.1uF

C26

10uF/10V

+ EC54

100uF/16V

CAP100 C139

0.1uF

FB25

120/100M

C253

10uF

C41

0.1uF

C122

0.1uF

C34

0.1uF

C58

0.1uF

C252

10uF

C380

0.1uF

C79

1uF

C52

0.1uF


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H O L D #S C K _ F L A S H

S C L _ MC E N _ F L A S H

R E S E T N

H O L D #

S D 1 _ F L A S H

C E N _ F L A S H

W P #

W P #S D 0 _ F L A S H

S C K _ F L A S HS D 1 _ F L A S H

S D 0 _ F L A S H

I R _ D A T

K P D 4

K P D 1

K P D 2

K P D 3

K P D 6

K P D 5

S A R I N 0R E S E T N

+ 5 V S B

S D A _ MS C L _ M

S C K _ F L A S HC E N _ F L A S H

S D 0 _ F L A S HS D 1 _ F L A S H

I R _ D A T

R X DT X D

K P D 0S A R I N 0

I R

S D A _ M

I R

K P D 0

K P D 3K P D 2

K P D 4

K P D 6K P D 5

K P D 1

I R

L E D _ G _ O NL E D _ R _ O N

L E D _ G _ O N

L E D _ R _ O N

K P D _ P O W E R

+ 5 V S B1 , 5 , 1 0 , 1 3

G N D1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 1 0 , 1 1 , 1 2 , 1 3 , 1 4 ,1 5

+ 3 V 3

+ 3 V 3 _ F L A S H

+ 3 V 3

+ 3 V 3 _ F L A S H+ 3 V 3

+ 3 V 3

+ 3 V 3

+ 5 V S B

+ 5 V _ D C

+ 5 V S B

+ 3 V 3

+ 5 V S B

+ 5 V S B 1

+ 5 V S B 1

+ 5 V S B 1

W P #2

S A R I N 0 7R E S E T N 7 , 1 3

C E N _ F L A S H7S C K _ F L A S H7

S D A _ M7 , 1 2 , 1 3S C L _ M7 , 1 2 , 1 3

S D 1 _ F L A S H7S D 0 _ F L A S H7

I R _ D A T7

R X D 2 , 7T X D 2 ,7

L E D _ C7

I R _ D V D 5

S T B _ C O N7

S A R I N 1 9K P D _ P O W E R

D V D _ I R _ S W I R _ D V D 5

K P D _ P O W E R

IR 7

K P D _ P O W E R

T i t le

S i z e D o c u m e n t N u m b e r R e v

D a t e : S h e e t o fSPTV0 5 -1 3 -V1 1.0

M C U Inte rfaceD

9 15F r i day, April 03, 2009

SUNPLUS

Flash Interface

EEPROM

Hardware Reset

RS-232 Interface

1 1 / 0 5 Add

Flash Interface

5 VR E M OTEG NDP O W ERR EDG R E ENG NDM U TEV -V +M E NUS ELC H -C H +

J6

G P R O B EC O N 4 / 2 . 0 m m

R 81 0 K

D 6 9

n c

C 2 5

0 . 1 u F

C 9 4

0 . 1 u F

R 4 6 81 0 K

C 3 8 8

3 9 0 p F

C 2 5 5

1 0 u F

U 1 5

2 4 L C 3 2S O P 8

R 4 2 34 7 K

R 1 61 . 2 K

D 7 0

1 N 4 1 4 8

D M 1 9

E S D - 0 6 0 3

Q 5 22 N 3 9 0 4

R 5 4 9NC

R 1 72 K

R 6 91 0 K

R 6 71 K

R 4 1 62 2 0 R

+ E C 7 4

4 7 u F / 1 6 VR 1 82 . 4 K

J P 2

J P 2 / 2 . 5 4

12

R 4 2 0 N C / 1 K

R 4 2 44 . 7 K

R 1 2 01 0 K

D 95 . 6 V

12

R 5 4 84 7 K

R 2 06 . 2 K

1 0 KR 7 7

R - 0 6 0 3

12

D 4

1 N 4 1 4 8

D - 1 2 0 6

12

R 1 7 12 K 2

U 7

E N 2 5 T 8 0 / D I PD I P 8

< A s s e m b l y >

Q 1 8N C / A P 1 7 0 1 F

13

R 2 11 1 K

F B 4

L - 0 8 0 51 2 0 / 1 0 0 M

Q 5 62 N 3 9 0 6

31

R 1 7 22 K2

N C / 1 K

R 8 2

R - 0 6 0 3

D 8

N C / 3 . 9 V

C 3 8 7

3 9 0 p F

R 5 5 0 4 . 7 K

D7B A V 9 9

1 23

R 2 2NC

C O N 8

C O N 1 1

R 6 81 0 K

R 4 2 22 2 0 R

R 1 93 . 6 K

D 7 1

1 N 4 1 4 8

D 7 3

1 N 4 1 4 8

R 5 4 74 7 K

R 1 1 91 0 K

C80 . 1 u F

R 5 7 1N C / 0 R


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TX1M0 TX1P0

TX0P1TX0M1TX0M0 TX0P0

TX0P2TX0M2

TX0M3 TX0P3

TX1P2

TX1P3

TX1P1TX1M1

TX1M3

TX1M2

+5V_SW

+12V_IN

BL_ADJ

BL_ADJBL_ON

BL_ON

+12V_IN1,5,11

+5V_SW1,3,4,12,13,15

GND1,2,3,4,5,6,7,8,9,11,12,13,14,15

+5V_DC

+12V_IN

+VCC_PNL

+VCC_PNL

GNDP

GNDP

GNDP

GNDP

GNDP

GNDP

GNDP

+3V3

+3V3

GND_TMDSGND_PWR

+12V_IN

+5V_SW

GNDP

+5VSB

+5VSB

+12V_power

PANEL_ON7

TX0M07 TX0P0 7TX0M17 TX0P1 7

TX0M27 TX0P2 7

TXCLK0M7 TXCLK0P 7TX0M37 TX0P3 7TX1M07 TX1P0 7TX1M17 TX1P1 7TX1M27 TX1P2 7

TXCLK1M7 TXCLK1P 7TX1M37 TX1P3 7

BL_ADJ7BL_ON7

PDP_CONTROL17

Title

Size Document Number Rev

Date: Sheet o fSPTV05-13-V1 1.0Panel Output

Custom


SUNPLUS

EVEN

ODD

(2nd pixel)

(1st pixel)

C151 = 1uF ~ 10uF

11/06 For layout change

11/06 For layout change

R62

10K

1 2

Q172N3904

1

2

3

R5147K

J315x2PIN/2.0

252523232121191917171515131311119977553311

26 2624 2422 2220 2018 1816 1614 1412 1210 108 86 64 42 2

2727 28 28

2929 30 30R479 331 2

C130.1uF

CN1

12V612V5

BRI_ON/OFF4

BRI_ADJ3GND2

GND1

R5010K

D65NC/1N4002

R31K

G23_5mm_8via

4 5

67

9

123

8

R5447K

EC11100uF/16V

R478 331 2

D64NC/1N4002

R3010K

JP1SIP3/2.54 1 2 3

C23

56pFC-0603

R477331 2

R480 331 2

+ EC7

100uF/16V

R32

4.7K

R547K

R340ohm-0805

R61

10K

1 2

Q62N3904

12

3

G33_5mm_8via

4 5

67

9

123

8R24

1K

Q13NDS9435A/SO

2345 76 8

1

R55847K1 2

L1NC

R6675R

Q72N3904

1

2

3

R281K

C9

1uF

C-0603

G13_5mm_8via

4 5

67

9

123

8

FB2

120/100M

C2571uF

C-0603


55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CVBS3_INCVBS_TV1CVBS_TV

T UNER_SCLT UNER_SDA

SDA_M

CVBS_TV1

TUNER_4MHz

SCL_M

RF_ AGC

RF_ AGC

T UNER_ RF_AGC

TUNER_4MHz

T UNER_SDA

T UNER_SCL

IF_OUT

CVBS3_IN

TU_SDA T_SDAT_SCLTU_SCL

IFAGC_ ONOFF

IFAGC_ ONOFF

IF_OUT

IF_OUT1

IF_OUT1

CVBS_TV1 ATV_SCART

ATV_SCART

TU_SCART

TU_SCART

T UNER_ RF_AGC

IF_OUT1

CVBSO

+T5V_BOOSTER

GNDTA

+5V_SW

GNDTA

+T5V_IFGNDTA

+TUN_5V

GNDV GNDVGNDVGNDV

GNDTD GNDV

GNDTA

GNDTA

GNDTA

GNDTA

GNDTA

GNDTA

+5V_SW

+5V_SW_4052

+5V_SW

+T5V_IF

+T5V_BOOSTER

+T5V_IF

+TUN_5V

GNDTD

GNDTA

GNDTA

GNDTAGNDTA GNDTA

GNDTA

GNDTA

GNDTAGNDTA

GNDTA

GNDTA

GNDTA

GNDTA GNDTA

GNDTA

GNDTA

GNDV

GNDTA

+T5V

_IF

+T5V_IF

GNDTD

GNDTD+T5V_IF

GNDTA

GNDTA

GNDTA

GNDTA

GNDTA

GNDTA

GNDTA

+ANT_5V

+ANT_5V

+TUN_5V

GNDTA

GNDTA GNDTA

GNDTA

DTV_CVBS13

SDA_M7,9,13SCL_M7,9,13

I2 C_SW7

IFD2 13

IFD1 13

IFAGC 13

SIFAIN0 7

CVBS3_IN 7

T_SCL 12T_SDA 12

TU_SCART 7

CVBSO

Sh o rt_Protect 18

ANT _POWER 18

Title



TUNER PARTC


SUNPLUS

(to SPV7100)


Tuner TO SPV710010/25 Add

Close to IFAGC NET

Close to CN9

Close to FB37

Close to FB12

Close to XT1

A,B,C=L ===> DTVA,B,C=H ===> ATV

Close to 2nd_IF NET

2.54..

FB30

L-0805120/100M

1 2

TR5100K

R3511K

TR3470

ncD48

R17633R R-060312

C2010.1uFC-0603

12

C30

50.

01uF

C192330pF

C346100pF

NC/4 .7RR545

100R407

D59BA277

C3990 .0 1 uF/NC

TR410K

75RR542

TC10.1uFC0603

12

C29

40.

22uF

0RR399

NC/5 10RR543

33R388

C193220pF

R4029.1K

EC89N C

R169

33R R-060312

C194470pF

U22

PI5V330

1A2

1B51C11

1D14

2A3

2B6

2C10

2D13

A 4

B 7C 9

D 12

EN 15

S 1

VC

C16

VS

S8

R267 0R

5.6KR410

C187470pF

D58BA277

C2980.1uF

C29

10.

01uF

C27910uFC-0805

12

+

C401 100uF/16V

Q652N3904

1

2

3

C398NC/0 .01uF

6.8KR380

R156 0R

SAW

Z1 K9456D

11

22 33

4 4

5 5

R281 0R

22KR381

C300 0.1uF

CDT-9DT33C-40T1

5V_ANT 1

RF_AGC 2

ADDRESS 3

SCL 4

SDA 5

REF_4MHz 6

5VCC 7

IF_OUT 8

IF_AGC 9

IF_OUT1 10

IF_OUT2 11

GN

D12

GN

D13

GN

D14

GN

D15

GN

D16

GN

D17 R404

1K

C29

215

00pF

akira lh185s92dt manual de servicio lcd

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