ALGORITHMS FOR VLSIPHYSICAL DESIGN AUTOMATION

THIRD EDITION

ALGORITHMS FOR VLSIPHYSICAL DESIGN AUTOMATION

THIRD EDITION

Naveed A. SherwaniIntel Corporation.

KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: 0-306-47509-XPrint ISBN: 0-7923-8393-1

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Dordrecht

To my parentsAkhter and Akram Sherwani

Contents

Foreword xvii

Preface xix

Acknowledgements xxvii

1 VLSI Physical Design Automation 1379

1.11.21.31.41.5

VLSI Design CycleNew Trends in VLSI Design CyclePhysical Design CycleNew Trends in Physical Design CycleDesign Styles1.5.11.5.21.5.31.5.41.5.51.5.6

Full-CustomStandard CellGate ArraysField Programmable Gate ArraysSea of GatesComparison of Different Design Styles

1.6 System Packaging Styles1.6.1 Die Packaging and Attachment Styles

1.6.1.11.6.1.2

Die Package StylesPackage and Die Attachment Styles

1.6.21.6.31.6.41.6.5

Printed Circuit BoardsMultichip ModulesWafer Scale IntegrationComparison of Different Packaging Styles

1.71.81.9

Historical PerspectivesExisting Design ToolsSummary

13151718202225252626262727293131323335

3940434345

2 Design and Fabrication of VLSI Devices2.12.2

Fabrication MaterialsTransistor Fundamentals2.2.12.2.2

Basic Semiconductor JunctionTTL Transistors

viii Contents

2.2.3 MOS Transistors2.3 Fabrication of VLSI Circuits

2.3.12.3.22.3.3

nMOS Fabrication ProcessCMOS Fabrication ProcessDetails of Fabrication Processes

2.42.5

Design RulesLayout of Basic Devices2.5.12.5.22.5.3

InvertersNAND and NOR GatesMemory Cells2.5.3.12.5.3.2

Static Random Access Memory (SRAM)Dynamic Random Access Memory (DRAM)

2.62.7

SummaryExercises

3 Fabrication Process and its Impact on Physical Design3.13.2

Scaling MethodsStatus of Fabrication Process3.2.1 Comparison of Fabrication Processes

3.3 Issues related to the Fabrication Process3.3.13.3.23.3.33.3.43.3.53.3.63.3.7

Parasitic EffectsInterconnect DelayNoise and CrosstalkInterconnect Size and ComplexityOther Issues in InterconnectPower DissipationYield and Fabrication Costs

3.4 Future of Fabrication Process3.4.13.4.23.4.3

SIA RoadmapAdvances in LithographyInnovations in Interconnect3.4.3.13.4.3.23.4.3.33.4.3.4

More Layers of MetalLocal InterconnectCopper InterconnectUnlanded Vias

3.4.43.4.53.4.6

Innovations/Issues in DevicesAggressive Projections for the ProcessOther Process Innovations3.4.6.13.4.6.2

Silicon On InsulatorSilicon Germaniun

3.53.63.73.8

Solutions for Interconnect IssuesTools for Process DevelopmentSummaryExercises

4648515353586262646667697171

7576777779798081828282838585868787878788888990909091939494

Contents ix

4 Data Structures and Basic Algorithms 974.14.2

Basic Terminology 99Complexity Issues and NP-hardness4.2.1 Algorithms for NP-hard Problems

4.2.1.14.2.1.24.2.1.34.2.1.4

Exponential AlgorithmsSpecial Case AlgorithmsApproximation AlgorithmsHeuristic Algorithms

4.3 Basic Algorithms4.3.1 Graph Algorithms

4.3.1.14.3.1.24.3.1.34.3.1.44.3.1.54.3.1.6

Graph Search AlgorithmsSpanning Tree AlgorithmsShortest Path AlgorithmsMatching AlgorithmsMin-Cut and Max-Cut AlgorithmsSteiner Tree Algorithms

4.3.2 Computational Geometry Algorithms4.3.2.14.3.2.2

Line Sweep MethodExtended Line Sweep Method

4.4 Basic Data Structures4.4.14.4.24.4.34.4.44.4.54.4.64.4.74.4.8

Atomic Operations for Layout EditorsLinked List of BlocksBin-Based MethodNeighbor PointersCorner StitchingMulti-layer OperationsLimitations of Existing Data StructuresLayout Specification Languages

4.5 Graph Algorithms for Physical design4.5.1 Classes of Graphs in Physical Design

4.5.1.14.5.1.2

Graphs Related to a Set of LinesGraphs Related to Set of Rectangles

4.5.24.5.34.5.4

Relationship Between Graph ClassesGraph Problems in Physical DesignAlgorithms for Interval Graphs4.5.4.14.5.4.2

Maximum Independent SetMaximum Clique and Minimum Coloring

4.5.5 Algorithms for Permutation Graphs4.5.5.14.5.5.2

Maximum Independent SetMaximum -Independent Set

4.5.6 Algorithms for Circle Graphs4.5.6.14.5.6.24.5.6.3

Maximum Independent SetMaximum -Independent SetMaximum Clique

4.64.7

SummaryExercises

100101102102102103104104104106108110110111115115115117117119120122123130131131135135136138138140142142143144144146148148149151151152

x Contents

5 Partitioning 1575.1 Problem Formulation

5.1.1 Design Style Specific Partitioning Problems5.25.3

Classification of Partitioning AlgorithmsGroup Migration Algorithms5.3.15.3.2

Kernighan-Lin AlgorithmExtensions of Kernighan-Lin Algorithm5.3.2.15.3.2.25.3.2.35.3.2.4

Fiduccia-Mattheyses AlgorithmGoldberg and Burstein AlgorithmComponent ReplicationRatio Cut

5.4 Simulated Annealing and Evolution5.4.15.4.2

Simulated AnnealingSimulated Evolution

5.5 Other Partitioning Algorithms5.5.1 Metric Allocation Method

5.65.75.8

Performance Driven PartitioningSummaryExercises

163166168169170171173174174176177177179183183185187187

6 Floorplanning and Pin Assignment 1916.1 Floorplanning

6.1.1 Problem Formulation6.1.1.1 Design Style Specific Floorplanning Problems

6.1.26.1.36.1.46.1.56.1.66.1.7

Classification of Floorplanning AlgorithmsConstraint Based FloorplanningInteger Programming Based FloorplanningRectangular DualizationHierarchical Tree Based MethodsFloorplanning Algorithms for Mixed Block and Cell De-signs

6.1.86.1.96.1.106.1.11

Simulated Evolution AlgorithmsTiming Driven FloorplanningTheoretical advancements in FloorplanningRecent Trends

6.2 Chip planning6.2.1 Problem Formulation

6.3 Pin Assignment6.3.1 Problem Formulation

6.3.1.1 Design Style Specific Pin Assignment Problems6.3.26.3.36.3.4

Classification of Pin Assignment AlgorithmsGeneral Pin AssignmentChannel Pin Assignment

6.46.56.6

Integrated ApproachSummaryExercises

193193194194196198200201

203203204205206207207207208208209210211214217217

Contents xi

7 Placement 2197.1 Problem Formulation

7.1.1 Design Style Specific Placement Problems7.27.3

Classification of Placement AlgorithmsSimulation Based Placement Algorithms7.3.17.3.27.3.37.3.4

Simulated AnnealingSimulated EvolutionForce Directed PlacementSequence-Pair Technique

7.3.5 Comparison of Simulation Based Algorithms7.4 Partitioning Based Placement Algorithms

7.4.17.4.2

Breuer’s AlgorithmTerminal Propagation Algorithm

7.5 Other Placement Algorithms7.5.17.5.27.5.37.5.4

Cluster GrowthQuadratic AssignmentResistive Network OptimizationBranch-and-Bound Technique

7.67.77.87.9

Performance Driven PlacementRecent TrendsSummaryExercises

220223225225226229232233233236236236239240240241241242242243244244

8 Global Routing 2478.1 Problem Formulation

8.1.1 Design Style Specific Global Routing Problems253257

8.2 Classification of Global RoutingAlgorithms

8.3 Maze Routing Algorithms8.3.18.3.28.3.38.3.4

Lee’s AlgorithmSoukup’s AlgorithmHadlock’s AlgorithmComparison of Maze Routing Algorithms

8.48.58.6

Line-Probe AlgorithmsShortest Path Based AlgorithmsSteiner Tree based Algorithms8.6.18.6.28.6.38.6.4

Separability Based AlgorithmNon-Rectilinear Steiner Tree Based AlgorithmSteiner Min-Max Tree based AlgorithmWeighted Steiner Tree based Algorithm

8.7 Integer Programming Based Approach8.7.1 Hierarchical Approach

8.88.98.10

Performance Driven RoutingSummaryExercises

260261261263264267269272273274277279281282282286287288

xii Contents

9 Detailed Routing9.1 Problem Formulation

291293293295297302302303304306306311312316316318320320321321323325329330334338340345345346346348349352353354355358358362362363

9.1.19.1.29.1.39.1.49.1.5

Routing ConsiderationsRouting ModelsChannel Routing ProblemsSwitchbox Routing ProblemsDesign Style Specific Detailed Routing Problems

9.29.3

Classification of Routing AlgorithmsSingle-Layer Routing Algorithms9.3.1 General River Routing Problem

9.3.1.1 General River Routing Algorithm9.3.2 Single Row Routing Problem

9.3.2.19.3.2.29.3.2.39.3.2.4

Origin of Single Row RoutingA Graph Theoretic ApproachAlgorithm for Street Congestion MinimizationAlgorithm for Minimizing Doglegs

9.4 Two-Layer Channel Routing Algorithms9.4.19.4.2

Classification of Two-Layer AlgorithmsLEA based Algorithms9.4.2.19.4.2.29.4.2.3

Basic Left-Edge AlgorithmDogleg RouterSymbolic Channel Router: YACR2

9.4.3 Constraint Graph based Routing Algorithms9.4.3.19.4.3.2

Net Merge Channel RouterGlitter: A Gridless Channel Router

9.4.49.4.59.4.6

Greedy Channel RouterHierarchical Channel RouterComparison of Two-Layer Channel Routers

9.5 Three-Layer Channel Routing Algorithms9.5.19.5.29.5.39.5.4

Classification of Three-Layer AlgorithmsExtended Net Merge Channel RouterHVH Routing from HV SolutionHybrid HVH-VHV Router

9.69.7

Multi-Layer Channel Routing AlgorithmsSwitchbox Routing Algorithms9.7.19.7.29.7.39.7.49.7.5

Classification of switchbox routing algorithmsGreedy RouterRip-up and Re-route Based RouterComputational Geometry Based RouterComparison of Switchbox Routers

9.89.9

SummaryExercises

Contents xiii

10 Over-the-Cell Routing and Via Minimization 369370371373373377389396398398400401

403407

408

409410410411

417418419422423426427427428429430432433436439439440444444

10.1 Over-the-cell Routing10.1.110.1.2

Cell ModelsTwo-Layer Over-the-Cell Routers10.1.2.110.1.2.210.1.2.3

Basic OTC Routing AlgorithmPlanar Over-the-Cell RoutingOver-the-Cell Routing Using Vacant Terminals

10.1.310.1.410.1.5

Three-Layer Over-the-cell RoutingMultilayer OTC RoutingPerformance Driven Over-the-cell Routing

10.2 Via Minimization10.2.1 Constrained Via Minimization Problem

10.2.1.1 Graph Representation of Two-Layer CVM Prob-lem

10.2.2 Unconstrained Via Minimization10.2.2.1

10.2.2.2

10.2.2.3

Optimal Algorithm for Crossing-Channel TVMProblemApproximation Result for General k-TVM Prob-lemRouting Based on Topological Solution

10.310.4

SummaryExercises

11 Clock and Power Routing11.1 Clock Routing

11.1.111.1.2

Clocking SchemesDesign Considerations for the Clocking System11.1.2.1 Delay Calculation for Clock Trees

11.1.3 Problem Formulation11.1.3.1 Design Style Specific Problems

11.1.4 Clock Routing Algorithms11.1.4.111.1.4.211.1.4.311.1.4.411.1.4.511.1.4.6

H-tree Based AlgorithmThe MMM AlgorithmGeometric Matching based AlgorithmWeighted Center AlgorithmExact Zero Skew AlgorithmDME Algorithm

11.1.511.1.6

Skew and Delay Reduction by Pin AssignmentMultiple Clock Routing

11.211.311.4

Power and Ground RoutingSummaryExercises

xiv Contents

12 Compaction12.1 Problem Formulation

449450450451452453454460463463463464464467468470473473473474474475476476

479480485485489490492493494496497

501502505507510512512513514

12.1.1 Design Style Specific Compaction Problem12.212.3

Classification of Compaction AlgorithmsOne-Dimensional Compaction12.3.1 Constraint-Graph Based Compaction

12.3.1.112.3.1.212.3.1.312.3.1.4

Constraint Graph GenerationCritical Path AnalysisWire JoggingWire Length Minimization

12.3.2 Virtual Grid Based Compaction12.3.2.112.3.2.212.3.2.3

Basic Virtual Grid AlgorithmSplit Grid CompactionMost Recent Layer Algorithm

12.412.5

CompactionTwo-Dimensional Compaction12.5.1 Simulated Annealing based Algorithm

12.6 Hierarchical Compaction12.6.1 Constraint-Graph Based Hierarchical Compaction

12.7 Recent trends in compaction12.7.112.7.2

Performance-driven compactionCompaction techniques for yield enhancement

12.812.9

SummaryExercises

13 Physical Design Automation of FPGAs13.113.213.313.4

FPGA TechnologiesPhysical Design Cycle for FPGAsPartitioningRouting13.4.113.4.2

Routing Algorithm for the Non-Segmented ModelRouting Algorithms for the Segmented Model13.4.2.113.4.2.2

Basic AlgorithmRouting Algorithm for Staggered Model

13.513.6

SummaryExercises

14 Physical Design Automation of MCMs14.114.214.314.4

MCM TechnologiesMCM Physical Design CyclePartitioningPlacement14.4.114.4.2

Chip Array Based ApproachFull Custom Approach

14.5 Routing14.5.1 Classification of MCM Routing Algorithms

Contents xv

14.5.214.5.3

Maze Routing 514515515517517517519519521521

Multiple Stage Routing14.5.3.114.5.3.214.5.3.3

Pin Redistribution ProblemLayer AssignmentDetailed Routing

14.5.414.5.514.5.6

Topological RoutingIntegrated Pin Distribution and RoutingRouting in Programmable Multichip Modules

14.614.7

SummaryExercises

Bibliography 525

Author Index 563

Subject Index 567

Foreword

Since the invention of integrated circuits thirty years ago, manufacturing ofelectronic systems has taken rapid strides in improvement in speed, size, andcost. For today’s integrated circuit chips, switching time is on the order ofnanoseconds, minimum feature size is on the order of sub-microns, transistorcount is on the order of millions, and cost is on the order of a few dollars.In fact, it was estimated that the performance/cost ratio of integrated circuitchips has been increasing at the rate of one thousand-fold every ten years,yielding a total of for the last three decades. A combination of high productperformance and low per-unit cost leads to the very pervasive introduction ofintegrated circuit chips to many aspects of modern engineering and scientificendeavors including computations, telecommunications, aeronautics, genetics,bioengineering, manufacturing, factory automation, and so on. It is clear thatthe integrated circuit chip will play the role of a key building block in theinformation society of the twenty-first century.

The manufacture of integrated circuit chips is similar to the manufactureof other highly sophisticated engineering products in many ways. The threemajor steps are designing the product, fabricating the product, and testing thefabricated product. In the design step, a large number of components are tobe designed or selected, specifications on how these components should be as-sembled are to be made, and verification steps are to be carried out to assurethe correctness of the design. In the manufacturing step, a great deal of man-power, and a large collection of expensive equipment, together with painstakingcare are needed to assemble the product according to the design specification.Finally, the fabricated product must be tested to check its physical function-ality. As in all engineering problems, there are conflicting requirements in allthese steps. In the design step, we want to obtain an optimal product design,and yet we also want the design cycle to be short. In the fabrication step, wewant the product yield to be high, and yet we also need to be able to producea large volume of the product and get them to market in time. In the testingstep, we want the product to be tested thoroughly and yet we also want to beable to do so quickly.

The title of this book reveals how the issue of enormous design complexityis to be handled so that high quality designs can be obtained in a reason-able amount of design time: We use muscles (automation) and we use brain

xviii

(algorithms). Professor Sherwani has written an excellent book to introducestudents in computer science and electrical engineering as well as CAD engi-neers to the subject of physical design of VLSI circuits. Physical design is akey step in the design process. Research and development efforts in the lasttwenty years have led us to some very good understanding on many of theimportant problems in physical design. Professor Sherwani’s book provides atimely, up-to-date integration of the results in the field and will be most usefulboth as a graduate level textbook and as a reference for professionals in thefield. All aspects of the physical design process are covered in a meticulousand comprehensive manner. The treatment is enlightening and enticing. Fur-thermore, topics related to some of the latest technology developments such asField Programmable Gate Arrays (FPGA) and Multi-Chip Modules (MCM)are also included. A strong emphasis is placed on the algorithmic aspect ofthe design process. Algorithms are presented in an intuitive manner withoutthe obscurity of unnecessary formalism. Both theoretical and practical aspectsof algorithmic design are stressed. Neither the elegance of optimal algorithmsnor the usefulness of heuristic algorithms are overlooked. ¿From a pedagogicalpoint of view, the chapters on electronic devices and on data structures and ba-sic algorithms provide useful background material for students from computerscience, computer engineering, and electrical engineering. The many exercisesincluded in the book are also most helpful teaching aids.

This is a book on physical design algorithms. Yet, this is a book thatgoes beyond physical design algorithms. There are other important designsteps of which our understanding is still quite limited. Furthermore, develop-ment of new materials, devices, and technologies will unquestionably create newproblems and new avenues of research and development in the design process.An algorithmic outlook on design problem and the algorithmic techniques forsolving complex design problems, which a reader learns through the examplesdrawn from physical design in this book, will transcend the confine of physicaldesign and will undoubtedly prepare the reader for many of the activities inthe field of computer-aided design of VLSI circuits. I expect to hear from manystudents and CAD professionals in the years to come that they have learned agreat deal about physical design, computer-aided design, and scientific researchfrom Professor Sherwani’s book. I also expect to hear from many of them thatProfessor Sherwani’s book is a source of information as well as a source of in-spiration.

Urbana-Champaign, September 1992 C. L. Liu

Preface

From its humble beginning in the early 1950’s to the manufacture of circuitswith millions of components today, VLSI design has brought the power of themainframe computer to the laptop. Of course, this tremendous growth in thearea of VLSI design is made possible by the development of sophisticated designtools and software. To deal with the complexity of millions of components andto achieve a turn around time of a couple of months, VLSI design tools mustnot only be computationally fast but also perform close to optimal.

The future growth of VLSI systems depends critically on the research anddevelopment of Physical Design (PD) Automation tools. In the last two decades,the research in physical design automation has been very intense, and literallythousands of research articles covering all phases of physical design automationhave been published. The development of VLSI physical design automation alsodepends on availability of trained manpower. We have two types of studentsstudying VLSI physical design: students preparing for a research career andstudents preparing for a career in industry. Both types of students need tobuild a solid background. However, currently we lack courses and text bookswhich give students a comprehensive background. It is common to find stu-dents doing research in placement, but are unaware of the latest developmentsin compaction. Those students seeking careers in industry will find that theVLSI physical design industry is very fast paced. They are expected to be con-versant with existing tools and algorithms for all the stages of the design cycleof a VLSI chip. In industry, it is usual to find CAD engineers who work on oneaspect of physical design and lack knowledge of other aspects. For example,a CAD engineer working in the development of detailed routers may not beknowledgeable about partitioning algorithms. This is again due to the lackof comprehensive textbooks which cover background material in all aspects ofVLSI physical design.

Providing a comprehensive background in one textbook in VLSI physicaldesign is indeed difficult. This is due to the fact that physical design automa-tion requires a mix of backgrounds. Some electrical engineering and a solidundergraduate computer science background is necessary to grasp the funda-mentals. In addition, some background in graph theory and combinatorics isalso needed, since many of the algorithms are graph theoretic or use othercombinatorial optimization techniques. This mix of backgrounds has perhaps

xx

restricted the development of courses and textbooks in this very area.This book is an attempt to provide a comprehensive background in the

principles and algorithms of VLSI physical design. The goal of this book is toserve as a basis for the development of introductory level graduate courses inVLSI physical design automation. It is hoped that the book provides self con-tained material for teaching and learning algorithms of physical design. Allalgorithms which are considered basic have been included. The algorithms arepresented in an intuitive manner, so that the reader can concentrate on thebasic idea of the algorithms. Yet, at the same time, enough detail is providedso that readers can actually implement the algorithms given in the text anduse them.

This book grew out of a graduate level class in VLSI physical design au-tomation at Western Michigan University. Initially written as a set of classnotes, the book took form as it was refined over a period of three years.

Overview of the Book

This book covers all aspects of physical design. The first three chaptersprovide the background material, while the focus of each chapter of the restof the book is on each phase of the physical design cycle. In addition, newertopics like physical design automation of FPGAs and MCMs have also beenincluded.

In Chapter 1, we give an overview of the VLSI physical design automationfield. Topics include the VLSI design cycle, physical design cycle, design stylesand packaging styles. The chapter concludes with a brief historical review ofthe field.

Chapter 2 discusses the fabrication process for VLSI devices. It is importantto understand the fabrication technology in order to correctly formulate theproblems. In addition, it is important for one to understand, what is doableand what is not! Chapter 2 presents fundamentals of MOS and TTL transistors.It then describes simple NAND and NOR gates in nMOS and CMOS.

Chapter 3 presents the status of fabrication process, as well as, processinnovations on the horizons and studies its impact on physical design. We alsodiscuss several other factors such as design rules, yield, delay, and fabricationcosts involved in the VLSI process.

Basic material on data structures and algorithms involved in the physicaldesign is presented in Chapter 4. Several different data structures for layouthave been discussed. Graphs which are used to model several different problemsin VLSI design are defined and basic algorithms for these graphs are presented.

Chapter 5 deals with partitioning algorithms. An attempt has been madeto explain all the possible factors that must be considered in partitioning theVLSI circuits. Group migration, simulated annealing and simulated evolutionalgorithms have been presented in detail. The issue of performance drivenpartitioning is also discussed.

In Chapter 6, we discuss basic algorithms for floorplanning and pin assign-ment. Several different techniques for placement such as, simulated annealing,

xxi

simulated evolution, and force-directed are discussed in Chapter 7.Chapter 8 deals with global routing. It covers simple routing algorithms,

such as maze routing, and more advanced integer programming based methods.It also discusses Steiner tree algorithms for routing of multiterminal nets.

Chapter 9 is the longest chapter in the book and represents the depthof knowledge that has been gained in the detailed routing area in the lastdecade. Algorithms are classified according to the number of layers allowed forrouting. In single layer routing, we discuss general river routing and the singlerow routing problem. All major two-layer channel and switch box routers arealso presented. The chapter also discusses three-layer and multilayer routingalgorithms.

Chapter 10 discusses two ways of improving layouts after detailed routing,namely, via minimization and over-the-cell routing. Basic algorithms for viaminimization are presented. Over-the-cell routing is a relatively new techniquefor reducing routing areas. We present the two latest algorithms for over-the-cell routing.

The problems of routing clock and power/ground nets are discussed inChapter 11. These topics play a key role in determining the layout of highperformance systems. Circuit compaction is discussed in Chapter 12. One di-mensional compaction, as well as two dimensional compaction algorithms arepresented.

Field Programmable Gate Arrays (FPGAs) are rapidly gaining ground inmany applications, such as system prototyping. In Chapter 13, we discussphysical design automation problems and algorithms for FPGAs. In particular,we discuss the partitioning and routing problems in FPGAs. Both of theseproblems are significantly different from problems in VLSI. Many aspects ofphysical design of FPGAs remain a topic of current research.

Multi-Chip Modules (MCMs) are replacing conventional printed circuitboards in many applications. MCMs promise high performance systems ata lower cost. In Chapter 14, we explore the physical design issues in MCMs. Inparticular, the routing problem of MCMs is a true three dimensional problem.MCMs are currently a topic of intense research.

At the end of each chapter, a list of exercises is provided, which range incomplexity from simple to research level. Unmarked problems and algorithmsare the simplest. The exercises marked with (†) are harder and algorithms inthese exercises may take a significant effort to implement. The exercises andalgorithms marked with (‡) are the hardest. In fact, some of these problemsare research problems.

Bibliographic notes can be found at the end of each chapter. In these notes,we give pointers to the readers for advanced topics. An extensive bibliographyis presented at the end of the text. This bibliography is complete, to the bestof our knowledge, up to the September of 1998. An attempt has been made toinclude all papers which are appropriate for the targeted readers of this text.The readers may also find the author and the subject index at the back of thetext.

xxii

Overview of the Second Edition

In 1992, when this book was originally published, the largest microprocessorhad one million transistors and fabrication process had three metal layers. Wehave now moved into a six metal layer process and 15 million transistor micro-processors are already in advanced stages of design. The designs are movingtowards a 500 to 700 Mhz frequency goal. This challenging frequency goal, aswell as, the additional metal layers have significantly altered the VLSI field.Many issues such as three dimensional routing, Over-the-Cell routing, earlyfloorplanning have now taken a central place in the microprocessor physicaldesign flow. This changes in the VLSI design prompted us to reflect these inthe book. That gave birth to the idea of the second edition.

The basic purpose of the second edition is to introduce a more realisticpicture to the reader exposing the concerns facing the VLSI industry whilemaintaining the theoretical flavor of the book. New material has been addedto all the chapters. Several new sections have been added to many chapters.Few chapters have been completely rewritten. New figures have been added tosupplement the new material and clarify the existing material.

In summary, I have made an attempt to capture the physical design flowused in the industry and present it in the second addition. I hope that readerswill find that information both useful and interesting.

Overview of the Third Edition

In 1995, when we prepared the 2nd edition of this book, a six metal layerprocess and 15 million transistor microprocessors were in advanced stages ofdesign. In 1998, six metal process and 20 million transistor designs are in pro-duction. Several manufacturers have moved to 0.18 micron process and copperinterconnect. One company has announced plans for 0.10 micron process andplans to integrate 200 to 400 million transistors on a chip. Operating frequencyhas moved from 266 Mhz (in 1995) to 650 Mhz and several Ghz experimentalchips have been demonstrated. Interconnect delay has far exceeded device de-lay and has become a dominant theme in physical design. Process innovationssuch as copper, low k dielectrics, multiple threshold devices, local interconnectare once again poised to change physical design once again.

The basic purpose of the third edition is to investigate the new challengespresented by interconnect and process innovations. In particular, we wanted toidentify key problems and research areas that physical design community needsto invest in order to meet the challenges. We took a task of presenting thoseideas while maintaining the flavor of the book. As a result, we have added twonew chapters and new material has been added to most of the chapters. A newchapter on process innovation and its impact on physical design has been added.Another focus of the book has been to promote use of Internet as a resource,so wherever possible URLs has been provided for further investigation.

Chapters 1 and 2 have been updated. Chapter 3 is a new chapter on thefabrication process and its impact. Chapter 4 (algorithms) and Chapter 5

xxiii

(partitioning) have been edited for clarity. Chapter on Floorplanning, Place-ment and Pin Assignment has been split into Chapter 6 (Floorplanning) andChapter 7 (Placement) to bring sharper focus to floorplanning. New sequencepair algorithms have been added to Chapter 7 (Placement) Chapter 8 and 9have been edited for clarity and references have been updated as appropriate.New sections have been added to Chapter 10, Chapter 11 and Chapter 12. InChapter 10, we have added material related to performance driven routing. InChapter 11, DME algorithm has been added. In Chapter 12, we have addednew compaction algorithms. Chapters 13 (FPGAs) and 14 (MCMs) have beenupdated. We have made an attempt to update the bibliography quite exten-sively and many new items have been added.

In summary, I have made an attempt to capture the impact of interconnectand process innovations on physical design flow. I have attempted to balancematerial on new innovations with the classical content of the 2nd edition. Ihope that readers will find that information both useful and interesting.

To the Teacher

This book has been written for introductory level graduate students. Itpresents concepts and algorithms in an intuitive manner. Each chapter contains3 to 4 algorithms that have been discussed in detail. This has been done so asto assist students in implementing the algorithms. Other algorithms have beenpresented in a somewhat shorter format. References to advanced algorithmshave been presented at the end of each chapter. Effort has been made to makethe book self contained.

This book has been developed for a one-semester or a two-semester coursein VLSI physical design automation. In a one-semester course, it is recom-mended that chapters 8, 9, 11, and 12 be omitted. A half-semester algorithmdevelopment project is highly recommended. Implementation of algorithms isan important tool in making students understand algorithms. In physical de-sign, the majority of the algorithms are heuristic in nature and testing of thesealgorithms on benchmarks should be stressed. In addition, the development ofpractical algorithms must be stressed, that is, students must be very aware ofthe complexity of the algorithms. An optimal algorithm may be imprac-tical for an input of size 10 million. Several (†) marked problems at the end ofeach chapter may serve as mini-projects.

In a two-semester class, it is recommended that all the chapters be included.Reading state-of-art papers must be an integral part of this class. In particular,students may be assigned papers from proceedings of DAC and ICCAD orfrom IEEE Transactions on CAD. Papers from Transactions typically requirea little more mathematical maturity than the papers in DAC and ICCAD. Animportant part of this class should be a two-semester project, which may bethe development of a new algorithm for some problem in physical design. Atypical first part of the project may involve modifying an existing algorithmfor a special application. Some (‡) problems may serve as projects.

In both the courses, a good background in hand layout is critical. It is

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expected that students will have access to a layout editor, such as MAGIC orLEDIT. It is very important that students actually layout a few small circuits.For examples see exercises at the end of Chapter 2.

For faculty members, a teaching aid package, consisting of a set of 400 over-heads (foils) is available from the author. These are quite helpful in teachingthe class, as all the important points have been summarized on section by sec-tion basis. In order to obtain these foils, please send an email (or a mail) tothe author, at the address below.

To the Student

First and foremost, I hope that you will enjoy reading this book. Everyeffort has been made to make this book easy to read. The algorithms havebeen explained in an intuitive manner. The idea is to get you to develop newalgorithms at the end of the semester. The book has been balanced to givea practical as well as a theoretical background. In that sense, you will findit useful, if you are thinking about a career in industry or if you are thinkingabout physical design as a possible graduate research topic.

What do you need to start reading this book? Some maturity in generalalgorithm techniques and data structures is assumed. Some electrical engi-neering background and mathematics background will be helpful, although notnecessary. The book is self-contained to a great extent and does not need anysupporting text or reference text.

If you are considering a career in this field, I have one important piece ofadvise for you. Research in this field moves very fast. As a result, no textbookcan replace state-of-the-art papers. It is recommended that you read papersto keep you abreast of latest developments. A list of conference proceedingsand journals appears in the bibliographic notes of Chapter 1. I also recom-mend attending DAC and ICCAD conferences every year and a membership inACM/SIGDA, IEEE/DATC and IEEE/TC-VLSI.

To the CAD Professional

This book provides a detailed description of all aspects of physical designand I hope you have picked up this book to review your basics of physical de-sign. While it concentrates on basic algorithms, pointers are given to advancedalgorithms as well. The text has been written with a balance of theory andpractice in mind. You will also find the extensive bibliography useful for findingadvanced material on a topic.

Errors and Omissions

No book is free of errors and omissions. Despite our best attempt, thistext may contain some errors. If you find any errors or have any constructivesuggestions, I would appreciate receiving your comments and suggestions. Inparticular, new exercises would certainly be very helpful. You can mail your

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comments to:

Naveed SherwaniIntel Corporation, Mail Stop: JFT-1042111 N. E. 25th AvenueHillsboro, OR 97124-5961

or email them to sherwaan@ichips.intel.com.A concentrated effort has been made to include all pertinent references to

papers and books that we could find. If you find omissions in the book, pleasefeel free to remind me.

This book was typeset in Latex. Figures were made using ‘xfig’ and in-serted directly into the text as .ps files using ‘transfig’. The bibliography wasgenerated using Bibtex and the index was generated with a program writtenby Siddharth Bhingarde.

Portland, March, 1998 Naveed A. Sherwani

Acknowledgments

No book is a product of one person. The same is true for this book. FirstI must thank all members of the nitegroup who worked tirelessly for daysand nights (mostly nights) for the final six months. First I would like tothank Siddharth Bhingarde, Surendra Burman, Moazzem Hossain, ChandarKamalanathan, Wasim Khan, Arun Shanbhag, Timothy Strunk and Qiong Yu.Thanks are also to due to nitegroup members who have graduated. In par-ticular Roshan Gidwani, Jahangir Hashmi, Nancy Holmes, and Bo Wu, whohelped in all stages of this project. Special thanks are due to the youngestmember of nitegroup, Timothy Strunk, who made (almost) all the figures inthe text and brought enthusiasm to the team. Thanks are also due to AnandPanyam, Konduru Nagesh and Aizaz Manzar for helping in the final stages ofthis project. Many students in my class CS520 (Introduction to VLSI designautomation) suffered through earlier version of this book, and I would like tothank them for their constructive suggestions.

Several colleagues and friends contributed significantly by reviewing severalchapters and using parts of the book in their courses. In this regard, I wouldlike to thank Jeff Banker, Ajay Gupta, Mark Kerstetter, Sartaj Sahni, andJason Cong. I would also like to especially thank Dinesh Mehta and Si-QingZheng. I wish to express my sincere thanks to Malgorzata Marek-Sadowska,who made very critical remarks and contributions to the improvement in thequality of the text.

Thanks are due to two special people, who have contributed very generouslyin my career and helped in many ways. I would like to thank Vishwani Agrawaland C. L. Liu for their constant encouragement and sound words of advise.

I would like to thank several different organizations who have contributeddirectly to this project. First, I would like to thank Ken Wan, and the restof the CTS group at Advanced Micro Devices for helping with many technicaldetails. I would also like to thank ACM SIGDA for supporting our researchduring the last four years. Thanks are also due to Western Michigan University,and in particular Donald Nelson and Douglas Ferraro, who, despite all costs,made the necessary facilities available to complete this book. The NationalScience Foundation deserves thanks for supporting the VLSI laboratory andour research at Western Michigan University. I would also like to thank RezaRashidi and the staff of FRC laboratory for their help in printing the text and

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cover design.I would also like to thank our system manager Patty Labelle, who cheerfully

accepted our occasional abuse of the system and kept all the machines up whenwe needed them. I must also thank our department secretaries Phyllis Wolfand Sue Moorian for being very helpful during all stages of this project.

I must thank my copy editor Frank Strunk, who very carefully read themanuscript in the short time we gave him. Thanks are also due to Carl Har-ris, editor at Kluwer Academic Publishers for being understanding and goingbeyond his call of duty to help out with my requests.

Finally, I wish to thank my parents and my family for supporting methroughout my life and for being there when I needed them. They sufferedas I neglected many social responsibilities to complete this book.

Kalamazoo, September, 1992 Naveed A. Sherwani

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Acknowledgments for the Second Edition

The second edition project would not have been possible without the help ofSiddharth Bhingarde, Aman Sureka, Rameshwar Donakanti and Anand Pa-nyam. In particular, Siddharth worked with me for many many nights on thisproject. I am very grateful to these individuals for their help.

Several of my colleagues at Intel helped as reviewers of the chapters. Inthis regard, I would like to thank Marc Rose, John Hansen, Dave Ackley, MikeFarabee, and Niraj Bindal.

Several friends and family members helped by being copy editors. SabahatNaveed, Shazia Asif and Akram Sherwani helped by editing many revisions.Internet played a key role, as many of these revisions were done in Pakistanand then emailed to me.

I would like to thank Intel Corporation for helping me with this project. Inparticular, I would like to thank Atiq Bajwa for making the time available forme to complete the project.

Portland, March, 1995 Naveed A. Sherwani

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Acknowledgments for the Third Edition

The third edition would not have been possible without the help of FaranRafiq, Srinivasa Danda, Siddharth Bhingarde, Niraj Bindal, Prashant Saxena,Peichen Pan and Anand Panyam. I am very grateful to these individuals fortheir help. In particular, I am indebted to Faran Rafiq, who worked tirelesswith me and this project would not have been possible without his dedicationand hard work.

I would like to thank Intel Corporation for helping me with the third edition.In particular, I would like to thank Manpreet Khaira for the Research andDevelopment environment, which has helped mature many ideas.

I must thank my copy editor Tawni Schlieski, who very carefully read thenew chapters and turned them around in a very short time. I am very thankfulto Carl Harris, editor at Kluwer Academic Publishers for encouraging me towrite the third edition.

Finally, I am very thankful to my wife Sabahat and my daughter Aysel fortheir encouragement and support.

Portland, September, 1998 Naveed A. Sherwani