FPGA System Design using VHDL/Verilog (Altera)

Exposure to the complete design process of FPGA system with wide range of IP core and NIOSII

embedded Micro controller .You will learn how to make best use of the latest features of the Quartus® II

software, including all the productivity and efficiency benefits of using TimeQuest Timing Analysis,

Incremental Design and PowerPlay power analysis and optimization.

Altera NIOS II & SoPC covers both hardware and software aspects of the design flow and are accessible

to engineers. This co-training approach enables successful team working on SoPC designs. This ensures

successful convergence in the design flow and the development of efficient architectures.

The scope of the course includes an appreciation of the hardware platform, hardware-software

partitioning, hardware acceleration as well as software development and debugging. Approximately 50%

of class time is spent on practical exercises to reinforce the lectures. The exercises make use of a

development board to emphasize the real-world application of the techniques learned. FPGA System

Design using VHDL/Verilog (Altera) is developed and maintained by Enixs based on source material from

Altera.

What will you learn?

How to make best use of the full capability of the Quartus II software to implement your FPGA design.

How to specify timing constraints and perform static timing analysis using TimeQuest. Use Incremental Compilation techniques, including creating LogicLock™ regions (Floor planning)

and Partitions to reduce compile times and more easily achieve timing closure. Estimating and optimizing power consumption. Functional and timing simulation using ModelSim®. Debugging designs using SignalTap® II Designing the hardware platform Software-hardware partitioning and generation using SOPC Software development & debugging using Nios II IDE

Pre-requisites

All participants must be computer literate and must have a basic understanding of digital design and

Digital Design Techniques or have a good working knowledge of digital hardware design. Prior

experience in C or C++ is preferable.

CONTENTES OF TRAINING PROGRAM

General Intro about FPGA architecture and FPGA as a system component

Programmable logic evolution, FPGA vs. CPLD, FPGA essential building blocks, logic mapping to the FPGA, Different classes of pins of an FPGA and system connectivity considerations, Understanding packages and thermal data, FPGA - Memory, Processor, DSP/Multiplier, serial I/Os, Clock management components, FPGA suppliers and differentiation

Quartus Foundation flow

Design Entry (including VHDL /Verilog, Schematic, State Diagram design entry methods), Normal

Compilation, Functional simulation, Quick overview of ModelSim AE (Altera Edition)

Verilog HDL - Module 1 Verilog HDL Intro, Top down design model, Modules, Data types, Operators and Behavioral modeling.

Verilog HDL - Module 2 External Interface, Data flow modeling, Gate level modeling and Tasks and functions.

VHDL - Module 1 VHDL Intro, Entities and Architectures, Instantiation and Port Maps, Structural modeling,

Behavioral modeling

VHDL - Module 2 Dataflow modeling, Synthesis of combinational logic and Synthesis of Sequential Logic.

Quartus Assignment & Implementation Flow

Mega Wizard Plug in Manager, I/O pin Assignment analysis, pin planner, pin assignments, board

configuration settings, implementation in development board. Exercises: simple digital functions

such (gates, F/F, encoder and decoder, mux and demux, counters etc...)

Quartus Incremental Compilation & Optimization in Time & Power

Preparing a project for incremental flow, Creating design partitions, Combining with floor plan

constraints using LogicLock, The TimeQuest Static Timing Analyzer, Concepts, Interface, Using

TimeQuest from the GUI, Early timing estimation Optimization techniques Using PowerPlay

power optimization, Early estimation, Using the power optimization adviser

Quartus signal Tap II Embedded Logic Analyzer

Debugging tool – signal Tap II Embedded Logic Analyzer, Take advantage of free Embedded Logic

Analyzers to debug your design. The three modes, Configuration, Using the Logic Analysis

Interface, Capturing/displaying, Saving data Advanced Triggering, Signal Probe and the logic

analyzer interface, Purpose and use.

Quartus Design Viewer & planner

Chip Planner, RTL Viewer, Technology Map Viewer, Design Flow Automation

using TCL commands, Why and when to use DSP Builder Exercises, creating own design

partitions, allocating FPGA logic elements, timing and power analysis for revision

projects, signal taping for own codes.

Designing a System on a Programmable Chip (SoPC)

Why and when to use SoPC, available IPs, SoPC design flow, identifying standard and specific

components, User interface, principles, step-by-step system generation, using the wizard and

configuring the blocks, defining and customizing the NIOS II processor and tightly coupled

memories.

The NIOS II Processor and NIOS II - IDE Design Flow

Main concepts, the NIOSII IDE, User interface, principles, step-by-step flow of creating a

software project, Creating NiosII custom peripherals, basic tools for compilation and debugging,

using signal Tap II Embedded Logic Analyzer for debugging.

Case studies

Sdram Controller, USB Controller, I2C Controller and Music Player

Real Time Application Development – Mini Project

System On Programmable Chip development for a real time application using Quartus, NIOS II

and Altera IP core (a mini project, developed as a team).