am57x sitara™ processors technical deep dive · am57x sitara™ processors technical deep dive...

AM57x Sitara™ Processors Technical Deep Dive

ARM Cortex-A15 Solutions for automation,

HMI, vision, imaging, and other industrial

and high-performance applications

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Agenda • AM57x Silicon Overview

• AM57x Processors

• AM57x Peripherals

• AM57x System Architecture

• AM57x EVMs & Tools

AM57x Silicon Overview

AM57x Sitara Processors Technical Deep Dive

AM57x Product Family

PRU-ICSS can be used for industrial communication protocols such as Profibus, Profinet RT/IRT, EtherCAT, POWERLINK, Ethernet/IP, and more.**

ARM Cortex-A15

(MHz)

Software Com

patible C66x DSP

(MHz)

ARM Cortex-M4

(MHz)

Graphics

Video Accel-

eration Pi

n Co

mpa

tible

Display

Sub-system

PRU-ICSS

AM5728

1.5GHz 1.5GHz 750 MHz

750 MHz

213 MHz

213 MHz 3D 2D 3D 1080p Yes PRU-ICSS*

(Quad Core)

AM5726 213 MHz

213 MHz

1.5GHz 1.5GHz 750 MHz

750 MHz

PRU-ICSS* (Quad Core)

1.5GHz AM5718

3D 2D 1080p 750 MHz

213 MHz

213 MHz Yes PRU-ICSS*

(Quad Core)

AM5716

1.5GHz 750 MHz

213 MHz

213 MHz

PRU-ICSSU* (Quad Core)

*PRU-ICSS is configured into two dual-core subsystems. **Support for premium protocols such as EtherCAT or POWERLINK requires ordering a specific part.

AM5716

500 MHz

213 MHz

213 MHz

PRU-ICSS* (Quad Core)

500 MHz

213 MHz

AM572x Cortex®-A15-based Processors High-Speed Interconnect 28 nm

32b DDR3/3L

ARM M4

System Services

ARM Cortex-A15

32K/32K L1

ARM Cortex-A15 32K/32K L1 ARM M4

32KB L1 64KB RAM

C66x DSP

= +

32K/32K L1 288KB L2

- *

C66x DSP = +

32K/32K L1 288KB L2

- *

32b DDR3/3L w/ ECC

Video Acceleration IVA HD 1080p Video, VPE

SDMA 13 Mailbox RTC Secure WDT WDT Spinlock EDMA 16 Timer KBD

Display Subsystem

3 LCD HDMI 1.4a

1080p Blend/Scale/ Convert

Video Input Ports 2x16b 2x24b, 2x8b

Graphics Acceleration BB2D

GC320 3D GPU

2x SGX544

Not available in AM5726, except VPE

Security Acceleration 2 AES, 2 SHA2MD5,

DES3DES, RNG

PRU (Quad Core)

Industrial Communication Subsystem (ICSS)

EtherCAT®,PROFINET®, EtherNET/IP™,

PROFIBUS, POWERLINK, SERCOS 3

Storage IO Serial IO

10 UART

4 McSPI

QSPI

8 McASP

5 I2C

2 DCAN

Industrial and Programmable IO GbE 2-port

switch w/1588 G/MII, RMII, RGMII

2 PCIe

USB3/2 USB2

3 PWM/CAP/QEP

GPIO

SATA

NAND/NOR

3 SD/SDIO

1 eMMC/ SD/SDIO

2x24b, 2x8b

1MB L2 w/ECC 2MB L2

512KB L3 Shared RAM w/ECC

Pin muxing may limit peripheral availability. Bandwidth may limit simultaneous use of peripherals.

AM571x Cortex®-A15-based Processors High-Speed Interconnect 28 nm

ARM M4

System Services

ARM Cortex-A15 32K/32K L1 ARM M4

32KB L1 64KB RAM

C66x DSP = +

32K/32K L1 288KB L2

- *

32b DDR3/3L w/ ECC


SDMA 13 Mailbox RTC Secure WDT WDT Spinlock EDMA 16 Timer KBD

Display Subsystem 3 LCD HDMI 1.4a


Video Input Ports 2x24b, 2x8b


GC320 3D GPU SGX544

Not available in AM5716, except VPE

Security Acceleration 2 AES, 2 SHA2MD5,

DES3DES, RNG

PRU (Quad Core)

Industrial Communication Subsystem (ICSS)

EtherCAT®,PROFINET®, EtherNET/IP™,

PROFIBUS, POWERLINK, SERCOS 3

Storage IO Serial IO

10 UART

4 McSPI

QSPI

8 McASP

5 I2C

2 DCAN

Industrial and Programmable IO GbE 2-port

switch w/1588 G/MII, RMII, RGMII

2 PCIe

USB3/2 USB2

3 PWM/CAP/QEP

GPIO

SATA

NAND/NOR

3 SD/SDIO

1 eMMC/ SD/SDIO

1MB L2 w/ECC

1MB L2 w/ ECC

512KB L3 Shared RAM w/ECC 512KB L3 Shared RAM w/ ECC

Pin muxing may limit peripheral availability. Bandwidth may limit simultaneous use of peripherals.

Camera Port 2 x CSI2

ABC Package: 23 x 23mm, 0.8 pitch, 760-pin BGA package

AM57x Package

AM57x Processors


Processors and Memory: ARM Dual (AM572x) / Single (AM571x) ARM Cortex-A15 • Up to 1.5 GHz, r2p2 revision core(s), ARMv7-A instructions set • Out-of-order instruction dispatch and completion • Backward-compatible with code for previous ARM processors • Integrated NEON™ processing engine and VFPv4-compatible

hardware • Five execution units handle simple instructions, branch instructions,

NEON and floating point instructions, multiply instructions, & load and store instructions

• AM572x has 2MB L2 memory (no ECC), while AM571x has 1MB L2 with ECC

Cortex-A15 (AM57x) vs Cortex-A9 (AM437x) Enhancements • 128-bit (vs 64) data path • 3-inst (vs 2) instruction decode • 8-micro-ops (vs 4) issue • 64-byte (vs 32) cache line • Dual load/store (vs one or other) • Improved branch prediction:

– Higher capacity – Support for indirect branches

• More out-of-order instructions • Physically-indexed/tagged L1 cache • Tighter integration with NEON/VFP:

– Faster interworking with ARM code

– Dual-issue (vs single) • Improved memory performance:

– Tightly-coupled L2 cache to reduce latency 23 to 14 clocks

– Enhanced auto-prefetch – More requests buffering

New Features • Extended physical addressing • Virtualization support:

– Virtual interrupt controller – 2nd stage MMU for

Hypervisor control of guest OS memory

– CP15 trapping • Debug/trace support:

– Integrated trace – Virtualization support

• AMBA4 bus supports: – System coherency – MMU coherency

Key Benefits • Higher single-thread

performance: 3.5 vs 2.5 DMIPS/MHz

• 1.4x higher instructions per cycle (IPC) from enhancements

• 1.4x faster floating point • 10-15% higher clock in same

process due to design • 10-100x faster fully-pipelined

cache maintenance support • Improved system-level support

to support new architecture needs: Larger memory, virtualization, system coherency…

Cortex-A15 offers substantial enhancements and new features to dramatically increase performance and system-level support.

AM5728 diagram shown

Dual (AM572x) / Single (AM571x) ARM Cortex-A15 • Up to 1.5 GHz, r2p2 revision core(s), ARMv7-A instructions set • Out-of-order instruction dispatch and completion • Backward-compatible with code for previous ARM processors • Integrated NEON™ processing engine and VFPv4 compatible hardware • Five execution units handle simple instructions, branch instructions,

NEON and floating point instructions, multiply instructions, & load and store instructions

• AM572x has 2MB L2 memory (no ECC), while AM571x has 1MB L2 with ECC

Dual-ARM Cortex M4s • Up to 213 MHz, ARMv7-M and Thumb®-2 ISAs w/ ARMv6 SIMD & DSP

extensions

Dual (AM572x) / Single (AM571x) C66x DSPs • Up to 750MHz, fixed- and floating-point ISA • Object code compatible with C64x+ and C674x DSPs • Advanced VLIW architecture w/ two multiplier units and six arithmetic

logic units operating in parallel

L3 Memory with ECC • AM572x has 2.5MB of L3 memory with ECC • AM571x has 512 KB of L3 memory with ECC

Processors and Memory: M4, DSP, & L3

Processors and Memory: PRU-ICSS

* Use of these ports is only supported via TI Processor SDK RTOS.

Programmable Real-Time Unit – Industrial Communication Subsystem (PRU-ICSS) (2) • Dual 32-bit RISC cores

• 12KB program RAM, 8 KB data RAM per CPU

• 32KB shared RAM

• Interrupt controller

• Fast IO interface

• Peripherals: – One Ethernet MII_RT module with two MII ports * – One MDIO port * – One Industrial Ethernet peripheral *

and Industrial Ethernet timer – 1 x 16550-compatible UART – 1 x eCAP

• Capable of supporting master and/or slave modes of protocols such as:

– Profinet, Ethernet IP, Profibus, Ethercat, Powerlink, and Sercos 3

Programming Tools

•PRU C-compiler for PRU firmware •ARM Linux remoteproc + rpmsg driver •PRU debugger in CCS

PRU-ICSS Feature Comparison Features

AM18x/ OMAPL138 AM335x AM437x AM571x AM572x (SR1.1)

PRUSS PRU-ICSS1 PRU-ICSS1 PRU-ICSS0 2 x PRU-ICSS 2 x PRU-ICSS PRU core version 1 3 3 3 3 3 Number of PRU cores 2 2 2 2 2 2 Max frequency CPU freq / 2 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz IRAM size (per PRU core) 4 KB 8 KB 12 KB 4 KB 12 KB 12 KB DRAM size (per PRU core) 512 B 8 KB 8 KB 4 KB 8 KB 8 KB Shared DRAM size -- 12 KB 32 KB -- 32KB 32KB

General purpose input (per PRU core) Direct

Direct; or 16-bit parallel capture;

or 28-bit shift

Direct; or 16-bit parallel capture; or 28-bit shift; or 3ch EnDat 2.2; or 9ch

Sigma Delta


Sigma Delta


Sigma Delta

Direct; or 16-bit parallel capture; or

28-bit shift;

General purpose output (per PRU core) Direct Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out

GPI Pins (PRU0, PRU1) 30, 30 17, 17 13, 0 20, 20 21*, 21 21, 21 GPO Pins (PRU0, PRU1) 32, 32 16, 16 12, 0 20, 20 21*, 21 21, 21 MPY/MAC N Y Y Y Y Y Scratchpad N Y (3 banks) Y (3 banks) N Y (3 banks) Y (3 banks) CRC16/32 0 0 2 2 2 0 INTC 1 1 1 1 1 1 Peripherals n/a Y Y Y Y Y UART 0 1 1 1 1 1 eCAP 0 1 1 not pinned out 1 1 IEP 0 1 1 not pinned out 1 1 MII_RT 0 2 2 not pinned out 2 2 MDIO 0 1 1 not pinned out 1 1 Simultaneous protocols 1 1 2** 2

* PRU-ICSS2 only. PRU-ICSS1 does not pin out the PRU0 core GPIs/GPOs. ** 2nd protocol limited to EnDAT/Profibus/BISS/HIperphase DSL or serial based protocol

AM57x Peripherals


Video and Graphics

Video Acceleration (same for AM572x and AM571x) • IVA (image and video accelerator) HD-based video processing

solution. Sometimes this is called HDVICP. • Up to 1080p60 decode and 1080p30 encode support for MPEG4 and

H.264 • Single-channel encode support (1080p30, D1, and QVGA)

Graphics Acceleration • Dual (AM572x) / Single (AM571x) Imagination SGX544 3D graphics

engine – Up to 532 MHz – API support for OpenGL® ES1.1 & 2.0 – Tile-based architecture reduces access to external memory

• Vivante Corporation GC320 2D graphics accelerator – API support for OpenWF™, DirectFB, and GDI/DirectDraw™ – Also supports BitBlt, StretchBlt, blending, and transparency

AM5728 diagram shown. Not available in AM57x6, except VPE.



GC320 3D GPU

2x SGX544

Display Subsystem

Display Subsystem • Three LCD outs supporting MIPI DPI 2.0, BT-656, or BT-1120, each

with dedicated overlay manager • HDMI output supporting up to 1080p with a dedicated overlay

manager • One graphics, three video, and one write-back pipelines • Maximum display resolution up to 1920x1200

NOTE: Simultaneous use of multiple displays will reduce maximum resolution subject to DDR bandwidth and graphics layers.

Not available in AM57x6. AM5728 diagram shown.

Display Subsystem

3 LCD HDMI 1.4a


Video Input Ports 2x16b 2x24b, 2x8b 2x24b, 2x8b

Dual Camera Serial Interface 2 (CSI2)

Display Subsystem • Three LCD outs supporting MIPI DPI 2.0, BT-656, or BT-1120, each

with dedicated overlay manager • HDMI output supporting up to 1080p with a dedicated overlay

manager • One graphics, three video, and one write-back pipelines • Maximum display resolution up to 1920x1200

NOTE: Simultaneous use of multiple displays will reduce maximum resolution subject to DDR bandwidth and graphics layers


Dual-Camera Serial Interface 2 (CSI2) (AM571x) • Two ports compliant with MIPI CSI-2 1.0, MIPI D-PHY RX 1.0

– Port A: Four data lanes – Port B: Two data lanes

Display Subsystem 3 LCD HDMI 1.4a


Video Input Ports 2x24b, 2x8b

Camera Port 2 x CSI2

Video Input Ports (VIP) Each VIP supports 2-input independent stream parser slices • VIP1 and VIP2 slice can handle two streams

- Port-A: 8/16/24-bit options - Port-B: 8-bit only

• VIP3 slice can handle one stream - Port-A: 8/16-bit options

NOTE: AM571x only supports VIP1


Video Input Ports (VIP)

Display Subsystem

3 LCD HDMI 1.4a


Video Input Ports 2x16b 2x24b, 2x8b 2x24b, 2x8b

AM57x Serial Peripherals • DCAN (2)

– Support bit rates up to 1Mbit/s and are compliant to CAN2.0B protocol specification

• Multichannel Audio Serial Port Interface (McASP) (8) – Two instances support 16 channels w/ independent TX/RX clock sync domains – Six instances support 4 channels w/ shared TX/RX clock sync domains

• QSPI – Master-only interface primarily intended for fast booting from quad-SPI flash memories – Supports single, dual or quad reads. Only single writes are supported.

• I2C (5) – Slave or master configurable – Two I2C ports support Fast mode (up to 400 Kbps) – Three I2C ports support HS mode (up to 3.4 Mbps)

• Universal Asynchronous Receiver Transmitters (UART) (10) – Baud rates up to 3.6864 Mbps – One with extended modem control signals (DCD, RI, DTR, DSR) – One with IrDA

• Multichannel Serial Port Interface (McSPI) (4) – Function as master or slave – Each supports up to four external device (four chip selects) or one external master

Serial IO

10 UART

4 McSPI

QSPI

8 McASP

5 I2C

2 DCAN

• Three PWMSS (Pulse-Width Modulation Subsystems) – eHRPWM: High Resolution PWM

• 2x PWM outputs with single-/dual-edge symmetric/asymmetric operation Only ehrpwm[x]A supports the High-Resolution PWM feature

• 1x Trip Zone Input for reacting to external fault conditions • eHRPWM1 has Time Base Synchronization I/Os (internally daisy-chained to other

modules) – eCAP: Capture

• 1x Capture Input with 4-event time-stamp registers • Used for measuring audio sample rate, rotating machinery

speed, position sensor pulses • Can optionally be configured as a single channel PWM output

– eQEP: Quadrature Encoded Pulse • Used to measure the angular position or motion of a shaft

or axle (for example, volume knob) • 2x Quadrature Inputs, 1x Index Input, 1x Strobe Input

• GPIOs – AM572x up to 247 GPIOs; AM571x up to 215 GPIOs – Divided amongst 8x GPIO modules

(muxed on most LVCMOS device pins)

Industrial Programmable I/Os: PWMSS & GPIO

Industrial and Programmable IO

GbE 2-port switch

w/1588 G/MII, RMII, RGMII

2 PCIe

USB3/2 USB2

3 PWM/CAP/QEP

GPIO

Industrial Programmable I/Os: PCI Express (PCIe) PCI Express (PCIe) (2)

– Supports Gen I (2.5GT/s) and Gen II (5GT/s) modes

– AM57x has 2x PCIe lanes* supporting two configurations: 1) One Controller with 2 lanes 2) Two Controllers with 1 lane each

* On AM571x, use of Lane 1 is mutually exclusive with USB SuperSpeed mode – Supported features:

• Root Complex and Endpoint modes • Single Function in Endpoint mode • Optional traffic mapping through dedicated MMU2 • Single Virtual Channel (VC) and Traffic Class (TC)

– Unsupported features: • Power states L2 (w/Beacon) and D3cold • Built-in hot plug • Addressing modes other than incremental for bursts • Outbound transactions involving less than 4 bytes

– Supports the following maximum payload sizes • 128-byte outbound payload size (limited by EDMA) • 256-byte inbound payload size

Lane 0

Lane 1

Control Module

PCIE_SS1

PCIE_SS2

USB SS *

Industrial Programmable I/Os: USB USB (2) (USB 3.0/2.0 x1; USB 2.0 x1)

• Two xHCI USB Controllers with different configurations:

• On AM571x, use of USB SuperSpeed mode is mutually exclusive with lane of second PCIe.

• All xHCI Controllers support: – Host or Peripheral mode (Dual-Role-Device (DRD)) – DRVVBUS (Drive-VBUS) output signal to External Charge

Pump for VBUS 5V generation

• No support for the following: – Full OTG (Software-based Role Switching still possible)

• Attached Detection Protocol (ADP), ACA – ID pin (if desired, must be implemented by an

external GPIO)

Standard Line Rate PHY

USB Port 1 (USB1) USB 3.0 5Gbps Internal SS (USB3.0) PHY and Internal HS/FS (USB2.0) PHY

USB Port 2 (USB2) USB 2.0 480Mbps Internal HS/FS PHY

Industrial Programmable I/Os: Ethernet Ethernet

• Internal Gb Ethernet Switch with 3 ports: – 2 External Ethernet Ports – 1 Internal Local Host Port

• External Interface support: – RMII/MII (10/100Mbps) at 3.3V – RGMII (10/100/1000*Mbps) at 1.8V/3.3V – Single MDIO interface for PHY Control

• Clocking: – MII/RMII: Supports both internal and external

50MHz reference clock – RGMII: Internal clock reference only

• No support for: – GMII interface – 2.5V Signaling

* AM572x errata – Ethernet RGMII2 limited to 10/100 Mbps. Refer to device errata for impacted silicon revisions.

Storage I/Os: SATA SATA

• Single Port SATA host controller supporting 1.5-Gbps and 3-Gbps speeds (SATA-1 and SATA-2)

• Supports multiple drives with a port multiplier: command-based switching only (Issuing commands to only one drive at a time)

• Dedicated sata1_led pin for Activity LED generation

• No support for the following: – ATA legacy mode of operation – Cold presence detection for hot-plug operation – Message signaled interrupts – Far-end Analog Loopback – Port Multiplier FIS-based switching

Storage IO

SATA

NAND/NOR

3 SD/SDIO

1 eMMC/ SD/SDIO

Storage I/Os: eMCC/SD/SDIO eMMC / SD / SDIO (4)

• Four controllers with different configurations:

• Full compliance with standards: – JC64 MMC/eMMC standard specification, v4.5 – SD Physical Layer specification v3.01 – SD part E1 specification v3.00 (SDIO) – SD card specification Part A2 v3.00

• No support for: – MMC POW output pin: Must utilize chip level GPIO for this function, if desired.

Data Bus Primary Support Max Frequency* IO Buffer Type DMA

MMC1 4-bit SD 192 MHz (via DLL) UHS1 Master & Slave

MMC2 8-bit eMMC 192 MHz (via DLL) LVCMOS Master & Slave

MMC3 8-bit SDIO / SD 96 MHz LVCMOS Slave

MMC4 4-bit SDIO / SD 48 MHz LVCMOS Slave

* AM572x errata – MMC1/2/3 write speed limited. Refer to device errata for impacted silicon revisions.

Storage I/Os: GPMC & ELM • General Purpose Memory Controller (GPMC)

– Used for accessing SRAM, NOR, NAND, etc. – 8/16-bit data at up to 88MHz – Non-muxed, Address-Data muxed, and

Address-Address-Data muxed modes – Async mode with read page access – Sync mode with burst access and wrap

capability – 8 chip-selects covering 512MB of address

space

• Error Locator Module (ELM) – Used when interfacing GPMC to a NAND

device – Provides 4-, 8- or 16-bit error location over a

512-Byte block based on BCH algorithms – Allows detected errors and their locations in

the NAND block to be retrieved by the processor when the PAGE_VALID interrupt is generated

GPMC

Storage I/Os: EMIF & DMM • External Memory Interface (EMIF)

– 16-/32-bit DDR3/ DDR3L support – Speeds up to 533MHz (DDR-1066) – Hardware-leveling support – Class of Service and burst priority counter – MPU MA has 128-bit direct path with

optimized latency to each of EMIF0/1

• Dynamic Memory Management (DMM) – Performs global address translation and

address rotation (tiling) between L3_MAIN Interconnect and EMIFs

– Performs access interleaving between EMIFs

* if using stacked die package

Number EMIF Controllers

ECC Addressable SDRAM size Chip Selects

AM572x Dual EMIF1 only Up to 2GB per controller 1 per controller

AM571x Single Yes Up to 4 GB * 2

System Services SDMA 13 Mailbox RTC Secure WDT WDT Spinlock EDMA 16 Timer KBD

System Peripherals • Enhanced DMA (EDMA)

– Supports two simultaneous read and two simultaneous write physical channels – Up to 64 programmable logical channels

• Mailbox (13) – 13 for the MPU, DSP, IPU, and PRU; 1 for IVA – Number of users, number of messages in the queue

• Real-Time Clock (RTC): RTC-only low power mode not supported

• System DMA (SDMA): Up to 128 hardware requests, 32 prioritizable logical channels, and 256 × 64-bit FIFO dynamically allocable between active channels

• Watchdog Timer: Free-running 32-bit upward counter (runs off of 32kHz system clock)

• Spinlock: 256 hardware semaphores between the MPU, DSP, and IPU

• Timer (16): Free-running 32-bit upward counter. Runs off 32KHz or system clock

• Keyboard Controller (KBD): Supports up to 9x9 Keypads

AM57x System Architecture


Pad Configuration Requirements • In order to guarantee the IO Timings in the AM57x Data Manual over the

lifetime of the device, AM57x software shall implement the proper pad configuration requirements.

• Pad configuration settings that impact IO timings include: – Slew Control Settings – Virtual IO Timing Modes – Manual IO Timing Modes

• Proper pad configuration procedure includes: – IO Isolation: Required to guarantee IO state when changing IO settings – IO Delay Recalibration: Required to guarantee timings after AVS changes

• The AM57x Data Manual lists the pad configuration requirements to achieve the various timing modes of operation.

• The TRM Pad Configuration Section provides the details on implementing the pad configuration requirements.

(default values must be used)

Virtual IO Timing Modes • Virtual IO Timing Modes are pre-defined IO timing settings that are coded in the

Device ROM.

• Selection of Virtual Modes is done via the Pad Configuration Registers. This is described in AM57x TRM section Virtual IO Timing Modes.

• Below is an example of how Virtual IO Timing Modes are defined in the AM57x Data Manual:

Manual IO Timing Modes • Manual IO Timing Modes are IO timing settings that must be calculated and

programmed by system software based on seed values in the datasheet.

• Application of Manual IO Timing Modes is done via the CFG_x_IN, CFG_x_OEN, and CFG_x_OUT registers in the IODELAYCONFIG Module. This is described in the AM57x TRM section Manual IO Timing Modes.

• Below is an example of how Manual IO Timing Modes seed values are defined in the AM57x Data Manual:

IO Isolation Mode • Any changes to the Pad Configuration Registers or IODELAYCONFIG registers

can potentially result in an undesirable state (i.e., output state changes or output enable changes) on the associated IOs.

• To guarantee IO state, device pins should be placed in Isolation Mode when making any changes to the Pad Configuration Registers or IODELAYCONFIG Module Registers.

• Run-time (non-isolated) changes are only supported for MMC.

• See TRM section “Isolation Requirements” for details.

Customer Software Implications • All I/O timing modes and pinmuxing shall be set by software …

– At boot-time – While under protection of isolation – While executing code from OCMCRAM (since DDR cannot be accessed while IOs

are in isolation) – The Secondary Boot Loaders (just after ROM bootloader) execute from OCMC

RAM. The MLO in the Linux eco-system operates from the OCMC RAM. – Therefore the MLO/ SBL is the ideal place for pad configurations.

• Run-time changes are needed for MMC where dynamic configurations can not be avoided. TI has validated this use case.

• IO Delay support is included in the AM57xx Pin Mux Tool (PMT).

NOTE: In order to guarantee the IO timings in the AM57x Data Manual over the lifetime of the device, AM57x software shall implement the proper pad configuration requirements.

AM57x Boot • Booting devices include:

– NOR flash memory or other XIP device – NAND flash memories (non-XIP) – Removable SD card device – eMMC™ memory device – 1-bit SPI flash memories (QSPI_1) – 4-bit (Quad) SPI flash memories (QSPI_4)

• Initial boot order comes from sysboot pins.

– SATA-compatible devices • Solid state drives (SSDs) • Hard-disk drives (HDDs)

– USB: HS USB 2.0 interface – UART: UART interface

• Each core or DMA can only supports a static number of interrupt/event inputs.

• Each core interrupt controller and each DMA event handler is preceded by an Interrupt Controller or DMA Crossbar mux.

• Crossbar allows any peripheral interrupt/event to be mapped to a core or DMA .

• Mapping of peripheral interrupt/event selections is the same for each crossbar instance to allow software consistency.

Interrupt & Event Controller Crossbar

All peripherals Repeated for each IRQ of each CPU core (similar for events/DMA)

AM57x EVMs & Tools


*Supplied via third party: would not ship with kit **Available via download: target 4Q15 *** Available via download: target 1Q16

General Availability

Sold and Supported by

Processor

Memory

Display

Key Features

Software

AM572x Evaluation Module (EVM)

Oct ‘15

TI

AM5728

2GB DDR3L 4GB eMMC

micro SD Yes, Capacitive Touch

Size: 7”, 800 x 480 USB 3.0/2.0, e/mSATA, HDMI, 2x Gb Ethernet, Audio in/out, WiLink8 connector, Camera, PCIe & Peripheral Expansion

Linux, Android*, TI-RTOS**

AM57x Industrial Development Kit (IDK)

1Q16

TI

AM5728 AM571x –1Q16

1GB DDR3L 32MB QSPI / 16 GB eMMC

micro SD Yes, Capacitive Touch

Size: 10”, 1080p

Full ICSS access (x4), ADC, ECC DDR support, HDMI, Camera

TI-RTOS, RT Linux***

BeagleBoard-X15

Late 4Q15

BeagleBoard.org

AM5728

2GB DDR3L 4GB eMMC

micro SD

None

USB 3.0/2.0, eSATA, HDMI, 2x Gb Ethernet, Audio in/out,

& Peripheral Expansion

Linux, TI-RTOS**

COMING SOON

AM57x Development Tools

AM572x Evaluation Module (EVM)

• Processor board based on BeagleBoard-X15 – Sitara™ AM5728 processor – TPS659037 power management – 2GB DDR3L – 4GB eMMC – Micro SD card – 3x USB 3.0 HUB – USB 2.0 (micro) – Full size HDMI connector – eSATA connector – 2Gb Ethernet ports – Audio input/output – 20-pin ARM JTAG

• Included accessories – Quick Start Guide – HDMI cable – USB-to-Serial debug cable – Micro SD card with Processor SDK

Processor board Plugs in via expansion connectors in the back

Bottom side of LCD board miniPCIe connector mSATA connector WiLink™ 8 connector

User buttons Power LED

Camera board 3Mp sensor

7” LCD Display (WVGA - 800x480) Capacitive touch screen

*Power supply not included

AM572x Power Solutions TPS659037 is the Power Management IC (PMIC) that shall be used for the Device designs. TI requires use of this PMIC for the following reasons: • TI has validated its use with the device. • Board level margins – including transient response and output accuracy – are analyzed and

optimized for the entire system. • Support for power sequencing requirements (refer to Section 5.8 Power Supply Sequences in the

AM57x datasheet) • Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software

TPS659037 Power Supply

TPS659037 configured for the AM572x EVM

TPS659037 configured for the AM572x IDK

SMPS1/2 vdd_mpu vdd_mpu

SMPS3 DDR Memory DDR Memory

SMPS4/5 vdd_dspeve, vdd_gpu,

vdd_iva vdd_dspeve

SMPS6 vdd vdd_gpu

SMPS7 SW configuration after boot vdd

SMPS8 vdds18v vdd_iva

SMPS9 SW configuration after boot 3.3V vddshvx

AM571x Power Solutions

TPS65916 or TPS659037 is the Power Management IC (PMIC) that shall be used for the Device designs.


TPS659037 configured for the AM571x IDK

SMPS1/2 vdd_mpu

SMPS3 DDR Memory

SMPS4/5 vdd_dsp

SMPS6 vdd_gpu

SMPS7 vdd

SMPS8 vdd_iva

SMPS9 3.3V


Generic TPS65916 configuration for AM571x

SMPS1 vdd_mpu

SMPS2 vdd

SMPS3 vdd_dsp, vdd_gpu, vdd_iva

SMPS4 vdds18v

SMPS5 DDR Memory

Thermal Considerations • Thermal management ensures that every silicon device on the board works within its allowable

operating junction temperature. Failure to maintain a junction temperature within the range specified reduces operating lifetime, reliability, and performance.

• The product design cycle should include thermal analysis to verify the operating junction temperature of the device is within functional limits. If the temperature is too high, component- or system-level thermal enhancements are required to dissipate the heat from the system.

AM572/1x Layout Compatibility • AM572x & AM571x are designed as layout compatible solutions.

• AM572/1x Compatibility Guide application note walks through differences: – Feature differences – Hardware considerations – Pin compatibility – Software impact – PMIC compatibility

• Example differences: – Same multiplexings for all common features – Features/signals removed or added in AM571x – New added pin muxings in AM571x – IVA/DSP must run at same OPP when AM571x populated

(unless special population hooks) – Some special powers swap, must treat them the same

(same filtering/handling)

For More Information

• For information about AM57x: www.ti.com/product/am5728 www.ti.com/product/am5718

• For more training related to Sitara and AM57x: www.ti.com/sitaratraining

• For questions about this training, refer to the E2E Sitara Processors Forum: https://e2e.ti.com/support/arm/sitara_arm

http://www.ti.com/product/am5728

http://www.ti.com/product/am5718

http://www.ti.com/sitaratraining

https://e2e.ti.com/support/arm/sitara_arm

am57x sitara™ processors technical deep dive · am57x sitara™ processors technical deep dive...

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