amber user guide

8/13/2019 Amber User Guide

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Amber Open Source Project

Amber Project User Guide

May 2013


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Amber Amber Project User Guide May 2013

Table of Contents

1 Amber Project ............................................................................................................................................................ 31.1 Project Directory Structure ........................................................................................................... 31.2 Amber FPGA System .......................................................................................................................... 4

2 Verilog simulations .......................................................................................................................................... 62.1 Instain! t"e Amber #roject ......................................................................................................... $2.2 Instain! t"e %om#ier ........................................................................................................................ $2.3 &unnin! Simuations ............................................................................................................................. '2.4 Simuation out#ut (ies ...................................................................................................................... .. 102.) *ard+are ,ests ......................................................................................................................................... .. 122.$ % Pro!rams ...................................................................................................................................................... 142.' -inu .......................................................................................................................................................................... 1$

3 FPGA Snt!esis ..................................................................................................................................................... 1"

# $sing %oot&'oa(er ........................................................................................................................................... 2)4.1 Insta and con(i!ure Minicom ................................................................................................... 204.2 %on(i!ure t"e FPGA .............................................................................................................................. 21

* 'icense .................................................................................................................................................................................... 22

Released under the GNU Lesser General Public License (v2.1) terms 2 of 22


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1 Amber Project

The Amber project is a complete processor system implemented on the Xilinx

Spartan-6 SP605 FPGA development board The project is hosted on opencoresor!

The project provides a complete hard"are and so#t"are development system abo$nt

the Amber processor core A n$mber o# applications% "ith & so$rce code% are

provided as examples o# "hat the systme can be $sed #or

The recommended system #or the project is the Xilinx SP605 development board% a

P& r$nnin! &ent'S 6x% the Xilinx (S) *+5 tool chain ,#ree ebpac. version/% and

the &ode Sorcery G1 toolchain #or A23 processors All o# these elements are #ree

except #or the act$al development board "hich costs aro$nd 4500

1+1 Project ,irector Structure

The #ollo"in! table describes the directories and s$b-directories located $nder

4A3)2AS)

Table 1 Project directory structure

,irector ,escription

doc %ontains a #roject documentation.

"+ %ontains a /erio! source (ies simuations and synt"esis scri#ts and "ard+are testsource (ies.

"+(#!a Fies reatin! to FPGA synt"esis.

"+(#!abin %ontains t"e FPGA synt"esis mae(ie and su##ortin! scri#ts.

"+(#!abit(ies ,"is directory is created durin! t"e FPGA synt"sis #rocess. It is used to store t"e (inabit(ie !enerated at t"e end o( t"e FPGA synt"eis #rocess.

"+(#!ao! ,"is directory is created durin! t"e FPGA synt"sis #rocess. It is used to store o! (ies(or eac" ste# o( t"e FPGA synt"esis #rocess.

"+(#!a+or ,"is directory is created durin! t"e FPGA synt"sis #rocess. It is used to storetem#orary (ies created durin! t"e FPGA synt"sis #rocess. ,"ese (ies !et erased +"ena ne+ synt"ess run is started.

"+isim "ere tests are run (rom. ,"e iin iSim /erio! simuator +or directory +a5e dum#and any ot"er simuation out#ut (ies !o in "ere.

"+tests *ods a set o( "ard+are tests +ritten in assemby. ,"ese tests (ocus on 5eri(yin! t"ecorrect o#eration o( t"e instruction set. I( any modi(ications are made to t"e Amber coreit is im#ortant t"at t"ese tests sti #ass.

"+toos *ods scri#ts used to run /erio! simuations.

"+5o! /erio! source (ies.

"+5o!amber23 Amber 23 core /eri o! source (ies.

"+5o!amber2) Amber 2) core /eri o! source (ies.

"+5o!et"mac ,"e 6t"ernet MA% /erio! source (ies. ,"ese (ies come (rom t"e 7#encores 6t"mac#roject and are re#roduced "ere (or con5enience.

"+5o! ib *ard+are ibary /erio! (i es incudin! memory modes. ,"e Amber #roject #ro5ides asim#e !eneric ibrary t"at is normay used (or simuations. It aso #ro5ides some

+ra##ers (or iin ibrary eements.

"+5o!system FPGA system /erio! source (ies.

"+5o!tb ,estbenc" /erio! (ies.

"+5o!s$8ddr3 iin S#artan9$ DD&3 controer /erio! (ies !o in "ere. ,"ese are not #ro5ided +it"t"e #roject (or co#yri!"t reasons. ,"ey are needed to im#ement t"e Amber system ona S#artan9$ de5eo#ment board and must be !enerated in iin %ore!en.

"+5o!5$8ddr3 iin /irte9$ DD&3 controer /erio! (ies !o in "ere. ,"ese are not #ro5ided +it" t"e



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,irector ,escription

#roject (or co#yri!"t reasons. ,"ey are needed to im#ement t"e Amber system on a/irte9$ de5eo#ment board and must be !enerated in iin %ore!en.

s+ %ontains % source (ies (or a##ications t"at run on t"e Amber system as +e as someutiities t"at aid in debu!!in! t"e system.

s+boot9oader9seria % assemby sources and a mae(ie (or t"e seria9#ort boot9oader a##ication.

s+boot9oader9et"mac % assemby sources and a mae(ie (or t"e et"ernet9#ort boot9oader a##ication. ,"isa##ication su##orts tenet (or contro and status and t(t# (or u#oadin! e( eecutabe(ies.

s+"eo9+ord % assemby source and a mae(ie (or a sim#e stand9aone a##ication eam#e.

s+incude %ommon % assemby and mae(ie incude (ies.

s+mini9ibc % assemby sources and a mae(ie to buid t"e object t"at com#rise a 5ery sma andimited stand9aone re#acement (or t"e ibc ibrary.

s+toos S"e scri#ts and % source (ies (or com#ie and debu! utiities.

s+5minu %ontains t"e .mem and .dis (ies (or t"e 5minu simuation.

1+2 Amber FPGA Sstem

The FPGA system incl$ded "ith the Amber project is a complete embedded

processor system "hich incl$ded all peripherals needed to r$n 7in$x% incl$din!

1A2T% timers and an )thernet ,3((/ port The #ollo"in! dia!ram sho"s the entire

system



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Figure 1 -mber !PG "#stem

All the 8erilo! so$rce code "as speci#ially developed #or this project "ith the

exception o# the #ollo"in! mod$les9

ddr3.v The Xilinx Spartan-6 ::2; controller "as !enerated by the Xilinx

&ore!en tool The #iles are not incl$ded "ith the project #or copyri!ht

reasons (t is $p to the $ser to optain the (S) so#t"are #rom Xilinx and

!enerate the correct memory controller ote that ishbone brid!e mod$les

are incl$ded that s$pport both the Xilinx Spartan-6 ::2; controller and the

8irtex-6 controller

eth_top.v This mod$le is #rom the 'pencores )thernet 3A& *0


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2 Verilog simulations

2+1 -nstalling t!e Amber project

(# yo$ have not already done so% yo$ need to do"nload the Amber project #rom'pencoresor! The Amber project incl$des all the 8erilo! so$rce #iles% tests "ritten

in assembly% a boot loader application "ritten in & and scripts to compile% sim$late

and synthesi=e the code >o$ can either do"nload a tar!= #ile #rom the 'pencores

"ebsite or better still% connect to the 'pencores S$bversion server to do"nload the

project This can be done on a 7in$x P& as #ollo"s9

$ mkdir //$ cd //$ svn --username --password \ co http://opencores.org/ocsvn/amber/amber/trunk

2+2 -nstalling t!e Compiler

Tests need to be compiled be#ore yo$ can r$n sim$lations >o$ need to install a G1

cross-compiler to do this The easiest "ay to install the G1 tool chain is to

do"nload a ready made pac.a!e &ode So$rcery provides a #ree one To do"nload

the &ode So$rcery pac.a!e% !o to this pa!e

"tt#>+++.codesourcery.coms!##itearm

>o$ need to re!ister and "ill be sent an email to access the do"nload area Select the

GNU/Linuxversion and then theIA32 GNU/Linux(nstaller 'nce the pac.a!e is

installed% add the #ollo"in! to yo$r bashrc #ile% "here the PAT? is set to "here yo$

install the &ode So$rcery G1 pac.a!e

# hange /pro!/amber to where you saved the amber package on your systeme"port %&'(%)&*//trunk

# hange /opt/)ourcery to where the package is installed on your system+,*//bin:$+,

# %&'('0)),001 is the name added to the start o2 each 345 tool in# the ode )ourcery bin directory. ,his variable is used in various make2iles to set# the correct tool to compile code 2or the mber coree"port %&'('0)),001*arm-none-linu"-gnueabi

# 6ilin" 7)& installation directory

# ,his should be con2igured 2or you when you install 7)&.# %ut check that is has the correct value# 7t is used in the run script to locate the 6ilin" library elements.e"port 671746*/opt/6ilin"/89./7)&

2+2+1 G.$ Tools $sage

(t@s important to remember to $se the correct s"itches "ith the G1 tools to restrict

the (SA to the set o# instr$ctions s$pported by the Amber core The s"itches are

already set in the ma.e#iles incl$ded "ith the Amber core ?ere are the s"itches to

$se "ith !cc ,arm-none-lin$x-!n$eabi-!cc/9

-march*armv;a -mno-thumb-interwork

Released under the GNU Lesser General Public License (v2.1) terms of 22
http://www.codesourcery.com/sgpp/lite/armhttp://www.codesourcery.com/sgpp/lite/arm


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These s"itches speci#y the correct version o# the (SA% and tell the compiler not to

create bx instr$ctions ?ere is the s"itch to $se "ith the G1 lin.er% arm-none-

lin$x-!n$eabi-ld9

--2i"-v9b"

This s"itch converts any bx instr$ctions ,"hich are not s$pported/ to @mov pc% lr@

?ere is an example $sa!e #rom the boot-loader ma.e process9

arm-none-linu"-gnueabi-gcc -c -0s -march*armv;a -mno-thumb-interwork -22reestanding-7../include -c -o boot-loader.o boot-loader.c

arm-none-linu"-gnueabi-gcc -7../include -c -o start.o start.)arm-none-linu"-gnueabi-gcc -c -0s -march*armv;a -mno-thumb-interwork -22reestanding

-7../include -c -o crc8.o crc8.carm-none-linu"-gnueabi-gcc -c -0s -march*armv;a -mno-thumb-interwork -22reestanding

-7../include -c -o "modem.o "modem.carm-none-linu"-gnueabi-gcc -c -0s -march*armv;a -mno-thumb-interwork -22reestanding

-7../include -c -o el2splitter.o el2splitter.carm-none-linu"-gnueabi-ld -%static -ap boot-loader.map --strip-debug --2i"-v9b" -o boot-

loader.el2 -, sections.lds boot-loader.o start.o crc8.o "modem.o el2splitter.o../mini-libc/print2.o ../mini-libc/libc(asm.o ../mini-libc/memcpy.o

arm-none-linu"-gnueabi-ob!copy -' .comment -' .note boot-loader.el2../tools/amber-el2splitter boot-loader.el2 > boot-loader.mem../tools/amber-memparams.sh boot-loader.mem boot-loader(memparams.varm-none-linu"-gnueabi-ob!dump - -) -&1 boot-loader.el2 > boot-loader.dis

A #$ll list o# compile s"itches #or !cc can be #o$nd here9

"tt#>!cc.!nu.or!oninedocs!cc94.).2!ccA&M97#tions."tm?A&M97#tions

And #or ld here9

"tt#>source+are.or!binutisdocs92.21dA&M."tm?A&M

2+3 /unning Simulations>o$ sho$ld be able to $se any 8erilo!-00* compatible sim$lator to r$n sim$lations

The project comes "ith r$n scripts and project #iles #or the #ree Xilinx ebpac. (Sim

*+5 sim$lator

)xample $sa!eB

$ cd $%&'(%)&/hw/isim$ ./run.sh hello-world

,est hello-world= type 9make -s - ../mini-libc 74()7&*8

arm-none-linu"-gnueabi-gcc -c -0s -march*armv;a -mno-thumb-interwork -22reestanding-7../include -c -o boot-loader-serial.o boot-loader-serial.carm-none-linu"-gnueabi-ld -%static -ap boot-loader-serial.map --strip-debug --2i"-v9b" -o boot-loader-serial.el2 -, sections.lds boot-loader-serial.o start.o crc8.o"modem.o el2splitter.o ../mini-libc/print2.o ../mini-libc/libc(asm.o ../mini-libc/memcpy.oarm-none-linu"-gnueabi-ob!copy -' .comment -' .note boot-loader-serial.el2../tools/amber-el2splitter boot-loader-serial.el2 > boot-loader-serial.mem../tools/amber-memparams?;.sh boot-loader-serial.mem boot-loader-serial(memparams?;.v../tools/amber-memparams8;@.sh boot-loader-serial.mem boot-loader-serial(memparams8;@.varm-none-linu"-gnueabi-ob!dump - -) -&1 boot-loader-serial.el2 > boot-loader-serial.dis../tools/check(mem(siAe.sh boot-loader-serial.mem BCDDDD;DBmake -s - ../mini-libc 74()7&*8'unning: /tools/6ilin"/89./7)&(E)/7)&/bin/lin/unwrapped/2use tb -o amber-test.e"e-pr! amber-isim.pr! -d %00,(&(F71&*B../../sw/boot-loader-serial/boot-loader-serial.memB -d %00,(&(+')(F71&*B../../sw/boot-loader-serial/boot-loader-serial(memparams?;.vB -d 74(&(F71&*B../../sw/hello-world/hello-world.memB -d

%&'(103(F71&*Btests.logB -d %&'(,&),(4&*Bhello-worldB -d %&'()7(,'1*9 -d%&'(,7&05,*D -d %&'(10E(74(& -incremental -i ../vlog/lib -i ../vlog/system

http://gcc.gnu.org/onlinedocs/gcc-4.5.2/gcc/ARM-Options.html#ARM-Optionshttp://sourceware.org/binutils/docs-2.21/ld/ARM.html#ARMhttp://gcc.gnu.org/onlinedocs/gcc-4.5.2/gcc/ARM-Options.html#ARM-Optionshttp://sourceware.org/binutils/docs-2.21/ld/ARM.html#ARM


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-i ../vlog/amber;? -i ../vlog/amber; -i ../vlog/tb7)im +.@2 Gsignature D"2bcDDdaaH4umber o2 +5s detected in this system: 9,urning on mult-threading= number o2 parallel sub-compilation !obs: @Eetermining compilation order o2 E1 2ilesnalyAing Ierilog 2ile B../vlog/system/boot(mem?;.vB into library worknalyAing Ierilog 2ile B../vlog/system/boot(mem8;@.vB into library worknalyAing Ierilog 2ile B../vlog/system/clocks(resets.vB into library work

nalyAing Ierilog 2ile B../vlog/system/interrupt(controller.vB into library worknalyAing Ierilog 2ile B../vlog/system/system.vB into library worknalyAing Ierilog 2ile B../vlog/system/test(module.vB into library worknalyAing Ierilog 2ile B../vlog/system/timer(module.vB into library worknalyAing Ierilog 2ile B../vlog/system/uart.vB into library worknalyAing Ierilog 2ile B../vlog/system/wb("s(ddr?(bridge.vB into library worknalyAing Ierilog 2ile B../vlog/system/wishbone(arbiter.vB into library worknalyAing Ierilog 2ile B../vlog/system/a2i2o.vB into library worknalyAing Ierilog 2ile B../vlog/system/ddr?(a2i2o.vB into library worknalyAing Ierilog 2ile B../vlog/system/ethmac(wb.vB into library worknalyAing Ierilog 2ile B../vlog/system/main(mem.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(clockgen.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(crc.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(2i2o.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(maccontrol.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(macstatus.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(miim.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(outputcontrol.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(random.vB into library work

nalyAing Ierilog 2ile B../vlog/ethmac/eth(receivecontrol.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(registers.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(register.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(r"addrcheck.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(r"counters.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(r"ethmac.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(r"statem.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(shi2treg.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(spram(;"?;.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(top.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(transmitcontrol.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(t"counters.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(t"ethmac.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(t"statem.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/eth(wishbone.vB into library worknalyAing Ierilog 2ile B../vlog/ethmac/"ilin"(dist(ram(8"?;.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(alu.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(barrel(shi2t.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(cache.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(coprocessor.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(core.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(decode.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(decompile.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(e"ecute.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(2etch.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(multiply.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(register(bank.vB into library worknalyAing Ierilog 2ile B../vlog/amber;?/a;?(wishbone.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(alu.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(barrel(shi2t.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(shi2ter.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(coprocessor.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(core.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(dcache.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(decode.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(decompile.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(e"ecute.vB into library work

nalyAing Ierilog 2ile B../vlog/amber;/a;(2etch.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(icache.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(mem.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(multiply.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(register(bank.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(wishbone.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(wishbone(bu2.vB into library worknalyAing Ierilog 2ile B../vlog/amber;/a;(write(back.vB into library worknalyAing Ierilog 2ile B../vlog/lib/generic(iobu2.vB into library worknalyAing Ierilog 2ile B../vlog/lib/generic(sram(byte(en.vB into library worknalyAing Ierilog 2ile B../vlog/lib/generic(sram(line(en.vB into library worknalyAing Ierilog 2ile B../vlog/tb/tb(uart.vB into library worknalyAing Ierilog 2ile B../vlog/tb/eth(test.vB into library worknalyAing Ierilog 2ile B../vlog/tb/dumpvcd.vB into library worknalyAing Ierilog 2ile B../vlog/tb/tb.vB into library work)tarting static elaborationompleted static elaborationFuse emory 5sage: 98J; K%Fuse +5 5sage: 8;;D ms

ompiling module clocks(resetsompiling module generic(sram(line(enGE,(L7E,*...



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ompiling module generic(sram(byte(enGE,(L7E,*...ompiling module a;?(cache(de2aultompiling module a;?(wishboneompiling module a;?(2etchompiling module a;?(decompile(;ompiling module a;?(decodeompiling module a;?(barrel(shi2tompiling module a;?(alu

ompiling module a;?(multiplyompiling module a;?(register(bankompiling module a;?(e"ecuteompiling module a;?(coprocessorompiling module a;?(coreompiling module eth(clockgenompiling module eth(shi2tregompiling module eth(outputcontrolompiling module eth(miimompiling module eth(registerG'&)&,(I15&*@MbDHompiling module eth(registerG'&)&,(I15&*@Mb8D8D...ompiling module eth(registerGL7E,*8='&)&,(I15&...ompiling module eth(registerGL7E,*N='&)&,(I15&...ompiling module eth(registerGL7E,*N='&)&,(I15&...ompiling module eth(registerGL7E,*N='&)&,(I15&...ompiling module eth(registerG'&)&,(I15&*@MbD88D...ompiling module eth(registerG'&)&,(I15&*@MbD8DD...ompiling module eth(registerGL7E,*='&)&,(I15&...ompiling module eth(registerGL7E,*9='&)&,(I15&...

ompiling module eth(registerGL7E,*?='&)&,(I15&...ompiling module eth(registerG'&)&,(I15&*@MbD88D...ompiling module eth(registerGL7E,*8Hompiling module eth(registerGL7E,*='&)&,(I15&...ompiling module eth(registerGL7E,*8='&)&,(I15...ompiling module eth(registersompiling module eth(receivecontrolompiling module eth(transmitcontrolompiling module eth(maccontrolompiling module eth(t"countersompiling module eth(t"statemompiling module eth(crcompiling module eth(randomompiling module eth(t"ethmacompiling module eth(r"statemompiling module eth(r"countersompiling module eth(r"addrcheckompiling module eth(r"ethmacompiling module generic(sram(byte(enGE,(L7E,*...ompiling module eth(spram(;"?;ompiling module eth(2i2oGE&+,*8=4,(L7E,*Hompiling module eth(wishboneompiling module eth(macstatusompiling module eth(topompiling module generic(iobu2ompiling module generic(sram(byte(enGE,(L7E,*...ompiling module boot(mem?;ompiling module uartGL%(EL7E,*?;=L%()L7E,*9Hompiling module test(moduleGL%(EL7E,*?;=L%()L7E...ompiling module timer(moduleGL%(EL7E,*?;=L%()L7...ompiling module interrupt(controllerGL%(EL7E,*?...ompiling module main(memGL%(EL7E,*?;=L%()L7E,*...ompiling module wishbone(arbiterGL%(EL7E,*?;=L%...ompiling module ethmac(wbGL%(EL7E,*?;=L%()L7E,...ompiling module systemompiling module eth(testompiling module tb(uart(de2ault

ompiling module dumpvcdompiling module tb,ime 'esolution 2or simulation

is 8ps.Laiting 2or 8 sub-compilationGsH to 2inish...ompiled @ Ierilog 5nits%uilt simulation e"ecutable amber-test.e"eFuse emory 5sage: @J@D K%Fuse +5 5sage: ;8;D ms3 +5 5sage: 8;DD ms7)im +.@2 Gsignature D"2bcDDdaaHL'4743: L&%+K license was 2ound.L'4743: +lease use 6ilin" 1icense on2iguration anager to check out a 2ull 7)imlicense.L'4743: 7)im will run in 1ite mode. +lease re2er to the 7)im documentation 2or morein2ormation on the di22erences between the 1ite and the Full version.,his is a 1ite version o2 7)im.,ime resolution is 8 ps)imulator is doing circuit initialiAation process.

1oad boot memory 2rom ../../sw/boot-loader-serial/boot-loader-serial.mem'ead in ;D? lines



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log 2ile tests.log= timeout D= test name hello-world1oad main memory 2rom ../../sw/hello-world/hello-world.mem'ead in J88 linesFinished circuit initialiAation process.mber %oot 1oader v;D8?D9;@89?8;D! D"DDDD@DDDello= LorldO

----------------------------------------------------------------------------mber ore > 5ser F7'P 7'P )IrD D"DDDDDD8Dr8 D"DDDD@d2cr; D"DDDDDDDDr? D"DDDDDDDDr9 D"DcDD@DD?r D"deadbee2r D"deadbee2rN D"deadbee2r@ D"deadbee2 D"deadbee2rJ D"deadbee2 D"deadbee2r8D D"DDDDDD88 D"deadbee2r88 D"2DDDDDDD D"deadbee2r8; D"DDDD8ecc D"deadbee2r8? D"D@DDDDDD D"deadbee2 D"deadbee2 D"D82222bDr89 GlrH D"DDDD@D;D D"deadbee2 D"deadbee2 D"DDDD?2b

r8 GpcH D"DDDD@9JD

)tatus %its: 4*D= *8= *8= I*D= 7'P ask D= F7'P ask D= ode * 5ser----------------------------------------------------------------------------

QQQQQQQQQQQQQQQQQQQQ+assed hello-world 9N?9 ticksQQQQQQQQQQQQQQQQQQQQ)topped at time : 88J8?;NDD ps : File B/pro!/amber(trunk(working/hw/vlog/tb/tb.vB1ine D?

2+# Simulation output files

2+#+1 ,isassembl Output File

The disassembly #ile% amberdis% is !enerated by de#a$lt d$rin! a sim$lation (t is

located in the 4A3)2AS)


11/22


;@; 8@: mov r9= #D ;@ 8c: mov r= #D ;@@ ;D: add r= r= r9 ;J8 ;9: cmp r= #D ;J9 ;@: -movne r8D= #;D ;JN ;c: -bne b9 ?DD ?D: mov rN= #D ?D? ?9: mvn r@= #D

?D ?@: add rJ= rN= r@ ?DJ ?c: cmn rJ= #8 ?8; 9D: -movne r8D= #?D ?8 99: -bne b9 ?8@ 9@: mvn r8= #D ?;8 9c: mov r;= #D ?;9 D: add r?= r8= r; ?;N 9: cmn r?= #8 ??D @: -movne r8D= #9D ??? c: -bne b9 ?? D: mvn r9= #D ??J 9: mvn r= #D ?9; @: add r= r9= r ?9 c: cmn r= #; ?9@ ND: -movne r8D= #D ?8 N9: -bne b9 ?9 N@: mvn rN= #D ?N Nc: mvn r@= #;9 ?D @D: add rJ= rN= r@

?? @9: cmn rJ= #; ? @@: -movne r8D= #D ?J @c: -bne b9 ?N; JD: ldr r8= Rpc= #DS ?NN read addr d9= data N2222222 ?@8 J9: mov r;= #8 ?@9 J@: adds r?= r8= r; ?@N Jc: -bvc b9 ?JD aD: ldr rD= Rpc= #9@S ?J read addr d@= data @DDDDDDD ?JJ a9: cmp rD= r? 9D; a@: -movne r8D= #ND 9D ac: -bne b9 9D@ bD: b cD 98D !ump 2rom bD to cD= rD @DDDDDDD= r8 N2222222 98N cD: ldr r88= Rpc= #@S 9;; read addr dD= data 2DDDDDDD 9; c9: mov r8D= #8N 9;J c@: str r8D= Rr88S 9?; write addr 2DDDDDDD= data DDDDDD88= be 2

2+#+2

Figure 2 - G067ave aveform vieer

2+#+3 Program Trace $tilit

A $tility is provided that traces all #$nction calls made d$rin! a 8erilo! sim$lation

?ere is an example $sa!e9

$ cd $%&'(%)&/hw/sim$ run ethmac-test$ ln -s ../../sw/tools/amber-!umps.sh !umps$ !umps ethmac-test

This prod$ces the #ollo"in! o$tp$t The le#t col$mn !ives the time o# the event The

next col$m !ives the name o# the callin! #$nction The next col$mn !ives the val$e

o# the r0 re!ister This re!ister holds the #irst parameter passed in #$nction calls The

next col$mn !ives the name o# the #$nction called

;ND?8 u main -> G DDDD@dec= H print2 u;N8D9 u print2 -> G DN2222@c= H print u;N?88 u print -> G DDDDDD?= H (outbyte u



12/22


;N988 print


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.ame ,escription

cac"e3 ,ests t"at t"e cac"e can +rite to and read bac muti#e t imes (rom 2 +ords in se:uence inmemory 9 t"e sie o( t"e cac"e.

cac"eabe8area ,ests t"e cac"eabe area co9#rocessor (unction.

cac"e8(us" ,ests t"e cac"e (us" (unction. Does a (us" in t"e midde o( a se:uence o( data reads. %"ecs t"ata t"e data reads are correct.

cac"e8s+a#8bu! ,ests t"e interaction bet+een a s+a# instruction and t"e cac"e. &uns t"rou!" a main oo#muti#e times +it" di((erent numbers o( no# instructions be(ore t"e s+# instruction to test a ran!eo( timin! interactions bet+een t"e cac"e state mac"ine and t"e s+a# instruction.

cac"e8s+a# Fis u# t"e cac"e and t"en does a s+a# access to data in t"e cac"e. ,"at data s"oud bein5aidated. %"ec by readin! it a!ain.

c"an!e8mode ,ests te: tst cm# and cmn +it" t"e # (a! set. Starts in su#er5isor mode c"an!es to Interru#tmode t"en Fast Interru#t mode t"en su#er5isor mode a!ain and (inay User mode.

c"an!e8sbits %"an!e status bits. ,ests mo5s +"ere t"e destination re!ister is r1) t"e #c. De#endin! on t"e#rocessor mode and +"et"er t"e s bit is set or not some or none o( t"e status bits +i c"an!e.

ddr31 ord accesses to random addresses in DD&3 memory. ,"e test creates a ist o( addresses in anarea o( boot8mem. It t"en +rites to a addresses +it" data 5aue e:ua to address. Finay it readsbac a ocations c"ecin! t"at t"e read 5aue is correct.

ddr32 ,ests byte read and +rite accesses to DD&3 memory.

ddr33 ,est bac to bac +rite9read accesses to DD&3 memory.

et"mac8mem ,ests +is"bone access to t"e interna memory in t"e 6t"ernet MA% modue.

et"mac8re! ,ests +is"bone access to re!isters in t"e 6t"ernet MA% modue.

et"mac8t ,ests et"ernet MA% (rame transmit and recei5e (unctions and 6t"mac DMA access to "iboot mem.6t"mac is #ut in oo#bac mode and a #acet is transmitted and recei5ed.

(ir: 6ecutes 20 FI&Es at random times +"ie eecutin! a sma oo# o( code. ,"e interru#ts aretri!!ered usin! a ransom timer. ,est c"ecs t"e (u set o( FI&E re!isters Br< to r14C and +i ony#ass i( a interru#ts are "anded correcty.

(o+8bu! ,"e core +as ie!ay si##in! an instruction a(ter a se:uence o( 3 conditiona not9eecuteinstructions and 1 conditiona eecute instruction.

(o+1 ,ests instruction and data (o+. S#eci(icay tests t"at a stm +rit in! to cac"ed memory aso +rites

a data t"rou!" to main memory.

(o+2 ,ests t"at a stream o( str instrutions +ritin! to cac"ed memory +ors correcty.

(o+3 ,ests dm +"ere t"e #c is oaded +"ic" causes a jum#. At t"e same time t"e mode is c"an!ed.,"is is re#eated +it" t"e cac"e enabed.

"iboot8mem ,ests +is"bone read and +rite access to "i Bnon9cac"abeC boot S&AM.

in(ate8bu! A oad store se:uence +as (ound to not eecute correcty.

ir: ,ests runnin! a sim#e a!orit"m to add a bunc" o( numbers and c"ec t"at t"e resut is correct.,"is a!orit"m runs


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.ame ,escription

+it" t"is +orst case.

stm1 ,ests t"e norma o#eration o( t"e stm instruction.

stm2 ,est jum#s into user mode oads some 5aues into re!isters r< 9 r14 t"en jum#s to FI&E andsa5es t"e user mode re!isters to memory.

strb ,ests str and strb +it" di((erent indein! modes.

sub ,ests sub and subs.

s+i ,ests t"e so(t+are interru#t = s+i.

s+#8oc8bu! ;u! broe an instruction read immediatey a(ter a s+# instruction.

s+# ,ests s+# and s+#b.

uart8re! ,ests +is"bone read and +rite access to t"e Amber UA&, re!isters.

uart8rint ,ests t"e UA&, recei5e interru#t (unction. Some tet is sent (rom t"e test8uart to t"e uart and aninterru#t !enerated.

uart8r ,ests t"e UA&, recei5e (unction.

uart8t Uses t"e tb8uart in oo#bac mode to 5eri(y t"e transmitted data.

unde(ined8ins ,ests Unde(ined Instruction Interru#t. Fires a (e+ unsu##orted (oatin! #oint unit BFPUC instructions

into t"e core. ,"ese cause unde(ined instruction interru#ts +"en eecuted.

2+6 C Programs

(n addition to the short assembly lan!$a!e tests% some lon!er pro!rams "ritten in &

are incl$ded "ith the Amber system These can be $sed to #$rther test and veri#y the

system% or as a basis to develop yo$r o"n applications

The so$rce code #or these pro!rams is in 4A3)2AS)


15/22


# r J deadbee2# r8D deadbee2# r88 deadbee2# r8; DDDDDD9@# r8? DDDD;2N# sp D82222@D# pc DDDD;2?#

# ----------------------------------------------------------------------------# mber ore# 5ser F7'P 7'P > )I# rD D"DDDDDDD8# r8 D"DDDD8c?# r; D"DDDDDDDD# r? D"DDDDDDDD# r9 D"deadbee2# r D"deadbee2# r D"deadbee2# rN D"deadbee2# r@ D"deadbee2 D"deadbee2# rJ D"deadbee2 D"deadbee2# r8D D"DDDDDD88 D"deadbee2# r88 D"2DDDDDDD D"deadbee2# r8; D"DDDDDD9@ D"deadbee2# r8? D"deadbee2 D"deadbee2 D"deadbee2 D"D82222cD# r89 GlrH D"deadbee2 D"deadbee2 D"deadbee2 D";DDDDN?# r8 GpcH D"DDDD8;D

## )tatus %its: 4*D= *8= *8= I*D= 7'P ask D= F7'P ask D= ode * )upervisor# ----------------------------------------------------------------------------## QQQQQQQQQQQQQQQQQQQQ# +assed boot-loader# QQQQQQQQQQQQQQQQQQQQ

The boot loader is $sed to do"nload lon!er applications onto the FPGA development

board via the 1A2T port and $sin! ?yper Terminal on a host indo"s P&

2+6+2 0ello orl(

This is located in 4A3)2AS)


16/22


> s)ocket 7E D+ackets received 8D+ackets transmitted J+ackets resent D,+ checksum errors Dounterparty 7+ 8J;[email protected].;ounterparty +ort ?8@

alloc pointer D"D8;;?DDalloc count ?85ptime ;8 seconds>

2+4 'inu5

A memory #ile is provided to r$n a sim$lation o# 7in$x bootin! The main reason #or

providin! this #ile is to have a lon! test to #$rther validate the correct operation o# the

core This #ile "as created #rom a modi#ied version o# the + .ernel "ith the

patch-+-vrs*b= patch #ile applied and then some modi#ications made to so$rce

#iles to s$pport the speci#ic hard"are in the Amber FPGA

The vmlin$xmem memory #ile contains an embedded ext #ormat ramdis. ima!e

"hich contains the hello-"orld pro!ram% b$t renamed as


17/22


# IF): ounted root Ge"t; 2ilesystemH readonly.# Freeing init memory: ?;K# ello= LorldO## ----------------------------------------------------------------------------# mber ore# > 5ser F7'P 7'P )I# rD D"DDDDDD8D

# r8 D"DD@DeeDD# r; D"DDDDDDDD# r? D"DDDDDDDD# r9 D"DDDDDDDD# r D"DDDDDDDD# r D"DDDDDDDD# rN D"DDDDDDDD# r@ D"DDDDDDDD D"deadbee2# rJ D"DDDDDDDD D"deadbee2# r8D D"DDDDDD88 D"deadbee2# r88 D"2DDDDDDD D"deadbee2# r8; D"DDDDDDDD D"deadbee2# r8? D"D8J2229D D"deadbee2 D"D;8Dbca9 D"D;882e@# r89 GlrH D"DDDDDDDD D"deadbee2 D";;Da9?N2 D"DD@De9;@# r8 GpcH D"DD@De@DD## )tatus %its: 4*D= *8= *8= I*D= 7'P ask D= F7'P ask D= ode * 5ser# ----------------------------------------------------------------------------#

# QQQQQQQQQQQQQQQQQQQQ# +assed vmlinu"# QQQQQQQQQQQQQQQQQQQQ

The pro!ram trace $tility can be $sed to trace the 7in$x exec$tion% as #ollo"s9

$ cd $%&'(%)&/hw/sim$ ln -s ../../sw/tools/amber-!umps.sh !umps$ !umps vmlinu"



18/22


3 FPGA Snt!esis

A ma.e#ile is provided that per#orms synthesis o# the system to a Xilinx Spartan-6

FPGA To $se this ma.e#ile yo$ m$st have Xilinx (S) installed ( have tested it "ith

(S) v*+5 The ma.e#ile is H$ite #lexible To see all its options% type9

$ cd $%&'(%)&/hw/2pga/bin$ make help

To $se the script to per#orm a complete synthesis r$n #rom start to #inish and !enerate

a bit#ile9

$ cd $%&'(%)&/hw/2pga/bin$ chmod Q" V.sh$ make new

The script per#orms the #ollo"in! steps

* &ompiles the boot loader pro!ram in 4A3)2AS)


19/22


$ make

The system cloc. speed is con#i!$red "ithin the FPGA ma.e#ile%

4A3)2AS)


20/22


# $sing %oot&'oa(er

(# yo$ have a development board "ith a 1A2T connection to a P& yo$ can $se boot-

loader to do"nload and r$n applications on the board ( have tested this "ith the

Xilinx SP605 development board (t provides a 1A2T connection via a 1S port on

the board

#+1 -nstall an( configure inicom

The #ollo"in! commands installs the ls$sb and minocom $tilities9

$ sudo yum install usbutils$ sudo yum install minicom

&onnect the SP605 serial port 1S to the P& and chec. that the port is visible9

ls -l /dev/tty5)%Dcrw-rw---- 8 root dialout 8@@= D ay 9 88:D; /dev/tty5)%D

$ lsusb%us DD8 Eevice DD8: 7E 8db:DDD; 1inu" Foundation ;.D root hub%us DD; Eevice DD8: 7E 8db:DDD; 1inu" Foundation ;.D root hub%us DD? Eevice DD8: 7E 8db:DDD8 1inu" Foundation 8.8 root hub%us DD9 Eevice DD8: 7E 8db:DDD8 1inu" Foundation 8.8 root hub%us DD Eevice DD8: 7E 8db:DDD8 1inu" Foundation 8.8 root hub%us DD Eevice DD8: 7E 8db:DDD8 1inu" Foundation 8.8 root hub%us DDN Eevice DD8: 7E 8db:DDD8 1inu" Foundation 8.8 root hub%us DD@ Eevice DD8: 7E 8db:DDD8 1inu" Foundation 8.8 root hub%us DD8 Eevice DD;: 7E De?:DD@ 3enesys 1ogic= 7nc. 5)%-;.D 9-+ort 5%%us DD Eevice DD;: 7E D9e:a %ehavior ,ech. omputer orp.%us DD Eevice DD?: 7E D92?:D;8; &lan icroelectronics orp. 1aser ouse%us DD; Eevice D8?: 7E D?2d:DDD@ 6ilin"= 7nc.

Bus 008 Device 006: ID 10c4:ea60 Cygnal Integrated Products, Inc. CP210x !"# Bridge $%y!&" %y'%art'B lig(t

&on#i!$re minicom

sudo minicom -s

Q-----------------------------------------------------------------------Q W - )erial Eevice : /dev/tty5)%D W W % - 1ock2ile 1ocation : /var/lock W W - allin +rogram : W W E - allout +rogram : W

W & - %ps/+ar/%its : J;8DD @48 W W F - ardware Flow ontrol : Xes W W 3 - )o2tware Flow ontrol : 4o W W W W hange which settingY W Q-----------------------------------------------------------------------Q

Save set$p as d#l Then to r$n minicom%

> sudo minicom



21/22


#+2 Configure t!e FPGA

7oad the bit#ile into the FPGA on the development board This can be done $sin!

Xilinx i3PA&T 'nce the FPGA is con#i!$red the boot loader "ill print some

messa!es via the 1A2T inter#ace onto the minicom screen% as #ollo"s9



22/22


* 'icense

All so$rce code provided in the Amber pac.a!e is release $nder the #ollo"in! license

terms9

opyright GH ;D8D uthors and 0+&40'&).0'3

,his source 2ile may be used and distributed withoutrestriction provided that this copyright statement is notremoved 2rom the 2ile and that any derivative work containsthe original copyright notice and the associated disclaimer.,his source 2ile is 2ree so2twareZ you can redistribute itand/or modi2y it under the terms o2 the 345 1esser 3eneral+ublic 1icense as published by the Free )o2tware FoundationZeither version ;.8 o2 the 1icense= or Gat your optionH anylater version.

,his source is distributed in the hope that it will beuse2ul= but L7,05, 4X L''4,XZ without even the impliedwarranty o2 &'4,%717,X or F7,4&)) F0' +',751'+5'+0)&. )ee the 345 1esser 3eneral +ublic 1icense 2or moredetails.

Xou should have received a copy o2 the 345 1esser 3eneral+ublic 1icense along with this sourceZ i2 not= download it2rom http://www.opencores.org/lgpl.shtml

uthorGsH:- onor )anti2ort= csanti2ort.amberCgmail.com

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