amd opteron - amd64 architecture sean downes

Click here to load reader

Post on 24-Jan-2016




0 download

Embed Size (px)


AMD Opteron - AMD64 Architecture Sean Downes. Description. Released April 22, 2003 The AMD Opteron is a 64 bit microprocessor designed for use in server applications. Available with single, dual, quad, six, and twelve cores. Up to 8-way scalability. Registers. - PowerPoint PPT Presentation


  • AMD Opteron - AMD64 ArchitectureSean Downes

  • DescriptionReleased April 22, 2003

    The AMD Opteron is a 64 bit microprocessor designed for use in server applications. Available with single, dual, quad, six, and twelve cores.Up to 8-way scalability.

  • Registers

  • Instruction types 128-Bit Media InstructionsThese are the streaming SIMDextension (SSE and SSE2) instructions that load, store, oroperate on data located primarily in the 128-bit XMMregisters. 128-Bit Media Instructions support 32-bit single-precision and 64-bit double-precision floating-point operations, in addition to integer operations. Operations on both vector data and scalar data are supported.Because the vector instructions can independently andsimultaneously perform a single operation on multiple setsof data, they are called single-instruction, multiple-data(SIMD) instructions. They are useful for high-performancemedia and scientific applications that operate on blocks ofData.

  • Instruction types 64-Bit Media InstructionsThese are the multimediaextension (MMX technology) and AMD 3DNow!technology instructions. They load, store, or operate on datalocated primarily on the 64-bit MMX registers. Like their128-bit counterparts, they perform integerand floating-point operations on vector (packed) and scalardata types. Thus, they are also SIMD instructions and areuseful in media applications that operate on blocks of data.

  • Instruction typesx87 Floating-Point InstructionsThese are the floating-point instructions used in legacy x87 applications. They load, store, or operate on data located in the x87 registers.x87 Floating-Point Instructions support single-precision, double-precision, and 80-bit extended-precision floating point operations. Only scalar data are supported, with a dedicated floating-point exception-reporting mechanism.

  • 16-bit mode Legacy mode or compatibility mode in which a 16-bit address size is active. See legacy mode and compatibility mode.

    32-bit mode Legacy mode or compatibility mode in which a 32-bit address size is active.

    64-bit mode A submode of long mode. In 64-bit mode, the default address size is 64 bits and new features, such as register extensions, are supported for system and application software. Programming Modes

  • CISC, but it acts like RISC... The x86 architecture dominates the PC and server markets, but the guts of modern x86 chips are very RISC-like. The combination is made possible by translating complex individual instructions into short sequences of simple ones. It sounds a little awkward but works well in practice; this approach has been standard for 10 years now.

  • Layout

  • Layout

  • Design PrinciplesSimplicity favors regularity Once mode is chosen all instructions take the same format and regardless of mode same basic instructions are supported.Smaller is faster Large CISC instructions broken down into smaller pieces.Make the common case fast On chip hardware support for floating point operations.Good design demands good compromises Complicated to program and operation mode must be chosen for given hardware but results in high performance.

  • ReferencesAMD64 Architecture Programmers Manual Volumes 1, 2, 3, 4, 5 -,,30_2252_875_7044,00.html

View more