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Reliable Architecture for Flash Memory. Amit Berman. Joint work with Uri C. Weiser, Acknowledgement: thanks to Idit Keidar Department of Electrical Engineering, Technion – Israel Institute of Technology. Agenda. Reliability in Flash Memory “ Reliable Architecture ” - PowerPoint PPT Presentation


  • *Amit Berman

    Reliable Architecture for Flash Memory Joint work with Uri C. Weiser, Acknowledgement: thanks to Idit Keidar

    Department of Electrical Engineering, Technion Israel Institute of Technology

  • *Agenda

    Reliability in Flash Memory Reliable Architecture The advantages of Reliable ArchitectureDensity Performance Conclusions

  • *Introduction Reliability: a crucial factor in flash memory design Quantification: Guaranteed # of times that a memory cell can be written and erased before an error occurs Our goal is to reduce the number of physical write/erase operations of the flash memory cells Basic physical characteristic of flash memory cell: every write/erase operation, the memory cell is degraded Eventually, there would be a data error in the memory cell, proportional to the number of write/erase operationsAnalogy : Flash memory cell as a glass of waterLevel -1 The amount of water in the glass represents the information Each time we will fill and empty the glass it will be cracked

  • *1 bit per cell (1BPC)Ref# of cellsVt Erased Programmed :Level 1 0 :BitEmptyFullRef2# of cellsVt 0 1 2 3 :LevelRef3Ref1 11 10 01 00 :BitLevel-0Level-0Level -1Level -1Level -2Level -2Level -3Level -3Reliability is important for density Bad reliability low density Good reliability high density2 bits per cell (2BPC) fewer glass cracks, low water leakage we can distinguish between more levelsReliable Architecture technique increase the reliabilityWe can use it to increase the density and keep constant reliabilityIncrease density decrease reliability

  • *Reliability is important for performanceRef2# of cellsVt 0 1 2 3 :LevelRef3Ref1 11 10 01 00 :Bit Bad reliability low writing speed Good reliability high writing speedRef2# of cellsVt 0 1 2 3 :LevelRef3Ref1 11 10 01 00 :BitLevel-0Level-0Level -2Level -2Level-0Level-0Level -2Level -2 glass cracks makes it hard to fill it

  • *Related Work Coding MFG Process* M. Schwartz, S. Bruck Rank Modulation for Flash Memories* M. Yanai, I. Bloom NROM memory cell design

  • *Observation Flash data is erased in blocks (e.g. 64KB) There are redundant write and erase operations The memory needs to be erased in order to write new information Erase operation lasts long (e.g. 1.5mS) cells are erased in groupseraseerasewriteThe cell returned to its original level

  • *Observation: ExampleVtVtVtTimeT3T2T1 There are redundant write and erase operationsAt time T1, information is writtenBlock is erased to enable new writeNew write is same as the initial valueIn this process there are total 2 writes and 1 erase operations,can we reduce it to 1 write operation?

  • * New concept of operating flash memoryCommon Architecture vs. Reliable ArchitectureReliable ArchitectureWrite Re-writeErase Virtual EraseRead (no change)

  • *Flash Re-write Conceptread the stored data, compare it to the input data and adjust for the difference if existsRe-write conceptread and adjustIf equal: do nothingIf difference: adjust

  • * Virtual erase process: when erase is applied to a certain block/page Mark a flag in the spare memory array for erase indicationVirtual erase concept Data is not physically erasederasevirtual eraseflagflag Construct a spare memory array that contain information about erase status

  • *Reliable Architecture: changes to the current architectureTarget: Avoid redundant write and erase operationsChanges: Arrange the memory array so that erase in a single cell is enabledChange the control logic for the new operationsAdd spare memory cells for virtual erase operation

  • *Analysis : symmetric binary sourceNT=# of bits with no transitionl= # of flash memory levelsn= # of bits in a pageWhile applying memory write, average # of cells with no transition:Average # of cells with write transition:Average # of cells with erase transition:

  • *Example 25% of the memory cells have write transition 25% of the memory cells have erase transitionFor 2-levels flash with random input data source: Saves 50% of write/erase operations, x2 improvementEach writing operation 50% of the memory cells hold the same value* Taking into account Gaussian distribution

  • *Reliability Improvement Factor (RIF) while using Reliable ArchitectureRIF is lower bound since we also save some transitions between levels

  • *Performance analysisErase Operation ~1.5msWrite Operation ~0.8ms(2KB page)In a large page size, the write performance is better then the one in common architecture On small page size, the erase transition reduce performanceWriting is done sequentially due to current consumption limitationsErase can be done in parallel, for any # of memory cells The Reliable Architecture re-write concept uses the erase operation on some of the cells Reliable architecture has advantage in large page size:

  • *Performance analysisModeling results of flash memory cells, write and erase operations with varying page size, utilizing a symmetric data source*MATLABReliable Architecture is effective in large page size (>8KB)

  • *Summary Reliable Architecture improves reliability by the elimination of the redundant write/erase operations to the flash memory Reliable Architecture statistically improves flash memory reliability Reliable Architecture is improving the write performance in page size >8KB in a smaller page size, write performance is reduced Can be used to increase reliabilityCan be use to increase density and keep reliability constant

  • *Questions?High DensityLow $/MBNonvolatileUpdateableROMEPROMDRAMEEPROMSRAM