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Amit Berman

Reliable Architecture for Flash Memory

Joint work with Uri C. Weiser, Acknowledgement: thanks to Idit Keidar

Department of Electrical Engineering, Technion – Israel Institute of Technology

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Agenda

Reliability in Flash Memory

“Reliable Architecture”

The advantages of “Reliable Architecture”

• Density

• Performance

Conclusions

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Introduction

Reliability: a crucial factor in flash memory design

Quantification: Guaranteed # of times that a memory cell can be written and erased before an error occurs

Our goal is to reduce the number of physical write/erase operations of the flash memory cells

• Basic physical characteristic of flash memory cell: every write/erase operation, the memory cell is degraded

• Eventually, there would be a data error in the memory cell, proportional to the number of write/erase operations

Analogy : Flash memory cell as a glass of water

Level - 1Level - 1Level - 1

• The amount of water in the glass represents the information• Each time we will fill and empty the glass – it will be cracked

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1 bit per cell (1BPC)

Ref

# o

f ce

lls

Vt

Erased Programmed :Level

1 0 :Bit

Empty

Full

Ref2

# o

f ce

lls

Vt

0 1 2 3 :Level

Ref3Ref1

11 10 01 00 :Bit

Level- 0

Level - 1

Level - 2

Level - 3

Level- 0Level- 0Level- 0

Level - 1Level - 1Level - 1

Level - 2Level - 2Level - 2

Level - 3Level - 3Level - 3Level - 3

Reliability is important for density

Bad reliability low density

Good reliability high density

2 bits per cell (2BPC)

“fewer glass cracks, low water leakage” we can distinguish between more levels

Reliable Architecture technique increase the reliabilityWe can use it to increase the density and keep constant reliability

Increase density decrease reliability

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Reliability is important for performance

Ref2

# o

f ce

lls

Vt

0 1 2 3 :Level

Ref3Ref1

11 10 01 00 :Bit

Bad reliability low writing speed

Good reliability high writing speed

Ref2

# o

f ce

lls

Vt

0 1 2 3 :Level

Ref3Ref1

11 10 01 00 :Bit

Level- 0

Level - 2

Level- 0Level- 0Level- 0

Level - 2Level - 2Level - 2

Level- 0

Level - 2

Level- 0Level- 0Level- 0

Level - 2Level - 2Level - 2

Level- 0Level- 0 Level- 0Level- 0

“glass cracks makes it hard to fill it”

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Related Work

Coding

MFG Process

* M. Schwartz, S. Bruck “Rank Modulation for Flash Memories”

* M. Yanai, I. Bloom “NROM memory cell design”

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Observation

Flash data is erased in blocks (e.g. 64KB)

There are redundant write and erase operations

• The memory needs to be erased in order to write new information

• Erase operation lasts long (e.g. 1.5mS) cells are erased in groups

erase

erase write

The cell returned to its original level

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Observation: Example

Vt

Vt

Vt

Time

T3

T2

T1

There are redundant write and erase operations

At time T1, information is written

Block is erased to enable new write

New write is same as the initial value

In this process there are total 2 writes and 1 erase operations,can we reduce it to 1 write operation?

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New concept of operating flash memory

Common Architecture vs. Reliable Architecture

Reliable Architecture

Write Re-write

Erase Virtual Erase

Read (no change)

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Flash Re-write Conceptread the stored data, compare it to the

input data and adjust for the difference if exists

Re-write concept

read and adjust

If equal: do nothingIf difference: adjust

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Virtual erase process: when erase is applied to a certain block/page Mark a flag in the spare memory array for erase indication

Virtual erase concept

Data is not physically erased

Non-VolatileMemory Array

Spare NVMValid Indication

Control Logic

Analog HV

I/O

erase

virtual erase

flag flag

Construct a “spare memory array” that contain information about erase status

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Reliable Architecture: changes to the current architecture

Target: Avoid redundant write and erase operations

Changes: Arrange the memory array so that erase in a single cell is enabled

Change the control logic for the new operations

Add spare memory cells for virtual erase operation

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Analysis : symmetric binary source

( , ) ( , )ET l n PT l n

1 1

1 1 22( , )2 2 2 2

ll

l l

ll l

PT l n n n n

( , )2ll

NT l n n NT=# of bits with no transitionl= # of flash memory levelsn= # of bits in a page

While applying memory write, average # of cells with no transition:

Average # of cells with write transition:

Average # of cells with erase transition:

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Example

( , ) ( , )ET l n PT l n

2

2 1

2 2 1( , )

2 4PT l n n n

25% of the memory cells have write transition

25% of the memory cells have erase transition

For 2-levels flash with random input data source:

Saves 50% of write/erase operations, x2 improvement

Each writing operation 50% of the memory cells hold the same value

2

2 1( , )

2 2NT l n n n

* Taking into account Gaussian distribution

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Reliability Improvement Factor (RIF) while using Reliable Architecture

2 4 6 8 10 12 14 162

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

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Flash Memory Levels

RIF

12( )

( , ) 2

l

l

nRIF l

ET l n l

( ) 2lRIF l

RIF is lower bound since we also save some transitions between levels

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Performance analysis

Erase Operation ~1.5ms

Write Operation ~0.8ms

(2KB page)

In a large page size, the write performance is better then the one in common architecture

On small page size, the erase transition reduce performance

Writing is done sequentially due to current consumption limitations

Erase can be done in parallel, for any # of memory cells

The Reliable Architecture re-write concept uses the erase operation on some of the cells

Reliable architecture has advantage in large page size:

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0 5 10 15 20 250

1

2

3

4

5

6

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Page Size [KB]

Pro

gram

Tim

e [m

S]

Program Time Vs. Page Size

Common Architecture

New Architecture

Performance analysis

Modeling results of flash memory cells, write and erase operations with varying page size, utilizing a symmetric data source

*MATLAB

Reliable Architecture is effective in large page size (>8KB)

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Summary

Reliable Architecture improves reliability by the elimination of the redundant write/erase operations to the flash memory

Reliable Architecture statistically improves flash memory reliability

Reliable Architecture is improving the write performance in page size >8KB in a smaller page size, write performance is reduced

• Can be used to increase reliability• Can be use to increase density and keep reliability constant

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Questions?

High DensityLow $/MB

NonvolatileUpdateable

ROMEPROM

DRAM

EEPROM

FLASHFLASHSRAM