ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ... 11-ece 307… · ¤ consumes only dynamic...
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ΗΜΥ 307ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ
ΚΥΚΛΩΜΑΤΑΕαρινό Εξάμηνο 2018
ΔΙΑΛΕΞΗ 11: Dynamic
CMOS Circuits
ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy)(ack: Prof. Mary Jane Irwin and Vijay Narayanan)
[Προσαρμογή από “Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.”]
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .2 © Θεοχαρίδης, ΗΜΥ, 2018
Dynamic CMOSl In static circuits at every point in time (except when
switching) the output is connected to either GND or VDD via a low resistance path.¤ fan-in of N requires 2N devices
l Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.¤ requires only N + 2 transistors¤ takes a sequence of precharge and conditional evaluation
phases to realize logic functions
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .4 © Θεοχαρίδης, ΗΜΥ, 2018
Dynamic Gate
In1
In2 PDNIn3
Me
Mp
CLK
CLKOut
CL
Out
CLK
CLK
A
BC
Mp
Me
Two phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)
on
off
1off
on
!((A&B)|C)
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .5 © Θεοχαρίδης, ΗΜΥ, 2018
Conditions on Outputl Once the output of a dynamic gate is discharged, it cannot
be charged again until the next precharge operation.l Inputs to the gate can make at most one transition during
evaluation.
l Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .6 © Θεοχαρίδης, ΗΜΥ, 2018
Properties of Dynamic Gatesl Logic function is implemented by the PDN only
¤ number of transistors is N + 2 (versus 2N for static complementary CMOS)
¤ should be smaller in area than static complementary CMOS
l Full swing outputs (VOL = GND and VOH = VDD)
l Nonratioed - sizing of the devices is not important for proper functioning (only for performance)
l Faster switching speeds¤ reduced load capacitance due to lower number of transistors per
gate (Cint) so a reduced logical effort
¤ reduced load capacitance due to smaller fan-out (Cext)
¤ no Isc, so all the current provided by PDN goes into discharging CL
¤ Ignoring the influence of precharge time on the switching speed of the gate, tpLH = 0 but the presence of the evaluation transistor slows down the tpHL
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .7 © Θεοχαρίδης, ΗΜΥ, 2018
Properties of Dynamic Gates, con’tl Power dissipation should be better
¤ consumes only dynamic power – no short circuit power consumption since the pull-up path is not on when evaluating
¤ lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two)
¤ by construction can have at most one transition per cycle – no glitching
l But power dissipation can be significantly higher due to¤ higher transition probabilities¤ extra load on CLK
l PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn¤ low noise margin (NML)
l Needs a precharge clock
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .8 © Θεοχαρίδης, ΗΜΥ, 2018
Dynamic Behavior
-0.5
0.5
1.5
2.5
0 0.5 1
CLK
CLK
In1
In2
In3
In4
Out
In &CLK Out
Time, ns
Volta
ge
#Trns VOH VOL VM NMH NML tpHL tpLH tp
6 2.5V 0V VTn 2.5-VTn VTn 110ps 0ns 83ps
Evaluate
Precharge
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .9 © Θεοχαρίδης, ΗΜΥ, 2018
Gate Parameters are Time Independentl The amount by which the output voltage drops is a strong
function of the input voltage and the available evaluation time.¤ Noise needed to corrupt the signal has to be larger if the
evaluation time is short – i.e., the switching threshold is truly time independent.
-0.5
0.5
1.5
2.5
0 20 40 60 80 100Time (ns)
Volta
ge (V
)
VG
CLK
Vout (VG=0.55)Vout (VG=0.5)
Vout (VG=0.45)
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .10 © Θεοχαρίδης, ΗΜΥ, 2018
Power Consumption of Dynamic Gate
In1
In2 PDNIn3
Me
Mp
CLK
CLKOut
CL
Power only dissipated when previous Out = 0
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .11 © Θεοχαρίδης, ΗΜΥ, 2018
Dynamic Power Consumption is Data Dependent
A B Out
0 0 1
0 1 0
1 0 0
1 1 0
Dynamic 2-input NOR Gate
Assume signal probabilitiesPA=1 = 1/2PB=1 = 1/2
Then transition probabilityP0®1 = Pout=0 x Pout=1
= 3/4 x 1 = 3/4
Switching activity can be higher in dynamic gates!P0®1 = Pout=0
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .12 © Θεοχαρίδης, ΗΜΥ, 2018
Issues in Dynamic Design 1: Charge Leakage
CL
CLK
CLKOut
A=0
Mp
Me
Minimum clock rate of a few kHz
Leakage sources
CLK
VOut
Precharge
Evaluate
1
2
34
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .13 © Θεοχαρίδης, ΗΜΥ, 2018
Impact of Charge Leakagel Output settles to an intermediate voltage determined by a
resistive divider of the pull-up and pull-down networks¤ Once the output drops below the switching threshold of the
fan-out logic gate, the output is interpreted as a low voltage.
-0.5
0.5
1.5
2.5
0 20 40
Time (ms)
Vo
ltag
e (V
)
CLK
Out
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .14 © Θεοχαρίδης, ΗΜΥ, 2018
A Solution to Charge Leakage
CL
CLK
CLK
Me
Mp
A
B
!Out
Mkp
Same approach as level restorer for pass transistor logic
Keeper
q Keeper compensates for the charge lost due to the pull-down leakage paths.
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .15 © Θεοχαρίδης, ΗΜΥ, 2018
Issues in Dynamic Design 2: Charge Sharing
CL
CLK
CLK
Ca
Cb
B=0
AOut
Mp
Me
Charge stored originally on CL is redistributed (shared) over CL and CA leading to static power consumption by downstream gates and possible circuit malfunction.
When DVout = - VDD (Ca / (Ca + CL )) the drop in Vout is large enough to be below the switching threshold of the gate it drives causing a malfunction.
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .17 © Θεοχαρίδης, ΗΜΥ, 2018
Charge Sharing ExampleWhat is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V.)
Cy=50fF
CLK
CLK
A !A
B !B B !B
C!C
y = A Å B Å C
Ca=15fF
Cc=15fF
Cb=15fF
Cd=10fF
Loadinverter
a
b
dc
DVout = - VDD ((Ca + Cc)/((Ca + Cc) + Cy))
= - 2.5V*(30/(30+50)) = -0.94V
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .18 © Θεοχαρίδης, ΗΜΥ, 2018
Solution to Charge Redistribution
CLK
CLK
Me
Mp
A
B
OutMkp
CLK
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .19 © Θεοχαρίδης, ΗΜΥ, 2018
Issues in Dynamic Design 3: Backgate Coupling
CL1
CLK
CLK
B=0
A=0
Out1Mp
Me
Out2
CL2
In
Dynamic NAND Static NAND
=1=0
q Susceptible to crosstalk due to 1) high impedance of the output node and 2) capacitive coupling
● Out2 capacitively couples with Out1 through the gate-source and gate-drain capacitances of M4
M1
M2M3
M4
M5M6
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .20 © Θεοχαρίδης, ΗΜΥ, 2018
Backgate Coupling Effect
-1
0
1
2
3
0 2 4 6
Volta
ge
Time, ns
CLK
In
Out1
Out2
q Capacitive coupling means Out1 drops significantly so Out2 doesn’t go all the way to ground
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .21 © Θεοχαρίδης, ΗΜΥ, 2018
Issues in Dynamic Design 4: Clock Feedthrough
CL
CLK
CLK
B
AOut
Mp
Me
Coupling between Out and CLK input of the precharge device due to the gate-drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
q A special case of capacitive coupling between the clock input of the precharge transistor and the dynamic output node
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .22 © Θεοχαρίδης, ΗΜΥ, 2018
Clock Feedthrough
-0.5
0.5
1.5
2.5
0 0.5 1
CLK
CLK
In1
In2
In3
In4
Out
In &CLK
Out
Time, ns
Volta
ge
Clock feedthrough
Clock feedthrough
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .23 © Θεοχαρίδης, ΗΜΥ, 2018
Cascading Dynamic Gates
CLK
CLK
Out1In
Mp
Me
Mp
Me
CLK
CLK
Out2
V
t
CLK
In
Out1
Out2 DV
VTn
Only a single 0 ® 1 transition allowed at the inputs during the evaluation period!
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .24 © Θεοχαρίδης, ΗΜΥ, 2018
Domino Logic
In1
In2 PDNIn3
Me
Mp
CLK
CLK Out1
In4 PDNIn5
Me
Mp
CLK
CLKOut2
Mkp
1 ® 11 ® 0
0 ® 00 ® 1
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .25 © Θεοχαρίδης, ΗΜΥ, 2018
Why Domino?
In1
CLK
CLK
Ini PDNInj
IniInj
PDN Ini PDNInj
Ini PDNInj
Like falling dominos!
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .27 © Θεοχαρίδης, ΗΜΥ, 2018
Domino Manchester Carry Chain
Ci,0 G0
CLK
CLKP0 P1 P2 P3
G1 G2 G3
Ci,41234
5
6
3 3 3 3 3
1
2
2
3
3
4
4
5
!(G0 + P0 Ci,0) !(G1 + P1G0 + P1P0 Ci,0)
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .29 © Θεοχαρίδης, ΗΜΥ, 2018
CLKA3
B3
A2
B2
A1
B1
A0
B0
Out
Domino Comparator
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .30 © Θεοχαρίδης, ΗΜΥ, 2018
Properties of Domino Logic
l Only non-inverting logic can be implemented, fixes include¤ can reorganize the logic using Boolean transformations¤ use differential logic (dual rail)¤ use np-CMOS (zipper)
l Very high speed¤ tpHL = 0¤ static inverter can be optimized to match fan-out (separation of
fan-in and fan-out capacitances)
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .31 © Θεοχαρίδης, ΗΜΥ, 2018
Differential (Dual Rail) Domino
A
B
Me
Mp
CLK
CLK!Out = !(AB)
!A !B
MkpCLK
Out = AB
Mkp Mp
Due to its high-performance, differential domino is very popular and is used in several commercial
microprocessors!
1 0 1 0
onoff
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .32 © Θεοχαρίδης, ΗΜΥ, 2018
np-CMOS (Zipper)
In1
In2 PDNIn3
Me
Mp
CLK
CLK Out1
In4 PUNIn5
Me
Mp!CLK
!CLK
Out2(to PDN)
1 ® 11 ® 0
0 ® 00 ® 1
Only 0 ® 1 transitions allowed at inputs of PDN Only 1 ® 0 transitions allowed at inputs of PUN
to otherPDN’s
to otherPUN’s
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .33 © Θεοχαρίδης, ΗΜΥ, 2018
np-CMOS Adder Circuit
B0 C0
C0
C0
!C1
!Sum0B0A0
A0
B0B0 A0
A0
CLK
CLK !CLK
!CLK
C2
Sum1!A1
!A1
!B1!B1!A1!A1!B1
!B1
!C1
!C1
!CLK
!CLK CLK
CLK
1 ® x
0 ® x
0 ® x
1 ® x
0 ® x
0 ® x
1 ® x
1 ® x
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .35 © Θεοχαρίδης, ΗΜΥ, 2018
DCVS Logic
In1
In2PDN1
Out
!In1
!In2
PDN2
!Out
PDN1 and PDN2 are mutually exclusive
1 0® 0 on off
off® on on® off
® on® off ® 1
Differential Cascade Voltage Switch Logic
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .36 © Θεοχαρίδης, ΗΜΥ, 2018
DCVSL Example
Out!Out
B
A !A
B!B!B
ΗΜΥ307 Δ11 Dynamic CMOS Circuits .37 © Θεοχαρίδης, ΗΜΥ, 2018
How to Choose a Logic Stylel Must consider ease of design, robustness (noise immunity),
area, speed, power, system clocking requirements, fan-out, functionality, ease of testing
Style # Trans Ease Ratioed? Delay PowerComp Static 8 1 no 3 1
CPL* 12 + 2 2 no 4 3
domino 6 + 2 4 no 2 2 + clk
DCVSL* 10 3 yes 1 4
4-input NAND
* Dual Rail
q Current trend is towards an increased use of
complementary static CMOS: design support through DA
tools, robust, more amenable to voltage scaling.
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