1 1998 morgan kaufmann publishers arithmetic where we've been: –performance (seconds,...
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11998 Morgan Kaufmann Publishers
Arithmetic
• Where we've been:– Performance (seconds, cycles, instructions)– Abstractions:
Instruction Set Architecture Assembly Language and Machine Language
• What's up ahead:– Implementing the Architecture
21998 Morgan Kaufmann Publishers
Arithmetic
• We start with the Arithmetic and Logic Unit
32
32
32
operation
result
a
b
ALU
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• Bits are just bits (no inherent meaning)— conventions define relationship between bits and numbers
• Binary numbers (base 2)0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...decimal: 0...2n-1
• Of course it gets more complicated:numbers are finite (overflow)fractions and real numbersnegative numbers
• How do we represent negative numbers?i.e., which bit patterns will represent which numbers?
• Octal and hexadecimal numbers
• Floating-point numbers
Numbers
41998 Morgan Kaufmann Publishers
• Sign Magnitude: One's Complement Two's Complement000 = +0 000 = +0 000 = +0001 = +1 001 = +1 001 = +1010 = +2 010 = +2 010 = +2011 = +3 011 = +3 011 = +3100 = -0 100 = -3 100 = -4101 = -1 101 = -2 101 = -3110 = -2 110 = -1 110 = -2111 = -3 111 = -0 111 = -1
• Issues: balance, number of zeros, ease of operations.• Two’s complement is best.
Possible Representations of Signed Numbers
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• 32 bit signed numbers:
0000 0000 0000 0000 0000 0000 0000 00002 = 010
0000 0000 0000 0000 0000 0000 0000 00012 = +110
0000 0000 0000 0000 0000 0000 0000 00102 = +210
...0111 1111 1111 1111 1111 1111 1111 11102 = +2,147,483,64610
0111 1111 1111 1111 1111 1111 1111 11112 = +2,147,483,64710
1000 0000 0000 0000 0000 0000 0000 00002 = –2,147,483,64810
1000 0000 0000 0000 0000 0000 0000 00012 = –2,147,483,64710
1000 0000 0000 0000 0000 0000 0000 00102 = –2,147,483,64610
...1111 1111 1111 1111 1111 1111 1111 11012 = –310
1111 1111 1111 1111 1111 1111 1111 11102 = –210
1111 1111 1111 1111 1111 1111 1111 11112 = –110
maxint
minint
MIPS
61998 Morgan Kaufmann Publishers
• Negating a two's complement number: invert all bits and add 1
– Remember: “Negate” and “invert” are different operations.
You negate a number but invert a bit.
• Converting n bit numbers into numbers with more than n bits:
– MIPS 16 bit immediate gets converted to 32 bits for arithmetic
– copy the most significant bit (the sign bit) into the other bits
0010 -> 0000 0010
1010 -> 1111 1010
"sign extension"
– MIPS load byte instructions
lbu: no sign extension
lb: sign extension
Two's Complement Operations
71998 Morgan Kaufmann Publishers
• Unsigned numbers just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101 1101 0001 0001
• Two's complement operations easy
– subtraction using addition of opposite number
0111+ 1010
10001 (result is 0001, carry bit is set)
• Two's complement overflow (result not within number range)
– e.g., adding two 4-bit numbers does not yield an 4-bit number 0111+ 0011
1010 (result is - 6, overflow bit is set)
Addition & Subtraction
81998 Morgan Kaufmann Publishers
• No overflow when adding a positive and a negative number• No overflow when signs are the same for subtraction• Overflow occurs when the value affects the sign:
– overflow when adding two positives yields a negative – or, adding two negatives gives a positive– or, subtract a negative from a positive and get a negative– or, subtract a positive from a negative and get a positive
• Consider the operations A + B, and A – B– Can overflow occur if B is 0 ? No.– Can overflow occur if A is 0 ? Yes.
Detecting Overflow
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• An exception (interrupt) occurs– Control jumps to predefined address for exception– Interrupted address is saved for possible resumption
• Details based on software system / language– example: flight control vs. homework assignment
• Don't always want to detect overflow— new MIPS instructions: addu, addiu, subu
note: addiu still sign-extends!note: sltu, sltiu for unsigned comparisons
Effects of Overflow
101998 Morgan Kaufmann Publishers
• and, andi: bit-by-bit AND• or, ori: bit-by-bit OR• sll: shift left logical• slr: shift right logical
• 0101 1010
shifting left two steps gives 0110 1000• 0110 1010
shifting right three bits gives 0000 1011
Logical Operations
111998 Morgan Kaufmann Publishers
• Let's build a logical unit to support the and and or instructions– we'll just build a 1 bit unit, and use 32 of them– op=0: and; op=1: or
• Possible Implementation (sum-of-products):
result = a • b + a • op + b • op
b
a
operation
result
Logical unit
op a b res0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1
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• Selects one of the inputs to be the output, based on a control input
IEC symbol
of a 4-input
MUX:
• Lets build our logical unit using a MUX:
S
CA
B0
1
Review: The Multiplexor
0
1b
a
Operation
Result
MUX
0
1
0123
G03_
EN
131998 Morgan Kaufmann Publishers
• Not easy to decide the “best” way to build something– Don't want too many inputs to a single gate– Don’t want to have to go through too many gates– For our purposes, ease of comprehension is important– We use multiplexors
• Let's look at a 1-bit ALU for addition:
• How could we build a 32-bit
ALU for AND, OR and ADD?
Different Implementations
cout = a b + a cin + b cin
sum = a b cin
Sum
CarryIn
CarryOut
a
b
a b cin cout sum
0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
141998 Morgan Kaufmann Publishers
Building a 32 bit ALU for AND, OR and ADD
b
0
2
Result
Operation
a
1
CarryIn
CarryOut
Result31a31
b31
Result0
CarryIn
a0
b0
Result1a1
b1
Result2a2
b2
Operation
ALU0
CarryIn
CarryOut
ALU1
CarryIn
CarryOut
ALU2
CarryIn
CarryOut
ALU31
CarryIn
We need a 4-input MUX.
1-bit ALU:
151998 Morgan Kaufmann Publishers
• Two's complement approach: just negate b and add.
• A clever solution:
• In a multiple bit ALU the least significant CarryIn has to be equal to 1 for subtraction.
What about subtraction (a – b) ?
0
2
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b
161998 Morgan Kaufmann Publishers
• Need to support the set-on-less-than instruction (slt)
– remember: slt is an arithmetic instruction
– produces a 1 if rs < rt and 0 otherwise
– use subtraction: (a-b) < 0 implies a < b
• Need to support test for equality (beq $t5, $t6, $t7)
– use subtraction: (a-b) = 0 implies a = b
Tailoring the ALU to the MIPS
Supporting slt
• Other ALUs:
• Most significant ALU:
0
3
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b 2
Less
0
3
Result
Operation
a
1
CarryIn
0
1
Binvert
b 2
Less
Set
Overflowdetection
Overflow
a.
b.
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Seta31
0
ALU0 Result0
CarryIn
a0
Result1a1
0
Result2a2
0
Operation
b31
b0
b1
b2
Result31
Overflow
Binvert
CarryIn
Less
CarryIn
CarryOut
ALU1Less
CarryIn
CarryOut
ALU2Less
CarryIn
CarryOut
ALU31Less
CarryIn
32 bit ALU supporting slt
a<b a-b<0, thusSet is the sign bitof the result.
191998 Morgan Kaufmann Publishers
Final ALU including test for equality
• Notice control lines:
000 = and001 = or010 = add110 = subtract111 = slt
•Note: Zero is a 1 when
the result is zero!
Seta31
0
Result0a0
Result1a1
0
Result2a2
0
Operation
b31
b0
b1
b2
Result31
Overflow
Bnegate
Zero
ALU0Less
CarryIn
CarryOut
ALU1Less
CarryIn
CarryOut
ALU2Less
CarryIn
CarryOut
ALU31Less
CarryIn
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Conclusion
• We can build an ALU to support the MIPS instruction set
– key idea: use a multiplexor to select the output we want
– we can efficiently perform subtraction using two’s complement
– we can replicate a 1-bit ALU to produce a 32-bit ALU
• Important points about hardware
– all of the gates are always working
– the speed of a gate is affected by the number of inputs to the gate
– the speed of a circuit is affected by the number of gates in series(on the “critical path” or the “deepest level of logic”)
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Conclusion
• Our primary focus: comprehension, however,– clever changes to organization can improve performance
(similar to using better algorithms in software)– we’ll look at examples for addition, multiplication and
division
221998 Morgan Kaufmann Publishers
• A 32-bit ALU is much slower than a 1-bit ALU.• There are more than one way to do addition.
– the two extremes: ripple carry and sum-of-products
Can you see the ripple? How could you get rid of it?
c1 = b0c0 + a0c0 + a0b0
c2 = b1c1 + a1c1 + a1b1 c2 = c2(a0,b0,c0,a1,b1)
c3 = b2c2 + a2c2 + a2b2 c3 = c3(a0,b0,c0,a1,b1,a2,b2)
c4 = b3c3 + a3c3 + a3b3 c4 = c4(a0,b0,c0,a1,b1,a2,b2,a3,b3)
Not feasible! Too many inputs to the gates.
Problem: ripple carry adder is slow
231998 Morgan Kaufmann Publishers
• An approach in-between the two extremes• Motivation:
– If we didn't know the value of carry-in, what could we do?
– When would we always generate a carry? gi = ai bi
– When would we propagate the carry? pi = ai + bi
– Look at the truth table!
• Did we get rid of the ripple?c1 = g0 + p0c0
c2 = g1 + p1c1 c2 = g1+p1g0+p1p0c0
c3 = g2 + p2c2 c3 = g2+p2g1+p2p1g0+p2p1p0c0
c4 = g3 + p3c3 c4 = ...
Feasible! A smaller number of inputs to the gates.
Carry-lookahead adder
241998 Morgan Kaufmann Publishers
• Can’t build a 16 bit CLA adder (too big)
• Could use ripple carry of 4-bit CLA adders
• Better: use the CLA principle again!
Principle shown in the figure. See textbook for details.
Use principle to build bigger adders
CarryIn
Result0--3
ALU0
CarryIn
Result4--7
ALU1
CarryIn
Result8--11
ALU2
CarryIn
CarryOut
Result12--15
ALU3
CarryIn
C1
C2
C3
C4
P0G0
P1G1
P2G2
P3G3
pigi
pi + 1gi + 1
ci + 1
ci + 2
ci + 3
ci + 4
pi + 2gi + 2
pi + 3gi + 3
a0b0a1b1a2b2a3b3
a4b4a5b5a6b6a7b7
a8b8a9b9
a10b10a11b11
a12b12a13b13a14b14a15b15
Carry-lookahead unit
251998 Morgan Kaufmann Publishers
• More complicated than addition– can be accomplished via shifting and addition
• More time and more area• Let's look at 2 versions based on grammar school algorithm
0010 (multiplicand) x_1011 (multiplier) 0010 0010
0000 0010___ 0010110
• Negative numbers:
– easy way: convert to positive and multiply– there are better techniques
Multiplication
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Multiplication, First Version
Done
1. TestMultiplier0
1a. Add multiplicand to product andplace the result in Product register
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
Start
Multiplier0 = 0Multiplier0 = 1
No: < 32 repetitions
Yes: 32 repetitions
64-bit ALU
Control test
MultiplierShift right
ProductWrite
MultiplicandShift left
64 bits
64 bits
32 bits
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Multiplication, Final Version
ControltestWrite
32 bits
64 bits
Shift rightProduct
Multiplicand
32-bit ALU
Done
1. TestProduct0
1a. Add multiplicand to the left half ofthe product and place the result inthe left half of the Product register
2. Shift the Product register right 1 bit
32nd repetition?
Start
Product0 = 0Product0 = 1
No: < 32 repetitions
Yes: 32 repetitions
281998 Morgan Kaufmann Publishers
Booth’s Algorithm
• The grammar school method was implemented using addition and shifting
• Booth’s algorithm also uses subtraction• Based on two bits of the multiplier either add, subtract or do
nothing; always shift• Handles two’s complement numbers
291998 Morgan Kaufmann Publishers
Fast multipliers
• Combinational implementations– Conventional multiplier algorithm
• partial products with AND gates• adders
– Lots of modifications
• Sequential implementations– Pipelined multiplier
• registers between levels of logic• result delayed• effective speed of multiple multiplications increased
301998 Morgan Kaufmann Publishers
Four-Bit Binary Multiplication
Multiplicand B3 B2 B1 B0
Multiplier A3 A2 A1 A0
1st partial product A0B3 A0B2 A0B1 A0B0
2nd partial product A1B3 A1B2 A1B1 A1B0
3rd partial product A2B3 A2B2 A2B1 A2B0
4th partial product + A3B3 A3B2 A3B1 A3B0
Final product P7 P6 P5 P4 P3 P2 P1 P0
311998 Morgan Kaufmann Publishers
Classical Implementation
P7:0
PP1
PP2
PP3
PP4
&
&
&
&
A0B0A0B1A0B2A0B3
4/
4/
4/
4/
6/
6/
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Pipelined Multiplier
Clk
/ /
/
/
/
/
/
/
/
/
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Division
• Simple method:– Initialise the remainder with the dividend– Start from most significant end– Subtract divisor from the remainder if possible (quotient
bit 1)– Shift divisor to the right and repeat
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Division, First Version
64-bit ALU
Control
test
Quotient
Shift left
Remainder
Write
Divisor
Shift right
64 bits
64 bits
32 bits
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Division, Final Version
Same hardware formultiply and divide.
Write
32 bits
64 bits
Shift leftShift right
Remainder
32-bit ALU
Divisor
Controltest
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Floating Point (a brief look)
• We need a way to represent
– numbers with fractions, e.g., 3.1416
– very small numbers, e.g., .000000001
– very large numbers, e.g., 3.15576 109
• Representation:
– sign, exponent, significand:
(–1)sign significand 2exponent
– more bits for significand gives more accuracy
– more bits for exponent increases range
• IEEE 754 floating point standard:
– single precision: 8 bit exponent, 23 bit significand
– double precision: 11 bit exponent, 52 bit significand
371998 Morgan Kaufmann Publishers
IEEE 754 floating-point standard
• Leading “1” bit of significand is implicit
• Exponent is “biased” to make sorting easier
– all 0s is smallest exponent all 1s is largest
– bias of 127 for single precision and 1023 for double precision
– summary: (–1)sign significand) 2exponent – bias
• Example:
– decimal: -.75 = -3/4 = -3/22
– binary: -.11 = -1.1 x 2-1
– floating point: exponent = 126 = 01111110
– IEEE single precision: 10111111010000000000000000000000
381998 Morgan Kaufmann Publishers
Floating-point addition
1. Shift the significand of the number with the lesser exponent right until the exponents match
2. Add the significands
3. Normalise the sum, checking for overflow or underflow
4. Round the sum
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Floating-point addition
401998 Morgan Kaufmann Publishers
Floating-point multiplication
1. Add the exponents
2. Multiply the significands
3. Normalise the product, checking for overflow or underflow
4. Round the product
5. Find out the sign of the product
411998 Morgan Kaufmann Publishers
Floating Point Complexities
• Operations are somewhat more complicated (see text)
• In addition to overflow we can have “underflow”
• Accuracy can be a big problem
– IEEE 754 keeps two extra bits during intermediate calculations,
guard and round
– four rounding modes
– positive divided by zero yields “infinity”
– zero divide by zero yields “not a number”
– other complexities• Implementing the standard can be tricky
421998 Morgan Kaufmann Publishers
Chapter Four Summary
• Computer arithmetic is constrained by limited precision• Bit patterns have no inherent meaning but standards do exist
– two’s complement– IEEE 754 floating point
• Computer instructions determine “meaning” of the bit patterns• Performance and accuracy are important so there are many
complexities in real machines (i.e., algorithms and implementation).
• We are ready to move on (and implement the processor)
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