1 detailed design review hybrid audio dynamics processor team lead: william sender jeffrey auclair...

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Detailed Design ReviewHybrid Audio Dynamics Processor

Team Lead: William SenderJeffrey AuclairBryan Beatrez Michael Ferry

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Agenda● Problem Definition

○ Problem Statement○ Customer Requirements○ Engineering Requirements

● System Design○ Functional Decomposition○ System Architecture

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Agenda● Detailed Design

○ Embedded Design○ Hardware Design○ Software Design○ Auto-Mode○ BOM○ Risk Assessment

● MSD II Plan

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Section One

Problem Definition

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Problem Statement• Audio amplitude control for motion picture shows.• Maintain the quality and dynamics of the sound.• Improve flexibility while maintaining audio quality.• Maintain usability that of previous devices.

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Customer Requirements

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Engineering Requirements

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Section Two

System Design

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Functional Decomposition

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System Architecture

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Section Three

Detailed Design

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Embedded DesignLQFP1000

Block Net Pin Number Pin Name Pin TypeI/O Struct. Alternative Functions Additional Functions

ADC Audio In 1 23 PA0 I/O TTa

USART2_CTS,TIM2_CH1_ETRTIM8_BKIN,TIM8_ETR,TSC_G1_IO1,COMP1_OUT, EVENTOUT

ADC1_IN1, COMP1_INM,RTC_ TAMP2, WKUP1,COMP7_INP

ADC Audio In 2 24 PA1 I/O TTa

USART2_RTS, TIM2_CH2,TSC_G1_IO2, TIM15_CH1N,RTC_REFIN, EVENTOUT

ADC1_IN2, COMP1_INP,OPAMP1_VINP, OPAMP3_VINP

ADC GND 20 VSSA/VREF- S - Analog Ground/Negative Reference Voltage

ADC 3V3 21 VREF+ S - Postitive Reference Voltage

ADC 3V3 22 VDDA S - Analog Power Supply

Bypass Relay_1 1 PE2 I/O FTTRACECK, TIM3_CH1,TSC_G7_IO1, EVENTOUT -

Bypass Relay_2 2 PE3 I/O FTTRACED0, TIM3_CH2,TSC_G7_IO2, EVENTOUT -

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Embedded Design

Block Net Pin Number Pin Name Pin TypeI/O Struct. Alternative Functions Additional Functions

Rotary & Back A~C 38 PE7 I/O TTa TIM1_ETR, EVENTOUT ADC3_IN13, COMP4_INP

Rotary & Back B~C 39 PE8 I/O TTa TIM1_CH1N, EVENTOUT COMP4_INM, ADC34_IN6

Rotary & Back PB 40 PE9 I/O TTa TIM1_CH1, EVENTOUT ADC3_IN2

Rotary & Back BB 41 PE10 I/O TTa TIM1_CH2N, EVENTOUT ADC3_IN14

Display I2C_D 76 PA14 I/O FTf

I2C1_SDA, USART2_TX, TIM8_CH2,TIM1_BKIN, TSC_G4_IO4, SWCLK-JTCK, EVENTOUT

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Display I2C_C 77 PA15 I/O FTf

I2C1_SCL, SPI1_NSS, SPI3_NSS, I2S3_WS, JTDI, USART2_RX, TIM1_BKIN, TIM2_CH1_ETR, TIM8_CH1, EVENTOUT

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Embedded DesignBlock Net Pin Num. Pin Name Pin Type I/O Struct. Alternative Functions Additional Functions

DAC CH1_CV 29 PA4 I/O TTaSPI1_NSS, SPI3_NSS, I2S3_WS, USART2_CK, TSC_G2_IO1, TIM3_CH2, EVENTOUT

ADC2_IN1, DAC1_OUT1, OPAMP4_VINP, COMP1_INM, COMP2_INM, COMP3_INMCOMP4_INM, COMP5_INMCOMP6_INM,COMP7_INM

DAC CH2_CV 30 PA5 I/O TTaSPI1_SCK, TIM2_CH1_ETR, TSC_G2_IO2, EVENTOUT

ADC2_IN2, DAC1_OUT2, OPAMP1_VINP, OPAMP2_VINM, OPAMP3_VINP COMP1_INM, COMP2_INM, COMP3_INMCOMP4_INM, COMP7_INMCOMP5_INMCOMP6_INM,

PWMCH1_MUG 71 PA12 I/O FT

USART1_RTS, USB_DP, CAN_TX, TIM1_CH2N, TIM1_ETR, TIM4_CH2, TIM16_CH1, COMP2_OUT, EVENTOUT

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PWMCH2_MUG 91 PB5 I/O FT

SPI3_MOSI, SPI1_MOSI, I2S3_SD, I2C1_SMBA, USART2_CK, TIM16_BKIN, TIM3_CH2, TIM8_CH3N, TIM17_CH1, EVENTOUT

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Embedded Design

Timer Use Counter Resolution

TIM6 DAC Trigger Generation 16-bit

TIM7 DAC Trigger Generation 16-bit

TIM16 Make Up Gain 1 PWM 16-bit

TIM17 Make Up Gain 2 PWM 16-bit

TIM1 Attack/Release Timer 32-bit

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Embedded Design (Clk Tree)

- External Crystal 24 Mhz- System Clock 72 Mhz- Make-up gain timers: Tim 16,17 (16-bit)- DAC timers: 6, 7 (16-bit)- Attack and release timer: Tim 1 (32-bit)- 12-bit SAR ADC: ADC1_IN1, ADC1_IN2

- SYSclk divided by 64 results in the desired sample rate.

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Embedded DesignNet Pin Number Pin Name Pin Type I/O Struct Alternate Functions Additional Functions

3V3 1 VBAT S - Backup Power Supply

OSC 12PF0-OSC_IN I/O FTf TIM1_CH3N, I2C2_SDA OSC_IN

OSC 13PF1-OSC_OUT I/O FTf I2C2_SCL OSC_OUT

SW 14 NRST I/O RST Device reset input / internal reset output (active low)

3V3 28 VDD_4 S - - -

GND 49 VSS_2 S - Digital Ground

3V3 50 VDD_2 S - Digital Power Supply

GND 74 VSS_3 S - Ground

3V3 75 VDD_3 S - Digital Power Supply

SW 94 BOOT0 I B Boot Memory Selection

GND 99 VSS_1 S - Ground

3V3 100 VDD_1 S - Digital Power Supply

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Hardware

● Current calculations for power supply design

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Hardware

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Hardware

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Hardware

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Hardware

● Top Level Design

● Each block is a detailed subsystem

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Hardware

● Schematic for simulation

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Hardware

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Hardware

● Input Section● Takes balanced differential

audio input and creates debalanced signal

● Also provides BPF

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Hardware

● Precision Rectifier

● Allows rectification of signal while combating diode non-idealities (Forward drop, recovery time)

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Hardware

● Gain Control Section● Allows for signal to be

attenuated via CV- signal and gained up via CV+ signal.

● VCA is a current in/current out device that requires a transimpedance output section

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Hardware● Output Line Driver● Capable of driving

600 Ohm output with 6dB of gain

● Output DC common mode protect

● RFI protection and surge protection

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Hardware

● LPF Filter Design

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Hardware

● Anti-aliasing LPF● Provides

accurate sampled signal

● Chebyshev Design with 0.26dB ripple

● -3dB @ 20kHz● -40db @ 49kHz

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Hardware

● Monte-Carlo Analysis

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Hardware

● Microcontroller● It’s fast, which is cool● It likes having capacitors

nearby

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Hardware

● Takes 3.3V signals from the microcontroller and converts them to 5V.

● Same in either direction.

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Hardware

● Relays provide true bypass● Diode protected

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Software Top-Level

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Software Main Function

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Software chooseCompress (Attack)

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Software chooseCompress (Release)

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Software Compression

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Software AutoMode Params

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Software Pseudo Code

Break from powerpoint to show pseudo code

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Auto ModeAuto mode block diagram:

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Auto ModeSuccessive algorithm

-The active low enable refers to the idea that you would only need to improve your compression settings if gain reduction was occurring in the safety compression block.

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Auto ModeSafety Mode- When auto mode is initialized this all the signal conditioning that occurs.

- Safety mode is a limiter to the incoming signal, +3dbu threshold 20:1 ratio.

- It also helps balance the system by feeding back compression data.

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Auto Mode (Improved Compression Settings)

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Auto Mode (Improved Compression Settings) - The improved compression will be developed from the product of each

sample exceeding the safety compression threshold and how much it is exceeded by.

(Sample Value - Threshold) X (# of Samples Exceeding Threshold) = Offset

- This offset will be added to the index of an array containing improved compression settings.

- It is important to note that in the event the above product is very small the offset will slowly make the compression settings less aggressive in order to not over compress.

- the offset will also be scaled appropriately for the array of improved compression settings.

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Bill of MaterialsComponet Price Componet Price

Power Supply $40.97 Rectifier $6.00

Level Shift $0.940 VCA $16.92

MCU $16.82 Output Stage $26.10

Relays $9.78 LPF $6.04

Input Stage $3.24 Chasis $87.90

$214.71

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Bill of MaterialsBreak from powerpoint to show full Bill of Materials

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Risks

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Week 1

-Finish unfinished business from MSDI

-Get micro working with prototype board

Weeks 2-5

-Layout PCB

-Start prototyping code

-Populate PCBs

MSDII Plan

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Weeks 6-9

-Test software

-Test hardware

-Machine the enclosure

Weeks 10-15

-Qualitative Tests

-Create poster

-Iterate until satisfied

MSDII Plan

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Questions

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