1 ee365 sequential pld timing registers counters shift registers

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EE365

Sequential PLD timing

Registers

Counters

Shift registers

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Sequential PLD timing parameters

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Timing contd.

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Multibit registers and latches

• 74x175

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8-bit (octal) register

• 74x374– 3-state output

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Other octal registers• 74x273

– asynchronous clear– Non-three state output

• 74x377– clock enable– no tristate-buffer

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Octal latch

• 74x373– Output enable– Latch-enable input “C” or “G”

• Register vs. latch, what’s the difference?– Register: edge-triggered behavior– Latch: output follows input when G is asserted

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Counters

• Any sequential circuit whose state diagram is a single cycle.

RESETEN

EN

EN

EN EN

EN

EN

ENEN EN

ENENEN

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10

LSB

MSB

Synchronous counter

Serial enable logic

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LSB

MSB

Synchronous counter

Parallel enable logic

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74x163 MSI 4-bit counter

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74x163 internal

logic diagram

• XOR gates embody the “T” function

• Mux-like structure for loading

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Counter operation

• Free-running 16• Count if ENP and

ENT both asserted.• Load if LD is asserted

(overrides counting).• Clear if CLR is asserted (overrides loading

and counting).• All operations take place on rising CLK edge.• RCO is asserted if ENT is asserted and

Count = 15.

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Free-running 4-bit ’163 counter

• “divide-by-16” counter

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Modified counting sequence

• Load 0101 (5) after Count = 15• 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5, 6, …• “divide-by-11” counter

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Another way

• Clear after Count = 1010 (10)• 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2, 3, …• “modulo-11” or “divide-by-11” counter

trick to save gate inputs

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Counting from 3 to 12

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Cascading counters

• RCO (ripple carry out) is asserted in state 15, if ENT is asserted.

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Decoding binary-counter states

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Decoder waveforms

• Glitches may or may not be a concern.

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Glitch-free outputs

• Registered outputs delayed by one clock tick.• We’ll show another way to get the same

outputs later, using a shift register.

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Shift registers

• For handling serial data, such as RS-232 and modem transmission and reception, Ethernet links, etc.

• Serial-in, serial-out

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Serial-to-parallel conversion

• Use a serial-in, parallel-out shift register

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Parallel-to-serial conversion

• Use parallel-in, serial-out shift register

mux

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Do both

• Parallel-in, parallel-out shift register

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“Universal” shift register

74x194

• Shift left• Shift right• Load• Hold

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One stage of ’194

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Shift-register counters

• Ring counter

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Johnson counter

• “Twisted ring” counter

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LFSR counters• Pseudo-random number generator• 2n - 1 states before repeating• Same circuits used in CRC error checking in

Ethernet networks, etc.