4 november 2014 birkbeck college, u. london1 introduction to computer systems lecturer: steve...
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4 November 2014 Birkbeck College, U. London 1
Introduction to Computer Systems
Lecturer: Steve Maybank
Department of Computer Science and Information Systemssjmaybank@dcs.bbk.ac.uk
Autumn 2014
Week 6b: Types of Instruction
4 November 2014 Brookshear, Section 2.2 2
Machine Architecture
Address | Cells
00
01
.
.
FF
Arithmetic/logic unit
Registers
.
.
0
F
1 Program counter
Instruction register
Bus
Main memoryCentral processing unit
Controlunit
4 November 2014 Brookshear, Section 2.2 3
Machine Language Concepts
Registers (R, S, T…) Memory addresses Number of bytes in a memory cell Instruction Sequence of instructions Branching (choice of next
instruction)
Properties of the Illustrative Machine
No. memory cells: 256 No. bits in a memory cell: 8 (1 byte) No. registers: 16 No. bits in a register: 8 (1 byte) No. bits in the programme counter: 8 (1 byte) No. bits in the instruction register: 16 (2 bytes)
4 November 2014 Birkbeck College, U. London 4
4 November 2014 Brookshear, Appendix C 5
Illustrative Machine Language
Op-code
Operand
description
1 RXY LOAD R from memory location XY
2 RXY LOAD R with data XY
3 RXY STORE R at memory location XY
4 0RS Move bit pattern in R to S
5 RST Add (2s comp) contents of S,T. Put result in R
6 RST Add (fp) contents of S,T.Put result in R
4 November 2014 Brookshear, Appendix C 6
Illustrative Machine Language
Op-code
Operand
Description
7 RST OR contents of S, T. Put result in R
8 RST AND contents of S, T. Put result in R
9 RST XOR contents of S, T. Put result in R
A R0X Rotate right contents of R for X times.
B RXY If contents R=contents register 0, then jump to instruction at address XY, otherwise continue as normal.
C 000 Halt
4 November 2014 Brookshear, Section 2.2 7
Types of Instruction
Data transferLOAD, STORE, MOVE
Arithmetic/LogicADD, OR, AND, XOR, ROTATE
ControlJUMP, HALT
4 November 2014 Brookshear, Section 2.2 8
Format of an Instruction
Instruction=op-code field+operand field
Op-code: identifies the elementary operation, e.g. STORE, SHIFT, XOR, JUMP.
Operand: additional information, e.g. data or a register address.
4 November 2014 Brookshear, Section 2.3 9
Instruction 156C
1 5 6 C
Op-code 1: loadRegister with bitpattern in memoryat the givenaddress
registermemory address
4 November 2014 Brookshear, Section 2.3 10
Op Code 7 (OR)
1 0 0 1 1 1 0 1
0 0 0 1 0 1 1 1
1 0 0 1 1 1 1 1
1st register
2nd register
3rd register
OR
=
4 November 2014 Brookshear, Section 2.3 11
Op Code A (Rotate right)
1 0 0 1 1 1 0 1
1 1 0 0 1 1 1 0
0 1 1 0 0 1 1 1
register
rotate right 1
rotate right 2
4 November 2014 Brookshear, Section 2.3 12
Instruction B258
B 2 5 8
Op-code B: change valueof program counter ifcontents of indicatedregister = contents ofregister 0
Indicatedregister
New contentsof programcounter
Brookshear, Fig. 2.9.
Brookshear, Section 2.3 13
Machine Cycle
Fetch next instructionfrom memory to theCPU
Decode theinstruction
Execute theinstruction
4 November 2014
FetchDecodeExecute
4 November 2014 Brookshear, Section 2.3 14
First Part of the Fetch Step of the Machine Cycle
bus
CPU Main memory
program counter
A0
instruction register
156C
address cells
A0
A1
A2
A3
15
6C
16
6D
4 November 2014 Brookshear, Section 2.3 15
Completion of the Fetch Step
bus
CPU Main memory
program counter
A2
instruction register
156C
address cells
A0
A1
A2
A3
15
6C
16
6D
4 November 2014 Brookshear, Section 2.3 16
Updating the Program Counter
Fixed length instructions (2 bytes). Instructions stored consecutively in main
memory. Each memory cell holds 1 byte. Then pc pc + 2 at the end of each Fetch.
… 5 6 7 8 9 10 11 12 13 14 …
pc=7
memory
4 November 2014 Brookshear, Section 2.3 17
Program to Add Two Values
1. Get the first value from memory and place it in a register S.
2. Get the second value from memory and place it in another register T.
3. Add the contents of S, T and place the result in a register R.
4. Store the result in R in memory5. Stop
4 November 2014 Brookshear, Section 2.3 18
Encoded Program1. 156C. Load register 5 with the
contents of memory cell 6C.2. 166D. Load register 6 with the
contents of memory cell 6D3. 5056. Add (2s comp) contents of
registers 5, 6. Put result in register 0.4. 306E. Store the contents of Register 0
at memory cell 6E.5. C000. Halt.
4 November 2014 Birkbeck College, U. London 19
Without Instruction B
A program containing n instructions would run for n-1 machine cycles.
The program would be unable to respond to changes in the data.
4 November 2014 Birkbeck College, U. London 20
Fibonacci Numbers
0,1,1,2,3,5,8,13,21,34,55, …
N(1)=0, N(2)=1
N(i+1)=N(i)+N(i-1) for i=2,3,4, …
4 November 2014 Birkbeck College, U. London 21
Program to Find the 10th Fibonacci Number
20 2000 // load register 0 with 022 2100 // load register 1 with 024 2201 // load register 2 with 126 2408 // load register 4 with 828 25FF // load register 5 with -1 (Two’s Comp)
Address Instruction Comment
R0 R2 R3 R4R1 R5
00 08**0100 FF
4 November 2014 Birkbeck College, U. London 22
Program to Find the 10th Fibonacci Number
2A 5312 // Add contents of R1, R2. Put result in R33C 4021 // Move bit pattern in R2 to R12E 4032 // Move bit pattern in R3 to R230 5445 // Add contents of R4, R5. Put result in R432 B436 // If contents R4=contents R0, go to 3634 B02A // If contents R0=contents R0, go to 2A36 C000 // Halt. Result is in R2.
Address Instruction Comment
4 November 2014 Brookshear, Section 6.1 23
Assembly Language Mnemonic system for representing
machine language
Machine language
156C166D5056306EC000
Assembly language
LD R5, PriceLD R6, ShippingChargeADDI R0, R5, R6St R0, TotalCostHLT
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