a fully integrated 20 gb/s optoelectronic in a standard µm cmos
Post on 03-Feb-2022
2 Views
Preview:
TRANSCRIPT
A Fully Integrated 20‐Gb/s Optoelectronic Transceiver Implemented in a Standard
0.13‐µm CMOS SOI Technology
School of Electrical and Electronic EngineeringYonsei University
이슬아
1. Introduction2. Architecture3. System Building Blocks
A. Optical Components : Holographic Lens, Optical WaveguideB. Optoelectric Components : High‐Speed Mach‐Zehnder Modulator, Thermal
Phase Modulator, Variable Optical AttenuatorC. Electronic Components : Optical transmitter, Optical Receiver, Common Clock
and Data Recovery Circuit4. Experimental Results5. Conclusion
Introduction
<Conventional system>• Optical data transceivers operating at 10 Gb/s have
been implemented in CMOS→ but a low level of optoelectronic integration
• Conventional processes results in very high cost, dominated by the packaging and testing of different optical components.
<Conventional multi‐wavelength optical communication system>
• This paper focuses on an application of the same technology to creating highly‐integrated communication systems.
• It describes the architecture, key building blocks, implementation and testing of a dual‐channel, 10 Gb/s per channel, C‐band (1550 nm) optoelectronic transceiverintegrated in a SOI material system.
Architecture• Two parallel high‐speed optoelectronic
transceivers → 10 Gb/s• Transmit (TX) path : electrical input →
optical out put• TX equalizer : compensate for a moderate
amount of high‐frequency attenuation due to the electrical channel prior to the TX input
• Clock and data recovery (CDR) : retimed to remove jitter, create a clean, high‐amplitude signal
• Modulator driver (MD) : amplifies the signal to provide a high voltage
• Mach‐Zehnder Interferometer (MZI) : four‐port network Input : a continuous wave (CW) optical
signal with λ = 1.55 μm, and high‐speed electrical data
Output : modulated optical signal and its complement
<Dual‐channel 10 Gb/s per channel optoelectronic transceiver architecthure>
Architecture• The input and output of the MZI is coupled in
and out of the chip by holographic lens (HL).• HL : couple normally incident light in and out of
the silicon chip. → commercially available• High‐speed p‐i‐n photodetector (PD)• Transimpedance amplifier (TIA) and limiting
amplifier (LA) : amplify the received signal to levels that are compatible with the receive (RX) CDR circuit
• Variable optical attenuator (VOA) ‐ loopback Self‐testing of the complete
optoelectronic TX/RX chain Feasibility of this technology in the
implementation of intra‐chip interconnect• 16‐bit bus controller unit (BCU) : enables
design for testability (DFT) as a critical function for managing the complexity of an integrated optoelectronic system.
<Dual‐channel 10 Gb/s per channel optoelectronic transceiver architecthure>
System Building blocks – Optical components
• An optical waveguide together with a transistor in the active layer of the CMOS SOI photonic technology
• Co‐existence of electronic and photonic devices in the same silicon layer allows photonic and electronic functions.
<Conceptual cross section of a CMOS photonic technology >
<Holographic lens>
A. Optical Components1) Holographic Lens (HL)
• Overcome a severe mode mismatch and high insertion loss for simple edge or end‐fire coupling
• Trench periodicity : optical phase matching, scatter light from an normally incident optical fiber into the silicon wave guide
2) Optical Waveguide• It is etched into the active top silicon of SOI• 0.5 μm wide
System Building blocks – Optoelectronic components
B. Optoelectronic Components1) High‐Speed Mach‐Zehnder Modulator (Majority carrier Device)• To impose high‐speed electronic data on the
optical carrier wave• Electric field → change of carrier density →
phase shi → construc vely/destruc vely interfere
• Reverse‐biased diode →majority carriers to drift in and out of the optical mode : high‐speed
2) Thermal Phase Modulator, TPM (Thermo‐Optic Device)• To use as phase tuners• A resistor implanted in an op cal waveguide →
current flows → heat up the waveguide → index change → phase change
• 250 µm long, 10 µm wide
System Building blocks3) Variable Optical Attenuator (Minority Carrier Device)• To impart an electrically controlled
attenuation to an optical wave• 1 mm long, 1 μm wide• It consists of a lateral p‐i‐n diode
integrated into an optical waveguide• Forward‐biasing the diode causes carriers
to accumulate in the intrinsic region → carrier density change → op cal absorption coefficient change
• An optical attenuation of up to 40 dB may be induced with ~100 mA of applied current.
System Building blocks – Optoelectronic components
System Building blocks – Electronic Components
C. Electronic Components1) Optical Transmitter
• The optical transmitter consists of a modulator driver circuit connected to the MZI.• Optical modulating elements : reverse‐biased p‐n junction straddling a section of a waveguide• Dual termination : avoid inter‐symbol interference (ISI) in the optical output due to signal
reflections
Compensation of phase offset
Modulator driver
• Large voltage can severely stress the breakdown limits• M1 with a pair of M2 → to protect the switching transistors from over‐voltage conditions
Current‐modeLogic (CML)
4‐bit word
System Building blocks – Electronic Components
2) Optical Receiver• Consists of an external high‐speed p‐i‐n PD and a capacitance of 150fF that is connected to
a TIA and followed by a five‐stage limiting amplifier (LA).
Extending TIA bandwidth
Feedback resistance to isolate
High gain
To reduce nose and provide stabilized gain
Compares the received signal average power against a locally created reference
System Building blocks – Electronic Components
3) Common Clock and Data Recovery Circuit• Consists of a data recovery loop and a frequency acquisition loop
Intrinsic data retiming
phase‐locked loop (PLL)
Experimental Results
<Chip microphotograph> <Packaged dual‐channel transceiver system>
• System chip with the two parallel 10‐Gb/s channels
• Die : 8mm x 5.6mm• 17mm x 20 mm x 4 mm
package• Aggregate data rate : 20
Gb/s• Total power : 2.5 W
• A typical extinction ratio of 5‐6 dB is achieved at the output of the TX with rise and fall times of 28 ps.
<Single‐ended XFI compatible RX output eye diagram>
<TX optical output eye diagram>
Experimental Results
• Data rate : 10.3125 Gb/s, receiver sensitivity of ‐19.5 dBm for a BER of 10‐12, receiver overload level : 0 dBm, dynamic range of almost 20 dB, transmitter electrical input sensitivity : 25 mVpp
• CDR jitter tolerance : relative to the 802.3ae specification• CDR jitter transfer bandwidth : 7 MHz, less than 1 dB of jitter peaking
<BER versus optical power at the PD> <Receive CDR jitter tolerance> <Receive CDR jitter transfer>
Conclusion• A complete 20‐Gb/s optical transceiver system has been
demonstrated, integrating key optical and electrical components on a single substrate using a 0.13‐µm CMOS SOI process.
• Advantage : reduced size, power consumption, and package integration complexity
Thank you for listening!
top related