a robust circuit-based sat solver for complex circuit...

QuteSatA Robust Circuit-Based SAT Solver

for Complex Circuit StructureChung-Yang (Ric) Huang

National Taiwan University

To appear: DATE 200702/10/2007

02/10/07 Chung-Yang (Ric) Huang ric@cc.ee.ntu.edu.tw +886-2-3366-3644

Fact Sheet (Background)Boolean Satisfiability (SAT)

Given a Boolean networkF: Bn B,

find an input assignment A: { x1 = a1, x2 = a2,... , xn = an | ai ∈ B }

such that F = 1.First proven NP complete problem (Cook 1971)

Well researched problems in AI, OR, EDA...Widely used in many EDA areas

Verification, Testing, Logic optimization, Physical implementation, etc

Yet Another SAT engine?Yaya, but with two missions...

1. Generalized for general constraint satisfiability and optimization problems

2. Specialized for EDA specific applications

GraspTegus

zChaff MiniSat

NimoSATO

Nemesis

Large vs. Little EnginesMuch of the focus in automated deduction has been on finding uniform procedures for large classes of theorems

For example, the resolution method is a simple, sound and complete inference procedure for first-order logicResolution-based methods have had signicant successes solving open problems in diverse branches of mathematics

However, big engines are not always predictable enough for serious applications --- they do a poor job of “exploiting domain knowledge”

The little engines ideology is based on composing small theory-specific engines.

“Little Engines of Proof”, Lec Notes, Dr. Shankar, SRI et. al.

Examples of Little EnginesPropositional satisability solversBinary Decision DiagramsCongruence Closure for Equality PropagationReal and Integer linear arithmetic solversDecision procedures for lists, arrays, bit-vectors.Presburger arithmeticMonadic Second Order Logic

“Little Engines of Proof”, Lec Notes, Dr. Shankar, SRI et. al.

Large vs. Little Engines

Little Engines

Tuned for specific

problems

Uniformity of data structure and interface

Large Engines

QuteSattarget

Sharing between engines

Flexibility for new algorithms

What to expect in this talk...

Background: Fact sheet, large vs. little enginesReview: CNF-based SAT

2-literal watch for Boolean Constraint Propagation (BCP)Antecedent clause for efficient conflict-driven learning

Proposed: QuteSat (Circuit SAT)Generic watch schemeImplicit implication graph

Experimental resultsFuture work

Conjunctive Normal Form (CNF) SATMost modern Boolean SAT solvers are in CNF

Product of sum (PoS) format

1. Efficient Boolean Constraint Propagation (BCP)2. Conflict-driven learning with non-chronological

backtracking3. Decision variable heuristics4. Clause database reduction

The simpler, the better.

(a+b+c)(a’+b’+c)(a’+b+c’)(a+b’+c’)

Variables Literals Clauses

From CNF to Circuit SATHowever, most of the EDA problems are not naturally in CNF format

Operators (∧∨¬⊕±×≥...) ∧(¬∨)Loss of implicability

Structural info (direction, locality,...) N/ACan we implement SAT on circuit structure?(This is not new e.g. ATPG)

Pros: flexibility, structural infoCons: complex implementation, slower BCP

BCP in CNF SATBoolean implication

e.g. (a1 = 1) && (a2 = 0) && ... (an-1 = 1) (an = 1)

BCP algorithms1. while (ai gets a value), check if only one ‘x’ is left

2. Count num of ‘x’O(n), but overhead in maintaining ‘x’ count

3. Watch 2 literals in a clause. Only when watched literal changes, then we check the clause

Amortized O(C)

(a1 + a2 + ... + an-1 + an)

value: x 0 x 1

Can circuit SAT do 2-watch?

Watch 2 fanins?What’s the watch value?How about gate output?How about OR, NOR, NAND,.. gates?How about XOR, MUX, ... complex gates?

111Forward Backward

omni-directional implications

A Closer Look

1 1 1 1 1 1

( ai + f ) ( a1 + a2 + ... + an + f )

Different implications on circuit-based SAT actually map to the same implication on CNF SAT

Direct vs. Indirect Implications

1. Direct implicationCorresponding n 2-literal clauses in CNF SATSingle implication source

No need to watch

Direct Implication

1. Single source for each implication2. Only depends on netlist structure; has

nothing to do with the proving process (e.g. decisions, etc)

3. Should never encounter “CONFLICT”during the proof process

Direct Implication

_0DirImps: { b, ... }_1DirImps: { ... } _0DirImps: { ... }

_1DirImps: { a, c, ... }

Construct a “direct implication graph” in the preprocessing step

Apply direct implications whenever a gate is implied to a value

_0DirImps: { b, ... }_1DirImps: { ... }

Direct vs. Indirect Implications

1. Direct implicationCorresponding n 2-literal clauses in CNF SATSingle implication source

No need to watch2. Indirect implication

Corresponding to the same (n+1)-literal clauseOnly the last implied pin has different value

2 watches: among all fanins and the gate itself

11 1 11 1

Indirect Implication (AND gate)

Select 2 pins (fanins or the gate itself) in a gate to watch

Almost the same as CNF SATFor each gate, a list of watching gates

When a gate gets a value, perform direct implication and/or update watch for the gates on the watching list

watching-0: { a }watching-1: { }

watching-0: { }watching-1: { a, b }

watching-0: { }watching-1: { }

watched pins

Watch Scheme for XOR Gaten-input XOR gate

2n (n+1)-literal clausese.g. (a + b + f) (a + b + f) (a + b + f) (a + b + f)

Implication occurs only when n variables become “known”2-watch; watch-known

watching-0: { a }watching-1: { }watching-known: { }

watching-0: { }watching-1: { b }watching-known: { a }

watching-0: { }watching-1: { }watching-known: { }

Watch Scheme for MUX Gate

2-watch; watch-known?No. If watching { f, s }, when { a=1, b=1 }, we miss the implication { f=1 }

3-watch; watch known!!Compared: CNF (6 clauses; 12 watch literals)

(¬f + a + b)(f + ¬a + ¬b)(a = b) (f = a)

(¬s + f + ¬b)(¬s + ¬f + b)s (f = b)

(s + f + ¬a)(s + ¬f + a)¬s (f = a)

CNF clausesImplication

MUX function: f = ¬s ∧ a + s ∧ b

Watch Scheme for PB GatesPB Constraint:

C0p0 + C1p1 + ... + Cn-1p1 ≥ Cn , where Ci ∈ Z+, pi∈Be.g. 4x1 + 3x2 + 2x3 + x4 >= 3

How many watches?2-watch? All-watch?Note:min #watches depends on the value assignmentsDynamic #watches? Too complicated....

Our approach∀ combinations of assignments triggering implications

max (min (#watches) )

Generic Watch Scheme1. Watch candidate set

Output and input pins of the gate2. Watched value ‘v’ for each pin

If ‘v’ on this pin may eventually lead to an indirect implication on other pin(s), then ‘v’ is the watched value of this pin

3. Find a minimum subset of watched candidates(a) Assigning watched values on all the variables of the subset will

produce an indirect implication (b) Removing any of these assignments will void the implication

Let ‘k’ be the size of this subset.

4. We will need (n – k + 1) watched pointers.

Generic Watch Scheme

5. Update of the watched pointerCalled only when there is a watched-value assignment on the watched pinOther cases:

Whenever there are assignments on the non-watched pinsNon-watched value assignments on the watched pinsDo nothing

CNF vs. Circuit SAT

Conflict Analysis

Branch on a Variable

conflict

No Sol.∅

learnedOK

Sol. Found

all variables assigned

successful

CNF SAT Circuit SAT

2-literal watch scheme

Topological scheduling

Antecedent ptr+ UIP cut

Imp Graph + UIP cut

Influence-guided + restart

Influence & structure-guided

+ restart

CNF vs. Circuit SAT

Conflict Analysis

conflict

No Sol.∅

learnedOK

Sol. Found

successful

Generic watch scheme

Imp Graph + UIP cut

Circuit SAT

+ restart

CNF SAT

Conflict-Driven Learning

(a + c + d)

(a + c + d’)(a + c’ + d)

(a + c’ + d’)

(a’ + b + c)

(b’ + c’ + d)(a’ + b + c’)

(a’ + b’ + c)

Conflict!d=1

(a + c + d)a=0

d=0(a + c + d’)

Implication Graph

Conflict source

(a + c) Learned clause

⇐ Backtrack

Conflict-Driven Learning

Does CNF SAT record the imp graph?No!!

Clauses:(a’+b+c)(a+c+d)(a+c+d’)(a+c’+d)(a+c’+d’)(b’+c’+d)(a’+b+c’)(a’+b’+c)

(a + c + d)a=0

variables: a b c d

antecedent clause

Can circuit SAT do “antecedent gate”?

GateClause

Gate + valueLiteral

GateVariable

Circuit SATCNF SAT

Who “is” g’s antecedent gate?

Implicit Implication GraphIf the implication type is “DIRECT”, then the antecedent pointer is the single implication source.If the implication type is “INDIRECT”, then the implication sources are the watched candidates of the antecedent gate that are

(a) non-watched variables, and (b) watched variables with watched values, excluding

the implied pin.

Implicit Implication Graph Example

Imp type: DIRECTAntecedent: f

impSrc: { f }

Imp type: INDIRECTAntecedent: f

impSrc: { f, a, b}

Implicit Implication Graph Example

PB gate C: 4x1 + 3x2 + 2x3 + x4 >= 3Implication order: { x1 = 0, x2 = 0 }

Watched pins: { x2, x3, x4 }

Indirect implications: “x3 = 1”, “x4 = 1”

Imp type: INDIRECTAntecedent: C

impSrc: { x1, x2 }

x3 Imp type: INDIRECTAntecedent: C

impSrc: { x1, x2 }

CNF vs. Circuit SAT

Conflict Analysis

conflict

No Sol.∅

learnedOK

Sol. Found

successful

Generic watch scheme

Implicit Imp Graph

+ UIP cut

Circuit SAT

+ restart

CNF SAT

Experimental Results

N/RN/R1.392.691.69ave rank

2.1776.63185>3600>3600B20

14.454.4666>3600737B17

2.3715.983.0168.8116B15

0.7820.833.948.4629.8S38584

0.453.1430.985.5936.2S38417

0.160.6721.529.2425.4S35932

0.050.3922.57.553.71C7552

0.010.386.497.208.36C3540

NIMOQuteSAT -JminiSatzChaffQuteSAT

with circuit infowithout circuit infoTime:seconds

Table 1. Equivalence checking (EC) experiments

Our Contributions

1. A generic watch scheme that can seamlessly work on all kinds of circuit gates (simple or complex gates)

2. An implicit implication graph that enables efficient conflict-driven learning

3. Careful engineering work to implement most of the advanced SAT algorithm on the circuit data structure

Future WorkMore experiments!! Make sure the robustness of our engine for Boolean SATMission is not yet completed...

1. Generalized for general constraint satisfiability and optimization problems

2. Specialized for EDA specific applications

(PB, ILP, SMT, ...)

a robust circuit-based sat solver for complex circuit...

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