ab c f gates are combined into circuits by using the output of one gate as the input for another....
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An Introduction to
Latches and Flip-FlopsCompiled by
Putta Satish
Combinational Logic Circuits
A
B
C
f
Gates are combined into circuits by using the output of one gate as the input for another.So, in these circuits the output depends only on the combination of the inputs.
Logic Circuits as memory units
Digital Circuits can also be as memory units. So, in these circuits the output depends on the past state of the inputs and outputs. These type of circuits are called as sequential circuits.
Combinational Vs Sequential
Output depends only on
inputs.
Doesn’t possess any memory
elements.
There will be no feedback from
the output to input.
easier to design & faster in
operation.
Eg: MUX, DEMUX, ADDERS,
ENCODERS & DECODERS
Output depends on both input
and past state outputs.
Possess memory elements.
Involves some kind of feedback.
lots of complexity involves in the
design and slower in operation.
Eg : Flipflops, latches, registers,
counters etc..
A Y = Ᾱ
A Y = Ᾱ0 11 0
Ǫ
Ǭ
1100
1
At the time of power ON condition, Let us assume the node Q is logic 1
Ǫ
Ǭ
0011
0
Qn Qn+1
01
01
This indicates that the cascade connection of 2 inverters with a feedback is capable of retaining the past information (i.e., capable of storing the past information). And hence it can be considered as a memory element. But, there is no input port and hence we don’t have the control over the data to be stored.
A B Y
000
11 01 1
1000 If A = 0, then Y = B’.
This states that if one of the input to NOR gate is grounded, then that NOR gate will act as a NOT gate.
Ǫ
Ǭ
Ǫ
Ǭ
Ǫ
Ǭ
But, even with modification, there is no input port and hence we don’t have the control over the data to be stored i.e., we don’t have the control over the output.
Ǫ
Ǭ
R – S LATCH
R
S
A B Y
000
11 01 1
1000
If one of the input is Logic 0, the output will be complement of second input.
If one of the input is logic 1, then the output will be logic 0 irrespective of the second input.
Ǫ
Ǭ
R
S
Behaviour of R-S Latch
R S Ǫ Ǭ
10
0
1
00
101
Ǫ
Ǭ
R
S
Behaviour of R-S Latch
R S Ǫ Ǭ
10
0
0
00
101
00 01
11
Ǫ
Ǭ
R
S
R S Ǫ Ǭ
10
1
0
0100 0101 10
0
1
0
Behaviour of R-S Latch
Ǫ
Ǭ
R
S
R S Ǫ Ǭ
10
0
0
0100 0101 10
0
1
0
00 101
Behaviour of R-S Latch
Ǫ
Ǭ
R
S
R S Ǫ Ǭ
10
1
1
0100 0101 10
0
00 1011 Invalid
0
0
0
Ǫ
Ǭ
1
1
1
1
00
11
0
0
00
Behaviour of R-S Latch
0Ǫ
Ǭ
R
S
0
0
Ǫ
Ǭ
1
1
00
11
0
0
00
0
1
1
11
00
R S Ǫ Ǭ
10 0100 0101 1000 1011 Invalid
00 Race
Behaviour of R-S Latch
Though the input is stable, both 0 and 1 will race with each other at the output.
R S Ǫ Ǭ State
10 0100 0101 1000 1011 Invalid
00 Race
SET
No Change
RESET
No Change
INVALID
RACE
Timing Diagram of R-S Latch
Ǫ
Ǭ
S’
R’
S’ R’ Ǫ Ǭ State
10 0111 0101 1011 1000 Invalid
11 Race
SET
No Change
RESET
No Change
INVALID
RACE
So, it can be concluded that a 2gate NAND latch can be considered as an ACTIVE LOW latch.
R-S Latch using NAND gates
S’ R’ Ǫ Ǭ State
10 0111 0101 1011 1000 Invalid
11 Race
SET
No Change
RESET
No Change
INVALID
RACE
Controlled R-S LatchS’
R’C S R S’ R’ Ǫ Ǭ State
11 --11 --01 1010 01
No Change
RESET
SET
X0 X01 001 111 0
No Change
00 11 Invalid11 1
Excitation Table of R-S Latch
C Qn S R Ǫn+1 State
xx 0
00 0
10 010 0
No Change
RESET
0 0
1 0
1 01 1
No Change
11 x Invalid1 0
xx 10 1 No Change
00 1 No Change1 1
RESET
01 101 1
SET1 01 1 SET
Invalid11 x1 1
Excitation Table of R-S Latch
Qn S R Ǫn+1
00 0
10 010 0
0
01
11 x0
00 11
01 101 1
01
11 x1
0 1 3 2
4 5 7 6
Qn’
Qn
S’R’ S’R SR SR’
11
x1x
QN+1 = S + R’QN Characteristic Equation
State Diagram of R-S Latch
0 1
SR
0 0, 0 1 0 0, 1 01 0
0 1
Overview Latch is a memory element which is capable of storing one bit (either 0 or 1). A Latch contains two output lines which are always complement to ach other. A NOR latch is an ACTIVE HIGH latch. A NAND latch is an ACTIVE LOW latch. In order to enable or disable any latch to accept the input data, control signal line can be used to convert latches into controlled latches. A controlled NAND latch is active high latch. Generally, invalid state or RACE condition occurs in latches for certain pattern of inputs which are undesired and must be eliminated.
D - Latch To eliminate the invalid and race conditions (occurs when the inputs are either ‘00’ and ‘11’), both the inputs must of RS latch must be compliment to each other.
S = R’ = D
Behavior of D - Latch Similar to behavior of controlled RS latch since…………..?????
S = R’ = D
C D S R Ǫ Ǭ State
XX --10 1001 01
Reset
Set
X00111
No Change
QN+1 = S + R’QN Characteristic Equation
QN+1 = D + DQN QN+1 = D
JK- Latch
Why are the input terminals named as J,K??
C J K S’ R’ Ǫ Ǭ State
11 --11 --
10No Change
RESET
X0 X01 001 1
1
No Change
1
0
1
1
?
0
1
0
11
(0)
(1)
1
0
1
00
(0)
(1)
Behavior of JK- Latch
C J K S’ R’ Ǫ Ǭ State
11 --11 --
1001
No Change
RESET
SET
X0 X01 001 111 0
No Change
1
1
01
?0
1
0
1
0
(1)
(0)
1
0
1
0
1
(1)
(0)
Behavior of JK- Latch
C J K S’ R’ Ǫ Ǭ State
11 --11 --
1001
No Change
RESET
SET
X0 X01 001 111 0
No Change
Toggle11 1
1
1
?0
1
0
1
0
(1)
(0)
1
0
1
0
1
(0)
(1)
?10
Behavior of JK- Latch
Excitation Table of J-K Latch
C Qn J K Ǫn+1 State
xx 0
00 0
10 010 0
No Change
RESET
0 0
1 0
1 01 1
No Change
11 1 Toggle1 0
xx 10 1 No Change
00 1 No Change1 1
RESET
01 101 1
SET1 01 1 SET
Toggle11 01 1
Excitation Table of J-K Latch
Qn J K Ǫn+1
00 0
10 010 0
0
01
11 10
00 11
01 101 1
01
11 01
0 1 3 2
4 5 7 6
Qn’
Qn
J’K’ J’K JK JK’
11
11
QN+1 = JQN‘+ K’QN Characteristic Equation
State Diagram of J - K Latch
0 1
JK
0 0, 0 1 0 0, 1 01 0, 1 1
0 1, 1 1
T - Latch
Behavior of T - Latch Similar to behavior of controlled JK latch since…………..?????
J = K = T
C T J K Ǫ Ǭ State
XX --00 --11 --
No Change
Toggle
X00111
No Change
QN+1 = JQN‘+ K’QN Characteristic Equation
QN+1 = TQN‘+ T’QN
Hazards with latches If the response time (time required for the output to respond for a corresponding change in input) of any latch is assumed be 1nS. Then, it can be concluded that, for a T latch, the output toggles for 10 times if toggle state input (T=1) is in high state for 10nS. For RS latch, RACE condition occurs for 10 times if the corresponding inputs (R=S=1) are high for 10nS. These rapid changes in the output are undesirable and must be avoided.
Hazards with latches (Contd..)
Control
10nS
20nS
20nS
Control
1nS
So, these hazards can be eliminated by enabling the latch only once in a complete cycle.
Master Slave Configuration
J
Ctr
l
K
Q
Q’
J
Ctr
l
K
Q
Q’
Master – Slave Configuration of JK Latches
MASTER SLAVECtrl
Ctrl
Edge Sensitivity of FlipFlops
Control
20nS 20nS 20nS
In a complete Cycle (which is spread over a period of 20nS, The flip-flop responds only once i.e., only during the falling edge. This makes it possible to eliminate the race around condition in latches.
Elimination of hazards (Races) So, these hazards can be eliminated by enabling the latch only once in a complete cycle. So, it would be better to make the memory elements edge sensitive instead of level sensitive. Because, edges will occur only once in a cycle. Edge sensitive memory elements are called flip-flops. Latches are level sensitive and flip-flops are edge sensitive. Latches will respond many no. of times in a single clk cycle. But, flipflops will respond only once in a cycle.
Thank U
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