anne bracy cs 3410...anne bracy cs 3410 computer science cornell university the slides are the...

AnneBracyCS3410

ComputerScienceCornellUniversity

The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer.

Combinationallogic• Outputcomputeddirectlyfrominputs• Systemhasnointernalstate• Nothingdependsonthepast!

Need:• torecorddata• tobuildstateful circuits• astate-holdingdevice

Enter: SequentialLogic&FiniteStateMachines2

Inputs Combinationalcircuit

OutputsN M

State• Storing1bit

– Set-ResetLatch–DLatch–DFlip-Flops

• StoringNbits:– Registers–Memory

FiniteStateMachines(FSM)• Mealy(andMoore)Machines• SerialAdderExample

3

4nochange ResetsQ SetsQ Forbidden!

IfQis1,stays1ifQis0,stays0

WhathappenswhenS,Rchangesfrom1,1to0,0?Q,Q" becomeunstable,oscillate (0,0à 1,1à 0,0)

StoresavalueQanditscomplementS R Q Q"0 00 11 01 1

S

R

Q"

Q

A B OR NOR0 0 0 10 1 1 01 0 1 01 1 1 0

Forreference:

S

R

Q

Q"

0 0 1 1S

R

Q"

Q

S

R

Q"

Q

S

R

Q"

Q

S

R

Q"

Q0 01 1

HotelCalifornia

iClicker QuestionWhat’swrongwiththeSRLatch?

A. QisundefinedwhenS=1andR=1(That’swhythisiscalledtheforbiddenstate.)

B. Qoscillatesbetween0and1whentheinputstransitionfromS=1andR=1à S=0andR=0

C. TheSRLatchisproblematicb/cithastwooutputstostoreasinglebit.

D. ThereisnothingwrongwiththeSRLatch!

6

7

S

R

D

C

Q

Q"

C D Q Q"

0 00 1

1 0

1 1

• InverterpreventsSRLatchfromentering1,1state• C=enableschange

C=1,DLatchtransparent:set/reset(accordingtoD)

C=0,DLatchopaque:keepstate(ignoreD)

D QQ"C

Clock helpscoordinatestatechanges• Fixedperiod• Frequency=1/period

9

1

0clockperiod

clockhigh

clocklow

risingedgefalling

edge

Levelsensitive• Statechangeswhenclockishigh(orlow)

Edgetriggered• Statechangesatclockedge

10

positiveedge-triggered

negative edge-triggered

ClockMethodology• Negativeedge,synchronous

Edge-Triggeredà signalsmustbestablenearfallingedge“near”=beforeandafter

tsetupthold

11

clk

compute save

tsetup thold

compute save compute

tcombinational

12

S

R

D

clk

Q

Q"

clk D Q Q"

0 00 1

1 0

1 1

• Levelsensitive• InverterpreventsSRLatchfromentering1,1state• clk=enableschange

13

clk D Q Q"

0 0 Q Q"

0 1 Q Q"

1 0 0 1

1 1 1 0

clk

DQ

D QQ"clk

WhatisthevalueofQatA&B?a) A=0,B=0b) A=0,B=1c) A=1,B=0d) A=1,B=1

A B

• Edge-Triggered• Datacapturedwhenclockhigh

• Outputchangesonlyonfallingedges

D QQ"

D QQ"C C

X Q

Q"D

clkL1 L2

15

Clock=1: L1transparentL2opaque

D QQ"

D QQ"C C

X Q

Q"Dclk 01

L1 L2

XD

DpassesthroughL1toX

X

Clock=0: L1opaqueL2transparent

D QQ"

D QQ"C C

X Q

Q"Dclk 10

L1 L2

X Q

X passesthroughL2toQ

X

16

Thus,onedgeoftheclock(whenCLK fallsfrom1à0)

(D passesthroughtoQ)

17

D QQ"

D QQ"C C

clk

D

X

Q

X Q

Q"D

clk 1

L1 L2

WhatisthevalueofQatA&B?a) A=0,B=0b) A=0,B=1c) A=1,B=0d) A=1,B=1

A B

State• Storing1bit

– Set-ResetLatch–DLatch Awordaboutclocks–DFlip-Flops Awordaboutterminology

• StoringNbits:– Registers–Memory

FiniteStateMachines(FSM)• MealyandMooreMachines• SerialAdderExample

19

• Dflip-flopsinparallel• sharedclock• Additional(optional)inputs:

writeEnable,reset,…

20

clk

D0

D3

D1

D2

4 44-bitreg

clk

RegisterFile• Nread/writeregisters• Indexedbyregisternumber

Dual-Read-PortSingle-Write-Port

32x32RegisterFile

QA

QB

DW

RW RA RBW

32

32

32

1 5 5 5

21

RegisterFile• Nread/writeregisters• Indexedbyregisternumber

addi r5, r0, 10

Howtowritetoone registerintheregisterfile?• Needadecoder

Reg 0

Reg 30Reg 31

Reg 15-to-32decoder

5RW

D32

….…00101

22

i2 i1 i0 o0 o1 o2 o3 o4 o5 o6o7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

3-to-8decoder

3RW

…

101

23

RegisterFile• Nread/writeregisters• Indexedbyregisternumber

addi r5, r0, 10

Howtowritetoone registerintheregisterfile?• Needadecoder

Reg 0

….Reg 30Reg 31

Reg 15-to-32decoder

5RW W

D32

25

RegisterFile• Nread/writeregisters• Indexedbyregisternumber

Howtoreadfromtworegisters?• Needamultiplexor

32Reg 0Reg 1….Reg 30Reg 31

MUX

MUX

32QA

32QB

55RBRA

….

….

26

RegisterFile• Nread/writeregisters• Indexedbyregisternumber

Implementation:• Dflipflopstostorebits• Decoderforeachwriteport• Mux foreach readport

32Reg 0Reg 1….Reg 30Reg 31

MUX

MUX

32QA

32QB

55RBRA

….

….

5-to-32decoder

5RWW

D32

27

RegisterFile• Nread/writeregisters• Indexedbyregisternumber

Implementation:• Dflipflopstostorebits• Decoderforeachwriteport• Mux foreach readport

Dual-Read-PortSingle-Write-Port

32x32RegisterFile

QA

QB

DW

RW RA RBW

32

32

32

1 5 5 5

28

RegisterFiletradeoffs+ Veryfast(afewgatedelaysfor

bothreadandwrite)+ Addingextraportsis

straightforward– Doesn’tscalee.g.32Mbregisterfilewith32bitregistersNeed32x1M-to-1multiplexorand32x20-to-1MdecoderHowmanylogicgates/transistors?

a

b

c

d

e

f

g

h

s2s1s0

8-to-1mux

29

• Set-Reset(SR)Latchcanstoreonebitandwecanchangethevalueofthestoredbit.But,SRLatchhasaforbiddenstate.

• DLatchcanstoreandchangeabitlikeanSRLatchwhileavoidingaforbiddenstate.

• ADFlip-Flipstoresonebit.Thebitcanbechangedinasynchronizedfashionontheedgeofaclocksignal.

• AnN-bitregister storesN-bits.ItisbecreatedwithN D-Flip-Flopsinparallelplusasharedclock.

30

• StorageCells+bus• Inputs:Address,Data(forwrites)• Outputs:Data(forreads)• AlsoneedR/Wsignal(notshown)

• Naddressbitsà 2Nwordstotal• Mdatabitsà eachwordMbits M

NAddress

Data31

• StorageCells+bus• Decoderselectsawordline• R/Wselector determines accesstype• Wordlineisthencoupledtothedatalines

datalines

Address

Decode

rR/W

E.g.Howdowedesigna4x2MemoryModule?

(i.e.4wordlinesthatareeach2bitswide)?

2-to-4decoder

2Address

D Q D Q

D Q D Q

D Q D Q

D Q D Q

Dout[1] Dout[2]

Din[1] Din[2]

enable enable

enable enable

enable enable

enable enable

0

1

2

3WriteEnable

OutputEnable

4x2Memory

33

2-to-4decoder

2Address

Dout[1] Dout[2]

Din[1] Din[2]

enable enable

enable enable

enable enable

enable enable

0

1

2

3WriteEnable

OutputEnable

E.g.Howdowedesigna4x2MemoryModule?

(i.e.4wordlinesthatareeach2bitswide)?

2-to-4decoder

2Address

Dout[1] Dout[2]

Din[1] Din[2]

enable enable

enable enable

enable enable

enable enable

0

1

2

3WriteEnable

OutputEnable

E.g.Howdowedesigna4x2MemoryModule?

(i.e.4wordlinesthatareeach2bitswide)?

Bitlines

35

2-to-4decoder

2Address

Dout[1] Dout[2]

Din[1] Din[2]

enable enable

enable enable

enable enable

enable enable

0

1

2

3WriteEnable

OutputEnable

E.g.Howdowedesigna4x2MemoryModule?

(i.e.4wordlinesthatareeach2bitswide)?

Wordlines

36

What’syourfamiliaritywithmemory(SRAM,DRAM)?

A. I’veneverheardofanyofthis.B. I’veheardthewordsSRAMandDRAM,butI

havenoideawhattheyare.C. IknowthatDRAMmeansmainmemory.D. IknowthedifferencebetweenSRAMand

DRAMandwheretheyareusedinacomputersystem.

37

TypicalSRAMCell

BB"

wordlinebitline

Eachcellstoresonebit,andrequires4– 8transistors(6istypical)

Pass-ThroughTransistors

38

SRAM•Afewtransistors(~6)percell•Usedforworkingmemory (caches)

•Butforevenhigherdensity…

39

Dynamic-RAM(DRAM)• Datavaluesrequireconstantrefresh

Gnd

wordlinebitline

Capacitor

Eachcellstoresonebit,andrequires1 transistors40

Dynamic-RAM(DRAM)• Datavaluesrequireconstantrefresh

Gnd

wordlinebitline

Capacitor

Pass-ThroughTransistors

Eachcellstoresonebit,andrequires1 transistors41

Singletransistorvs.manygates• Denser,cheaper($30/1GBvs.$30/2MB)• Butmorecomplicated,andhasanalogsensing

Alsoneedsrefresh• Readandwriteback…• …everyfewmilliseconds• Organizedin2Dgrid,socandorowsatatime• Chipcandorefreshinternally

Hence…slowerandenergyinefficient42

RegisterFiletradeoffs+ Veryfast(afewgatedelaysforbothreadandwrite)+ Addingextraportsisstraightforward– Expensive,doesn’tscale– Volatile

VolatileMemoryalternatives:SRAM,DRAM,…– Slower+ Cheaper,andscaleswell– Volatile

Non-VolatileMemory(NV-RAM):Flash,EEPROM,…+ Scaleswell– Limitedlifetime;degradesafter100000to1Mwrites

43

State• Storing1bit

–Bistable Circuit– Set-ResetLatch–DLatch–DFlip-Flops

• StoringNbits:– Registers–Memory

FiniteStateMachines(FSM)• MealyandMooreMachines• SerialAdderExample 44

Anelectronicmachinewhichhas• externalinputs• externallyvisibleoutputs• internalstate

Outputandnextstatedependon• inputs• currentstate

45

FiniteStateMachine

• inputsfromexternalworld• outputstoexternalworld• internalstate• combinationallogic

46

NextState

CurrentState

Input

OutputRe

gistersComb.Logic

47

Legend

state

input/output

startstate

A B

0/01/0 0/0

1/1

Input:1or0Output:1 or0States:A orB

WhatinputpatternistheFSM“lookingfor”?

(MealyMachine)

GeneralCase:MealyMachine

Outputsandnextstatedependonbothcurrentstateandinput

48

NextState

CurrentState

Input

OutputRe

gistersComb.Logic

SpecialCase:Outputs dependonlyoncurrentstate

49

NextState

CurrentState

Input

OutputRe

gisters Comb.

Logic

Comb.Logic

A0

B0

0

1

0

1Legend

stateout

input

startout

C1

1

0

Addtwoinfiniteinputbitstreams• streamsaresentwithleast-significant-bit(lsb)first• HowmanystatesareneededtorepresentFSM?• DrawandFillinFSMdiagram

50

…10110

…01111…00101

Strategy:(1)Drawastatediagram(e.g.MealyMachine)(2)Writeoutputandnext-statetables(3)Encodestates,inputs,andoutputsasbits(4)Determinelogicequationsfornextstateandoutputs

states:Inputs:??? and???Output:???

• .51

…10110

…01111…00101

states:Inputs:??? and???Output:???

• .52

S0 S1__/_ __/_

__/_

__/_

__/___/_

__/_

__/_

…10110

…01111…00101

Twostates:S0 (nocarryin),S1 (carryin)Inputs:a andbOutput:z

• z isthesumofinputsa,b,andcarry-in(onebitatatime)• Acarry-outis thenextcarry-instate.• .

53

…10110

…01111…00101

a

bz

S0 S1__/_ __/_

__/_

__/_

__/___/_

__/_

__/_

54

?? ?? Current state

? Next state

(2)Writedownallinputandstatecombinations

S0 S1__/_ __/_

__/_

__/_

__/___/_

__/_

__/_

55

a b Current state

z Next state

S0 S100/0 11/1

01/0

11/0

10/010/1

00/1

01/1

(2)Writedownallinputandstatecombinations

(2)Writedownallinputandstatecombinations

56

a b Current state

z Next state

0 0 S0 0 S00 1 S0 1 S01 0 S0 1 S01 1 S0 0 S10 0 S1 1 S00 1 S1 0 S11 0 S1 0 S11 1 S1 1 S1

S0 S100/0 11/1

01/0

11/0

10/010/1

00/1

01/1

57

?? ?? Current state

? Next state

(3)Encodestates,inputs,andoutputsasbits

S0 S1__/_ __/_

__/_

__/_

__/___/_

__/_

__/_

(3)Encodestates,inputs,andoutputsasbits

Twostates,so1-bitissufficient(singleflip-flopwillencodethestate)

58

a b s z s'0 0 0 0 00 1 0 1 01 0 0 1 01 1 0 0 10 0 1 1 00 1 1 0 11 0 1 0 11 1 1 1 1

0 100/0 11/1

01/0

11/0

10/010/1

00/1

01/1

59

?? ?? Current state

? Next state

(4)Determinelogicequationsfornextstateandoutputs

(4)Determinelogicequationsfornextstateandoutputs

CombinationalLogicEquationsz =a%bs̅ +abs +abs+abss’ =abs̅ +a%bs+ab%s+abs

60

NextState

CurrentState

Input

Output

Comb.Logica

b

D Q s zs'

s'

NextState

a b s z s'0 0 0 0 00 1 0 1 01 0 0 1 01 1 0 0 10 0 1 1 00 1 1 0 11 0 1 0 11 1 1 1 1

61

Strategy:(1)Drawastatediagram(e.g.MealyMachine)(2)Writeoutputandnext-statetables(3)Encodestates,inputs,andoutputsasbits(4)Determinelogicequationsfornextstateandoutputs

NextState

CurrentState

Input

Output

Comb.Logica

b

D Q s zs'

s'

NextState

z =a%bs̅ +abs +abs+abss’ =abs̅ +a%bs+ab%s+abs

Wecannowstoredatavalues• Statefulcircuitelements(DFlipFlops,Registers,…)• Clocksynchronizesstatechanges• StateMachinesorAd-HocCircuits

62