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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 1201ASP
v8.0 January 2007
201ASPMid-Range Family PeripheralConfiguration and Assembly
Programming
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 2201ASP
Objectives
At the end of this class you will: ² Understand the basic PICmicro peripherals
and their associated registers
² Have ³HANDS ON ́
experience initializingMid-Range peripherals
² Be able to implement peripherals notcovered here
² Understand interrupts and polling
² Write your own application code from³scratch´
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 3201ASP
To get the most from this Class
Ideally you should be familiar with thefollowing:
² Assembler programming
² Basic Mid-Range family Instruction set ² Data and Program memory organization
² MPLAB Integrated Development Environment
² Microchip ICD2 debugger
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 4201ASP
201ASP Agenda
Bri ef review of Mid-Range Architecture,Instruction Set and Tools
Interrupts on the Mid-Range PICmicro ² Interrupts Lab
Peripheral discussion: ² Input/Output Ports ² Timers
Timer0 Timer1
² Timer1 Lab Timer2
² Timer2 Lab
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 5201ASP
201ASP Agenda (cont.)
Capture / Compare / PWM Module (CCP) ² PWM and Output Compare Labs
Analog Comparator
Analog to Digital Converters (ADC) ² ADC Lab
Addressable Universal Asynchronous &Synchronous Receiver & Transmitter (AUSART)
I2C with the Master Synchronous Serial Port ² I2C Based Temp Sensor Lab
Wrap-Up and additional questions
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 6201ASP
v8.0 January 2007
Mid-Range Family BasicArchitecture and
Development Tools
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 7201ASP
Mid-Range PIC Block Diagram
ADC
TIMER0
MUX
ALU
AUSART
MSSP
PERIPHERALS
WORKINGREGISTER
STATUS REGISTER
Pages of
ProgramMemory
Banks of Data Memory
INSTRUCTION REGISTER
8-bit value from instruction
14-bits
PROGRAM COUNTER
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 8201ASP
Program Memory
Maximum 8K words ² (8K x 14 bits/word)/1 byte
= 14Kbytes of memory
Reset Vector at 0000h ² Program Counter (PC) will
go to this address onreset
Interrupt Vector at 0004h ² Program Counter (PC) will
go to this address uponany Interrupt
Reset Vector
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
0000h
0004h
0005h07FFh
0800h0FFFh
1000h17FFh
1800h1FFFh
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 9201ASP
Program Counter (PC) and Stack
13-bit PC ² PCL ALU result (8-bits) or
OPCODE(11-bits)
² PCH Paging bits U
pdated from PCLATH Specifies page in program
memory
8 Level Deep Stack
² Stores the contents of the PC PUSHES
² CALL/Interrupt
POPS ² RETURN, RETFIE,RETLW
PCLATH
PCH<12:8> PCL
Stack Level 1
Stack Level 8
Program Memory
PC<12:0>
CALL, RETURN,RETFIE, RETLW
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 10201ASP
Data Memory Map
128Bytes
Shared Shared Shared
Bank 0 Bank1 Bank2 Bank3
000h
01Fh
020h
07Fh
080h
09Fh
0A0h
0FFh
100h
110h
17Fh
180h
190h
1FFh
0EFh 16Fh 1EFh
10Fh 18FhSpecial
Function
RegistersRegisters
SFR SFR
General
PurposePurpose
RegistersRegisters
GeneralGeneral
PurposePurpose
RegistersRegisters
Special
FunctionFunction
RegistersRegisters
GeneralGeneral
Purpose
RegistersRegisters
General
PurposePurpose
RegistersRegisters
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 11201ASP
Special Function Registers (SFRs)
06hPORTB
PORTC 07h
PORTD 08h
PORTE 09h
PCLATH 0Ah
INTCON 0Bh
PIR1 0Ch
PIR2 0Dh
86hTRISB
TRISC 87h
TRISD 88h
TRISE 89h
PCLATH 8Ah
INTCON 8Bh
PIE1 8Ch
PIE2 8Dh
Bank0 Bank1
Register File Concept
Accessed like anyother register
Some registers carryacross all banks(PCLATH, INTCON, etc.)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 12201ASP
Status Register
Contains:
² Arithmetic status of theALU
² The RESET status
² Bank select bits for datamemory
RP1 RP0
RP1 RP00 0
0 11 0
1 1
BANK0
BANK1BANK2
BANK3
IRP RP1 RP0 TO PD Z DC C
Indirect Register Bank Select bit:(used for indirect addressing)
1 = Bank 2,3
0 = Bank 0,1
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 14201ASP v8.0 January 2007
PICmicro Development
Tools
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 15201ASP
MPLAB ® IDE
MPLABMPLAB®® IDE (Integrated DevelopmentIDE (Integrated DevelopmentEnvironment)Environment)
Integrates different Microchip and thirdIntegrates different Microchip and third
party toolsparty tools ² ² Code Editor Code Editor
² ² Cross CompilersCross Compilers
² ² AssemblersAssemblers ² ² Simulators, InSimulators, In--Circuit Debuggers, EmulatorsCircuit Debuggers, Emulators
² ² ProgrammersProgrammers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 16201ASP
MPLAB ® IDE
MPLABMPLAB®® IDE (IDE (IIntegratedntegrated DDevelopmentevelopmentEEnvironment)nvironment)
Integrates different Microchip and thirdIntegrates different Microchip and third
party toolsparty tools ² ² Code Editor Code Editor
² ² Cross CompilersCross Compilers
² ² AssemblersAssemblers ² ² Simulators, InSimulators, In--Circuit Debuggers, EmulatorsCircuit Debuggers, Emulators
² ² ProgrammersProgrammers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 17201ASP
ICD 2 (In Circuit Debugger)
MPLABMPLAB ® ICD 2 is a low cost, realICD 2 is a low cost, real--timetimedebugger and programmer.debugger and programmer.
² ² Reading/Writing memory space andReading/Writing memory space and
EEDATA areas of the PICEEDATA areas of the PIC ² ² Programs configuration bitsPrograms configuration bits
² ² Real time debuggingReal time debugging
² ² Erase of program memoryErase of program memoryspace with verificationspace with verification
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 18201ASP
18, 28 and 40-pin DIP
sockets
9V to 5V
regulator
ICDConnecto
r
RS232Connecto
r
Push buttonSwitches
PICDEM® 2 Plus Board
Analog Pot
LEDs16 x 2 LCD
Module
PiezoB
uzzer
I2C Based
Temp Sensor
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 19201ASP v8.0 January 2007
Interrupts
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 20201ASP
Often we would like the processor toperform a task if a specific event occurs
Two methods to check if this event hasoccurred:
² Polling:
Continuously check for event at various points in
the code ² Interrupts:
³INTERRUPTS´ the Main program and starts anInterrupt Service Routine when an event occurs
Polling and Interrupts
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 21201ASP
Polling
bsf PORTA,1 ;Set bit 1 of;PORTA
btfss INTCON,TMR0IF ;Check Timer0;interrupt flag;in ³INTCON´;register and ;skip the next;instruction if;it is set
goto $-1 ;Go to;previous;instruction
bcf PORTA,1 ;Clear bit 0 of;PORTA
RA<1> = 1
TMR0IF = 1??
RA<1> = 0
YES
NO
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 22201ASP
Reset code 000hgoto Start
;=========================int_vector code 004h
retfie ;return from ;interrupt
;=========================
main_prog code
Start ;start label for maincode
end
Interrupts
Mainprogram
execution
no interrupt
Execute ISR at
address 004h
interrupt flagset
retfieinstruction
Interrupt Service
Routine (ISR)
Main programcode
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 23201ASP
Enabling Interrupts
Processor must be told that interruptswill be used
² A number of registers with interrupt enable
bits do this: Interrupt Control (INTCON)
Peripheral Interrupt Enable 1 (PIE1)
Peripheral Interrupt Enable 2 (PIE2)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 24201ASP
Interrupt Logic
INTEINTF
RBIERBIF
TMR2IE
TMR2IFADIEADIF
PEIE
GIE
Interrupt
Other peripherals
TMR0IETMR0IF
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 25201ASP
GIE
INTCON Register (Core Interrupts)
PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
Flags will seteven if interruptsaren¶t enabled!
Global Interrupt EnableGIE
Peripheral Interrupt EnablePEIE
Timer0 Interrupt EnableTMR0IE
External Interrupt EnableINTEPORTB change Interrupt EnableRBIE
DescriptionEnable Bits
Timer0 Overflow Interrupt FlagTMR0IF
RB0/INT External Interrupt FlagINTF
PORTB Change Interrupt FlagRBIF
DescriptionFlag Bits
Must be set to useany Interrupts
Must be set to useany Peripheral
Interrupts
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 26201ASP
Enabling a Core Interrupt
INTCON
GIE
Interrupt detected
on ³RB0/INT´ Pin!!
0
³goto $´ address
Stack
0 0 0 0 0 0 011INTE INTF
1
Int_vect CODE 004h
;clear external interrupt;flag to enable;further interrupts bcf INTCON,INTF
<ISR code> retfie
Main CODEStart
<code to set up PORTB >
; initialize INTCONclrf INTCON
;enable an external;interrupt on the INT pin bsf INTCON,INTE
;enable global interrupts bsf INTCON,GIE; sit here and loop forevergoto $
Program Counter
³goto $´ address
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 27201ASP
Peripheral Interrupts
Two registers E NABLE interrupts for peripherals ² Peripheral Interrupt Enable 1 (PIE1) ² Peripheral Interrupt Enable 2 (PIE2)
Two registers display peripheralREQUE STS for an interrupt (F lags) ² Peripheral Interrupt Request 1 (PIR1)
² Peripheral Interrupt Request 2 (PIR2)
*Flags will set even if interrupts are not enabled!!
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 28201ASP
PIE1 and PIR1 Registers*
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
PIE1 Register (Peripheral Interrupt Enables)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
PIR1 Register (Peripheral Interrupt Requests)
ADIE ADIF ADC conversion complete
RCIE RCIF AUSART receive buffer is full
TXIE TXIF AUSART transmit buffer is full
SSPIE SSPIF I2
C or SPI InterruptCCP1IE CCP1IF Timer1 register capture or compare match
TMR2IE TMR2IF Timer2 value and PR2 period value match
TMR1IE TMR1IF Timer1 register has overflowed
Enable Flag Condition
*Check individual datasheets for bit locations
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 29201ASP
PIE2 and PIR2 Registers*
C2IE C1IE EEIE BCLIE ULPWUIE CCP2IEOSCFIE
PIE2 Register (Interrupt Enables)
C2IF C1IF EEIF BCLIF ULPWUIF CCP2IFOSCFIF
PIR2 Register (Interrupt Flags)
C2IE C2IF Comparator2 output changed
C1IE C1IF Comparator1 output changed
EEIE EEIF Write operation completedBCLIE BCLIF Bus collision occurred in MSSP I2C mode
ULPWUIE ULPWUIF Wake-up condition occurred
CCP2IE CCP2IF Timer1 Capture or Compare match occurred
OSCFIE OSCFIF System Oscillator Failed
Enable Flag Condition
*Check individual datasheets for bit locations
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 30201ASP
Enabling a Peripheral (Timer 1)Interrupt
1 1
INTCON
GIE PEIE
PIE1
PIR1
TMR1IE
TMR1IF
1
0
Timer1 Overflow!
1
0
³goto $´ address
³goto $´ address
Int_vect CODE 004h
banksel PIR1 bcf PIR1, TMR1IF
<ISR code> retfie
Main CODEStart
banksel PIR1 bcf PIR1,TMR1IF banksel PIE1 bsf PIE,TMR1IE
bsf INTCON,PEIE bsf INTCON,GIE
<code to set up Timer1>
; sit here and loop forevergoto $
Stack
Program Counter
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 31201ASP
Interrupt Latency
Interrupt Latency: ² Time from interrupt event to execution of
instruction at address 0004h
² Synchronous interrupts (typically internal) latency is 3 instruction cycles (Tcy)
² Asynchronous interrupts (typically external)
latency is 3 ± 3.75 instruction cycles
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 32201ASP
Context Saving
During an interrupt: ² Only the PC value is saved (on the stack)
² Registers changed in the Interrupt ServiceRoutine (ISR) are permanently changed
Key registers you may want saved:
² Working register
² Status
² PCLATH (Program Counter Latch High)
² User defined registers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 33201ASP
Interrupt Priority
Mid-Range PIC microcontrollers treat allInterrupts with the same priority
The user must do the following: ² Determine source of interrupt
² Determine the order in which the interrupts
are serviced.
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 34201ASP
Interrupt Priority ExampleINT_VECTOR CODE 0x004 ;interrupt vector location
;Save context movwf temp_w ;save WREGswapf STATUS,w ;movf affects Z bit,
;use swapf instead movwf temp_status ;save STATUS register
;Check flags in order of priority btfsc INTCON,RBIF ;PORTB change?call PORTB_ISR btfsc PIR1,TMR2IF ;Timer2 interrupt?call Timer2_ISR btfsc PIR2,TMR1IF ;Timer1 interrupt?
call Timer1_ISR Restore_context:
swapf temp_status,w movwf STATUS ;restore STATUS reg movf temp_w,w ;restore WREGretfie ;return from interrupt
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 35201ASP v8.0 January 2007
InterruptHands on Lab
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 36201ASP
Interrupt
The objective of this is to:
² Learn how to set up and enable aninterrupt on the Mid-Range PIC
² Become more familiar with the MPLAB IDE,the PICdem2 Plus and the ICD2
Building a Project
Using the ICD to set a break point
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 37201ASP
Interrupt Lab Overview
Enable Interrupts
Initialize PORTB
(RB
0) for S3 input
Clear Variables
³No Operation´ NOP
Calldebounce
delay function
IncrementCount variable
Clear IF
Return to Main
Interrupt Vector Main Program
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 38201ASP
Lab Specifics
Code is located in C:\RTC\201_ASP\Lab1-INT
The S3 switch is connected to the ³RBO/INT´ pin on PORTB
The ³push_count´ register will display the #of times S3 has been pushed.
Use MPLAB and the ICD to set a ³breakpoint´
in the code to view the changing value of theregister named ³push_count´
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 39201ASP
What you need to know
The function of the INTCON register bits
Jumper J6 must be removed in order for the INTE pin to work
A subroutine called ³debounce´ is given
² masks the mechanical bouncing of S3
How to setup break points and a ³W atch W indow ́ in MPLAB
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 40201ASP
Interrupt Lab Solution
bsf STATUS,RP0 ; point to BANK1
bsf TRISB,0 ; ### initialize PORTB<0> as input
bsf INTCON,INTE ; ### enable INTE interrupts bsf INTCON,GIE ; ### Enable global interrupts
bcf STATUS,RP0 ; return to BANK0
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 41201ASP v8.0 January 2007
Peripherals
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 42201ASP
Mid-Range Family Peripherals
I/O Ports
Timers (0, 1, 2)
Capture/Compare/PWM
Comparators Analog-to-Digital
Converter
AUSART
I2C and SPI SerialInterface
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 43201ASP
I/O Overview
Up to 35 bi-directional Input/Output pins ² some multiplexed with peripheral functions
High drive capability
² 25mA source or sink
Direct, single cycle bit manipulation
Most I/O¶s have ESD protection
After Reset:
² Analog capable pins come up as Analog
² Digital I/O pins come up as I npu t
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 44201ASP
PORTx and TRISx Registers
Every PORT (A,B
, C, D, E) will have acorresponding direction register TRISx
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
PORTB Register
TRISB7 TRISB6 TRISB5 TRISB4TRISB3 TRISB2 TRISB1 TRISB0
PORTB Tri-State Register (TRISB)
1 = corresponding PORTB pin is an I NP U T
0 = corresponding PORTB pin is an O U TP U T
DataConfigures Data Direction
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 45201ASP
Configuring Analog Inputs for Digital
I/O¶s with digital and analog capabilities
default to analog on reset
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 47201ASP
Configuring Analog Inputs for Digital
ADFM ADCS2
ADC Control Register 1 (ADCON1)
PCFG3 PCFG2 PCFG1 PCFG0
Port Configuration Bits
VddAN7 AN6 AN5 AN4 AN1 AN0AN3 AN2PCFG<3:0>
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 48201ASP
Initializing Digital I/O
Initialize PORTB ² RB4 through RB7 as Digital Inputs ² RB0 through RB3 as Digital Outputs
;------------configure PORTB for digital ---------------------- banksel PORTB ;Go to bank containing PORTB registerclrf PORTB ;Initialize PORTB data
banksel ANSELH ;Go to bank containing ANSELH registerclrf ANSELH ;Set as all digital
;-----------Set up direction of each PORTB pin-----------------
banksel TRISB ;Go to bank containing TRISB register movlw b¶11110000¶ ;Move value to set TRISB<7:4> high and
;TRISB<3:0> low into W register movwf TRISB ;Move value in W into TRISB
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 49201ASP
PORTB Interrupt & Weak Pull-Up Options
All PORTB pins have Interrupt-on-Change
and Weak Pull-Up options
RB3WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
Weak Pull-Up PORTB Register (WPUB)
1 = Pull-up enabled
0 = Pull-up disabled
1
IOCB7 IOCB6 IOCB5 IOCB4 ICOB3 IOCB2 IOCB1 IOCB0
RB4
Interrupt-On-Change PORTB Register (IOCB)
1 = Interrupt-on-change enabled0 = Interrupt-on-change disabled
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
Interrupt Control Register (INTCON)
RBIF
1
HIGHLOW
*PORTB must first be read/written and then RBIF can be cleared in software
Devices without WPUB register
use RBPU bit in OPTION register
Devices without IOCB relyon RBIE bit in INTCON
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 50201ASP v8.0 January 2007
Timers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 51201ASP
Timers are used for many functions: ² timing reference to generate an event
² count the number of events
²
waveform generation etc...
PIC16F877 has 3 timers
² Timer0
² Timer1
² Timer2
Timers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 52201ASP
Timer ComparisonTIMER0 TIMER1 TIMER2
SIZE OFREGISTER
8-bits (TMR0) 16-bits(TMR1H:TMR1L)
8-bits (TMR2)
CLOCK SOURCE
(Internal)
Fosc/4 Fosc/4 Fosc/4
CLOCK SOURCE
(External )
T0CKI pin T1CKI pin or
Timer 1 oscillator (T1OSC)
None
CLOCK SCALINGAVAILABLE
(Resolution)
Prescaler 8-bits(1:21:256)
Prescaler 3-bits(÷1,÷2,÷4,÷8)
Prescaler (1:1,1:4,1:8)
Postscaler (1:11:16)
INTERRUPTEVENT and FLAG
LOCATION
On overflowFFh00h
(TMR0IF in INTCON)
On overflowFFFFh0000h
(TMR1IF in PIR1)
TMR2 matchesPR2
(TMR2IF in PIR2)
CAN WAKE PICFROM SLEEP?
NO YES NO
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 53201ASP
Timer 0 Block Diagram
scaled clock TMR0T0CKIpin
Fosc/4
prescaler Watchdog Timer
synchronize
WDT out
OPTION register RBPU INTEDG TOCS TOSE PSA PS2 PS1 PS0
TMR0 ClockSource Select1 = TOCKI, 0 = Fosc/4 Source Edge Select
1 = increment TMR0 on high-to-low transition
0 = increment TMR0 on low-to-high transition
Prescaler Assignment1= prescaler assigned to WDT0= prescaler assigned to Timer 0
Prescaler Rate Select Bits
PS2 PS1 PS0TMR0RATE
0 0 0 1:2
0 0 1 1:4
0 1 0 1:8
0 1 1 1:16
1 0 0 1:32
1 0 1 1:64
1 1 0 1:128
1 1 1 1:256
8
DATA BUS
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 54201ASP
scaled clock TMR0T0CKIpin
Fosc/4
prescaler Watchdog Timer
synchronize
8
DATA BUS
Timer 0 is readable or writeable
TMR0IF
INTCON register
If the external clock source (TOCKI) is used it will besynchronized to the internal clock
Timer 0 interrupt flag is set on TMR0 roll-over (FF to 00)
Timer 0 Block Diagram
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 55201ASP
Timer0 Initialization
TMR00 0 0 0 0 0 0 0
INTCON
0
OPTION_REG
0 0 0 0 0 0 1 1
TMR0IF
This interrupt flag will set onTimer0 overflow even if interrupts are disabled
PSA
PS<2:0>
TOCS
Selects Timer 0Clock Source
(External or Internal)
Prescaler Assignment
(WDT or TMR0)
Prescaler value = 1:16
1
;Make sure the Timer0 count
;register (TMR0) is clear banksel TMR0clrf TMR0
;Clear Timer0 interrupt flag bcf INTCON,TMR0IF
;Setup the Option register to;increment Timer0 from internal;clock with a prescaler of 1:16 banksel OPTION_REG movlw b¶00000011¶ movwf OPTION_REG
;The TMR0 interrupt is disabled, do;polling on the flag bit (TMR0IF) btfss INTCON,TMR0IFgoto $-1
<continue>
1 1 1 1 1 1 0 01 110 0 0 0 0 0 0 0
Timer0incrementing
Flag on overflow
1 B
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 56201ASP
Timer1 Block Diagram
T1CKIpin
T1OSCT1OS0
T1OSI
prescaler synchronize
Timer1 Control Register (T1CON)
Clock Source Select1 = External (T1CKI)0 = Internal (FOSC /4)
LP Oscillator Enable1 = T1OSC selected0 = T1CKI can be used
Fosc/4
T1CKPS1 T1CKPS0 scale
1 1 1:8
1 0 1:4
0 1 1:2
0 0 1:1
Timer1 On1 = Enable Timer1
T1GINV TMR1GE T1CKPS1T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
TMR1H TMR1L
Enable
TMR1ON
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 57201ASP
Timer1 External Clock Input Synchronization1 = do not synchronize external clock input0 = synchronize external clock input with
internal clock (Fosc/4)
Timer1 Block Diagram
T1CKIpin
T1OSCT1OS0
T1OSI
prescaler synchronize
Timer1 Control Register (T1CON)
Fosc/4
TMR1H TMR1L
Timer1 Gate Enable andTimer1 Gate Invert areavailable on some devices
Enable
TMR1ON
T1CKPS1T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ONT1GINV TMR1GE
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 58201ASP
Main CodeStart;Start by clearing the Timer1 interrupt flag
banksel PIR1 bcf PIR1, TMR1IF
;Enable Timer1 interrupt banksel PIE1 bsf PIE1, TMR1IE
;Enable Global and Peripheral Interrupts bsf INTCON, PEIE bsf INTCON, GIE
Timer1 Interrupt Setup
INTCON
PIE1
1
GIE PEIE
TMR1IE
1
1
PIR1
TMR1IF
0
TMR1H
1 1 1 1 1 1 1 10 0 0 0 0 0 0 0
TMR1L
1 1 1 1 1 1 0 11 1 1 1 1 1 1 01 1 1 1 1 1 1 10 0 0 0 0 0 0 0
1
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 59201ASP
Timer1 InitializationTMR1H
0 0 0 0 0 0 0 0
T1CON (Timer1 Control)
Input clockprescale bits(T1CKPS<1:0>)
TMR1L
0 0 0 0 0 0 0 0
PIR1 (Peripheral Interrupt Request)
TMR1IF
0000000 0
000000 11
Clock sourceselect bit
(TMR1CS)
TMR1ON
1
TMR1H:TMR1L INCREMENTING
1
OVERFLOW!!
;Make sure the TMR1 registers are clear
banksel TMR1Hclrf TMR1Hclrf TMR1L
;Make sure the TMR1IF flag in PIR1;is cleared
banksel PIR1 bcf PIR1,TMR1IF
;Setup T1CON register for internal clock;with 1:8 prescaler, Timer1 is stopped ;and T1 osc is disabled
movlw b¶00110000¶ movwf T1CON
;Start Timer1 incrementing
bsf T1CON, TMR1ON
;The TMR1 interrupt is disabled, do;polling on the Timer1 flag bit
btfss PIR1, TMR1IFgoto $-1
Timer1oscillator enable bit
(T1OSCEN)
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 60201ASP v8.0 January 2007
Timer1 Lab
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 61201ASP
Timer1 Lab
Objective of this lab is to become familiar with
the operation of Timer1
AND
To gain experience enabling Peripheral
Interrupts
L b O i
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 62201ASP
Lab Overview
Initialize PORTB
Initialize Timer1 clocksource and pre-scaler:
Timer1 interrupts
every 100,000 Instruction cycles
Enable Timer1, Globaland Peripheral Interrupts
NOP Main Loop
Main ProgramInterrupt Vector Save Context
Clear IF
Reload Timer1
Toggle LED 0
Toggle LED 3
Restore Context
Retfie
5th Int. ?NO
YES
L b S ifi
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 63201ASP
Lab Specifics
The code for the lab is inC:\RTC\201_ASP\Lab2-TMR1
Within lab2.asm complete the following ² Set Timer1 clock source to Fosc/4
² Set Timer1 pre-scaler to 2
²
Load Timer1 with 0x3CB0(65,536 ± 50,000)
² Start Timer1
² Enable Timer1, Global and Peripheral Interrupts
Wh t d t k
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 64201ASP
What you need to know
Register Operations of INTCON, T1CON,
TMR1H, TMR1L and PIE1
With a value of 0x3CB0 and a pre-scaler of 2,
Timer1 will overflow every 100,000 cycles
The interrupt vector code to toggle the LEDshas been provided
Ti 1 LAB S l i
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 65201ASP
Timer1 LAB Solution;*******************************************************************
;Set code to Select clock source, Set pre-scaler to 2, load hex 3CB0;into Timer1 and turn on Timer1;*******************************************************************
movlw 0x3C ; ### initialize TMR1L and TMR1H movwf TMR1H ; ### movlw 0xB0 ; ### movwf TMR1L ; ###
bsf T1CON,T1CKPS0 ; ### configure prescaler to 1:2 bsf T1CON,T1CKPS1 ; ### bcf T1CON,TMR1CS ; ### set clock source to Fosc/4 bsf T1CON,TMR1ON ; ### turn TMR1 on
;;*******************************************************************;Enable Timer1 interrupts, Peripheral Interrupts and Global
Interrupts;*******************************************************************
bsf STATUS,RP0 ; ### point to BANK1 bsf PIE1,TMR1IE ; ### enable TMR1 interrupts bsf INTCON,GIE ; ### enable Peripheral interrupts bsf INTCON,PEIE ; ### enable Global interrupts bcf STATUS,RP0 ; ### return to bank0
L b Q ti
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 66201ASP
Lab Questions
Question:
Was Timer 1 still running during the time it
took to service the Interrupt?
Answer:
Yes
Question:
What effect did this have on the value to be
placed to reload TMR1L and TMR1H? Answer:
Everything ± to be precise the latency of
reloading Timer1 should be considered.
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 67201ASP
Timer2 Block Diagram
Prescaler 1:1, 1:4, 1:16
COMPARATOR
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Postscaler
1:1 1:16
Fosc/4
Timer2 ON1 = Timer2 enabled
T2CKPS1 T2CKPS2 Scale
0 0 1:1
0 1 1:4
1 X 1:16
TMR2
TMR2OUTPUT
PR2
Timer2 Control Register (T2CON)
Timer2 Block Diagram
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 68201ASP
Timer2 Block Diagram
Prescaler 1:1, 1:4, 1:16
COMPARATOR
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Postscaler
1:1 1:16
Fosc/4
Timer2 ON1 = Timer2 enabled
T2CKPS1 T2CKPS2 Scale
0 0 1:1
0 1 1:4
1 X 1:16
TMR2
TMR2OUTPUT
PR2
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 SCALE
0 0 0 0 1:1
0 0 0 1 1:2
0 0 1 0 1:3
0 0 1 1 1:4
0 1 0 0 1:5
0 1 0 1 1:6
0 1 1 0 1:7
0 1 1 1 1:8
1 0 0 0 1:9
1 0 0 1 1:10
1 0 1 0 1:11
1 0 1 1 1:12
1 1 0 0 1:13
1 1 0 1 1:14
1 1 1 0 1:15
1 1 1 1 1:16
Timer2 Control Register (T2CON)
Timer2 Block Diagram
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 69201ASP
Prescaler 1:1, 1:4, 1:16
COMPARATOR
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Postscaler
1:1 1:16
Fosc/4
TMR2OUTPUT
1 1 1 1 0 1 1 01 1 1 1 1 0 0 01 1 1 1 0 1 1 11 1 1 1 0 1 0 1
1
PIR1
TMR2IFTimer2 Control Register (T2CON)
TMR2
PR2
Timer2 Block Diagram
Load PeriodRegister
Start Timer2
Counting
Flag set on firstmatch with
postscaler = 1:1
1 1 1 1 1 0 0 0
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 70201ASP
Timer2 InitializationTMR2 (Timer2 Counter)
0 0 0 0 0 0 0 0
T2CON (Timer2 Control)
PIR1 (Peripheral Interrupt Request)
TMR2IF
PIE1 (Peripheral Interrupt Enable)
TMR2IE
0
0
100 00 111
;Disable the Timer2 interrupts in the PIE1;register. Make sure the Timer2 interrupt;flag in PIR1 is cleared.
banksel PIE1 bcf PIE1,TMR2IE banksel PIR1 bcf PIR1,TMR2IF
;Setup T2CON register for Postscaler = 1:15,;Prescaler = 1:16, Timer2 off
movlw b¶01110010¶ movwf T2CON;Make sure the TMR2 register is clear
banksel TMR2clrf TMR2
;Load the Period register banksel PR2 movlw b¶10000000¶
movwf PR2;Start Timer2 incrementing banksel T2CON bsf T2CON,TMR2ON
;The Timer2 interrupt is disabled, do;polling on the Timer2 interrupt flag
btfss PIR1,TMR2IFgoto $-1
1
Postscaler = 1:15(TOUTPS<3:0>)
TMR2ON
Prescaler = 1:16(T2CKPS<1:0>)
1
PR2 (Period Register Timer2)
0 0 0 0 0 0 01
Flag is set
Timer2Incrementing
1 1 1 1 111 111 11
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 71201ASP v8.0 January 2007
Timer2 Lab
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 72201ASP
Timer2 Lab
The Goal of Lab 3 is to become familiar withthe following:
² Timer2 Clock Source
² Setting the Prescaler
² Setting the Postscaler ² Turning on Timer2
² Setting the Interrupt Enable bits needed for Timer2 to successfully generate an interrupt.
Lab Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 73201ASP
Lab Overview
Main ProgramInitialize PORT B
Set up Timer2Period,
Prescaler,Postscaler
Enable interrupts
NOP
Interrupt Vector Save Context
Increment counter the
number of timesTimer2 has interrupted
Output 3 LSBs of countto LEDs
Restore context
retfie
Lab Specifics
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 74201ASP
Lab Specifics
Code for this lab is inC:\RTC\201_ASP\Lab3-TMR2
Complete the following sections of code
² Set Timer2 prescaler to a value of 4 ² Set Timer2 postscaler to a value of 13
² Turn Timer2 on
² Configure the GIE and PEIE bits in the Interrupt
Control register (INTCON) ² Configure the Timer2 Interrupt Enable bit in the
Timer2 Configuration register (T2CON)
What you need to know
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 75201ASP
What you need to know
Special Function Registers (SFRs) neededfor this lab are: ² INTCON«(Interrupt Control)
² PIE1««..(Peripheral Interrupt Enable 1)
² PR2««...(Timer2 Period Register) ² T2CON«..(Timer2 Control)
With the Period register (PR2) set to 250,
the prescaler at 4, and the postscaler at13, Timer2 will interrupt every 13 ms(about 1/80 second) with a 4Mhz oscillator (Fosc/4 = 1Mhz).
Timer2 Lab Solution
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 76201ASP
Timer2 Lab Solution
;*****************************************************************
; configure Timer2 prescaler of 4, PR2 of 250 and a postscaler; of 13 and turn timer2 on.;*****************************************************************;
BANKSEL T2CON ; point to bank containing T2CON movlw 0x60 ; ### set TMR2 postscaler = 1:13 movwf T2CON ; ###
bsf T2CON,T2CKPS0 ; ### set TMR2 prescaler = 1:4 bsf T2CON,TMR2ON ; ### turn on TMR2
;*****************************************************************;Enable Timer2 interrupts, Peripheral and Global Interrupts;*****************************************************************
bsf STATUS,RP0 ; point to BANK1 bsf PIE1,TMR2IE ; ### enable TMR2 interrupts bsf INTCON,PEIE ; ### enable peripheral interrupts bsf INTCON,GIE ; ### enable global interrupts bcf STATUS,RP0 ; return to BANK0
Lab Questions
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 77201ASP
Lab Questions
Question:
Like Timer1, does Timer2 keep runningduring Interrupt latency?
Answer:
Yes it does!
Question:
Does the user have to account for the freerunning Timer2 in order to ensure a preciseinterrupt period?
Answer:
No, Interrupt occurs on match not overflow
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 78201ASP v8.0 January 2007
Capture/Compare/PWMModule
Capture/Compare/PWM
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 79201ASP
Capture/Compare/PWM(CCP) Overview
Capture ² Times the duration of an external event using an
input pin
Compare
² Changes an output pin or generates an interruptwhen a specific amount of time has passed
Pulse Width Modulation (PWM)
² Creates a reconfigurable, steady duty-cycle, square
wave output at a defined frequency ² Provides enhanced features for various bridge
connectivity
* Module interfaces with Timers 1 and 2
Capture/Compare/PWM
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 80201ASP
Capture/Compare/PWM(CCP) Overview
Capture ² Times the duration of an external event using an
input pin
Compare
² Changes an output pin or generates an interruptwhen a specific amount of time has passed
Pulse Width Modulation (PWM)
² Creates a reconfigurable, steady duty-cycle, square
wave output at a defined frequency ² Provides enhanced features for various bridge
connectivity
* Module interfaces with Timers 1 and 2
CCP MODE Timer Resource
Capture Timer 1
Compare Timer 1
PWM Timer 2
CCP Control Registers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 81201ASP
CCP Control Registers
P1M<1:0>These PWM output configuration bits are available for EnhancedCCP (ECCP) modules only. They provide half-bridge or full-bridgeoutput steering control.
CCP1<X:Y> PWM duty cycle 2 LSB¶s (8 MSB¶s located in CCPR1L)
CCP1M<3:0>CCP Mode Select Bits configure the module as Input Capture,Output Compare, or PWM
BIT FUNCTION
CCP1 Control Register (CCP1CON)
P1M1 P1M0 CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCP Control Register
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 82201ASP
P1M<1:0>These PWM output configuration bits are available for EnhancedCCP (ECCP) modules only. They provide half-bridge or full-bridgeoutput steering control.
CCP1<X:Y> PWM duty cycle 2 LSB¶s (8 MSB¶s located in CCPR1L)
CCP1M<3:0>CCP Mode Select Bits configure the module as Input Capture,Output Compare, or PWM
BIT FUNCTION
CCP1 Control Register (CCP1CON)
CCPxM3
CCPxM2 CCPxM1 CCPxM0 CCP Mode Selected
0 0 0 0 Capture/Compare/PWM off (resets CCP module)
0 0 0 1 Unused (reserved)
0 0 1 0 Compare mode, toggle output on match
0 0 1 1 Unused (reserved)
0 1 0 0 Capture mode, every falling edge
0 1 0 1 Capture mode, every rising edge
0 1 1 0 Capture mode, every 4th rising edge
0 1 1 1 Capture mode, every 16th rising edge
1 0 0 0 Compare mode, set output on match
1 0 0 1 Compare mode, clear output on match
1 0 1 0 Compare mode, generate software interrupt on match
1 0 1 1 Compare mode, trigger special event
1 1 x x PWM mode
P1M1 P1M0 CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCP Control Register
Capture Mode
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 83201ASP
CCPx
Capture Mode
TMR1H TMR1L
CCPRxH CCPRxL
Prescaler ÷1, 4, 16
Edge Detect
and
System Clock (Fosc)
P1M1 P1M0 CCP1X CCP1Y CCP1M3CCP1M2 CCP1M1 CCP1M0
CCPxCON
CCPxIF in PIRx
Single Buffered
Capture Mode
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CCPx
Capture Mode
TMR1H TMR1L
CCPRxH CCPRxL
Prescaler ÷1, 4, 16
Edge Detect
and
System Clock (Fosc)
P1M1 P1M0 CCP1X CCP1Y CCP1M3CCP1M2 CCP1M1 CCP1M0
CCPxCON
CCPxIF in PIRx
Single Buffered
CCPxM3 CCPxM2 CCPxM1 CCPxM0 MODE
0 1 0 0 Capture every falling edge0 1 0 1 Capture every rising edge
0 1 1 0 Capture every 4th rising edge
0 1 1 1 Capture every 16th rising edge
Capture Initialization
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 85201ASP
Capture InitializationTMR1H
TMR1ON
CCP1IF
TMR1L
0000000 0
0000000 0
PIR1
0
CCP1CON
T1CON
00000 0
1
TIMER1 INCREMENTING!!
00
0
CCPR1H
CCPR1L
11
1
Rising EdgeDetected!!
Current Timer1 Value
Captured!
;Turn off CCP module banksel CCP1CON
clrf CCP1CON;Make sure Timer1 is off
bcf T1CON,TMR1ON;Clear Timer1 registers
clrf TMR1Hclrf TMR1L
;Disable all interrupts for CCP
bcf PIR1,CCP1IF banksel PIE1 bcf PIE1,CCP1IE
;Set CCP1 pin for input bsf TRISC,2
;Set Capture for every 4th rising edge banksel CCP1CON movlw b¶00000110¶ movwf CCP1CON
;Start Timer1 incrementing bsf T1CON,TMR1ON
;Test the interrupt flag for capture btfss PIR1,CCP1IFgoto $-1
CCP1Pin
01111
1st2nd3rd4th
Compare Mode
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YES YES CCPx
Special Event Trigger
Compare Mode
CCPxIF in PIRx
OUTPUTLOGIC
P1M1 P1M0 CCP1X CCP1Y CCP1M3CCP1M2 CCP1M1 CCP1M0
TMR1H TMR1L
COMPARATORDoes
TMR1H:TMR1L =
CCPRxH:CCPRxL
??
NO
CCPRxH CCPRxL
CCP1CON
Compare Mode
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YES YES CCPx
Special Event Trigger
Compare Mode
CCPxIF in PIRx
OUTPUTLOGIC
P1M1 P1M0 CCP1X CCP1Y CCP1M3CCP1M2 CCP1M1 CCP1M0
TMR1H TMR1L
COMPARATORDoes
TMR1H:TMR1L =
CCPRxH:CCPRxL
??
NO
CCPRxH CCPRxL
CCPxM3 CCPxM2 CCPxM1 CCPxM0 MODE
1 0 0 0 Set output on match (CCPxIF is set)
1 0 0 1 Clear output on match (CCPxIF is set)
1 0 1 0Generate software interrupt on match(CCPxIF is set CCP1 pin unaffected)
1 0 1 1
Trigger special event
(CCPxIF is set, CCP1 resets TMR1 or TMR2 and starts an A/D conversion if enabled)
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PWM Mode
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 89201ASP
PWM Mode
Generates a Pulse-Width Modulated(PWM) signal on the CCP1 and CCP2 pins
Duty cycle, period and resolution
determined by the following registers
Period Register PR2
Timer2 ControlT2CON2 Duty Cycle RegistersCCPRxL
2 CCP Control RegistersCCPxCON
DescriptionRegister
PWM Block Diagram
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 90201ASP
PWM Block Diagram
CCPR1L CCP1<X:Y>
CCP1pin
CCPR1H LATCH
TMR2 incrementing
PR2
Latch
CCP1 Output PinCOMPARATOR
COMPARATORTMR2 = PR2
DUTY CYCLE VALUE
TMR2 = CCPR1H
DOUBLEBUFFER
R
S
8
8
(1)
Note (1): TMR2 is concatenated with the2-bit FOSC, or 2-bits from Prescaler to create 10-bit time base
10
10
10
Period 1
10
PeriodStart
TMR2 Reset to 0¶sTMR2 Reset to 0¶s
TMR2 = PR2
DUTY CYCLE VALUE
TMR2 = CCPR1H
0
TMR2 = PR2
Period 2
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Pulse Width Modulation(PWM) Lab
PWM Lab Objectives
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 93201ASP
PWM Lab Objectives
Become familiar with the CCP moduleconfiguration and operation in PWM mode
Gain additional exposure to Timer2
configuration
PWM Lab Overview
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PWM Lab Overview
The PWM waveform is output on theCCP1 pin (RC2) that will emit a tone onthe PICdem2 plus onboard buzzer.
When the lab is completed, a 50% dutycycle at a period of 256/(Fosc/4) willdrive the buzzer.
PWM Lab Overview
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PWM Lab Overview
Load PR2 value
Set up RC2 as output pin
Load CCPR1L for 50% duty cycle
Configure CCP as 8-bit PWM
NOP
Turn on Timer2 w/ 1:1 pre scaler
Main Code
PWM Lab Specifics
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PWM Lab Specifics
Code for the lab is inC:\RTC\201_ASP\Lab4-PWM
Complete the following sections
² Configure PORTC pin 2 ( CCP1) as an output ² Set CCP in PWM mode
² Clear CCP1X and CCP1Y (8-bit PWM)
² Configure Timer2 with 1:1 pre-scaler
What you need to know
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What you need to know
The code to load PR2 (Timer2) and to set a50% duty cycle has been provided. These
values can be seen in the code
The CCP1 pin is RC2 (Pin 2 of PORTC) onthe PIC16F877
Registers needed to complete this lab are:
² TRISC
² T2CON
² CCP1CON
PWM Lab Solution
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 98201ASP
PWM Lab Solution;*****************************************************************; Set CCP1 as an output
;***************************************************************** bcf TRISC,2 ; ### config CCP1 pin PORTC<2> as output
bcf STATUS,RP0 ; point to BANK0 movlw 0x80 ; establish duty cycle @ 50% movwf CCPR1L
;*****************************************************************; Put CCP1 module in PWM mode.;*****************************************************************
movlw 0x0C ; ### configure CCP for PWM movwf CCP1CON ; ###
;*****************************************************************; Configure Timer2 pre and post scale of 1:1 and turn Timer2 on;*****************************************************************
bsf T2CON,TMR2ON ; ### turn on TMR2
PWM Lab Questions
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 99201ASP
ab Quest o s
Question:Why didn¶t we have to enable the interrupts
for the PWM to work?
Answer:
PWM will run concurrently with the PICmicro
MCU without slowing the processor down
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 100201ASP v8.0 January 2007
Output CompareLab
Output Compare Lab
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p p
Goals of the lab are to gain experience withthe following:
² Setting up the CCP for Output Compare
² Configure the Special Event Flag to reset Timer1
² Configure the CCP to generate an Interrupt onTimer1 overflow
² Using an Interrupt Vector to modify the intervalbetween Interrupts
Compare Lab Overview
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p
This lab configures the CCP into output compare
mode driven by Timer1
An Interrupt is used to change the sound of thebuzzer
During the Interrupt Service Routine (ISR):
² The RC2/CCP1 pin (connected to buzzer) is toggled
² The ISR period is reduced: The Compare Register (CCPR1L) is decremented
The Timer1 count registers are reset
The combination of a reduced period and theCCPR1L roll-over will cause the buzzer to emit achirping sound
Compare Lab Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 103201ASP
p
Save Context
Toggle CCPOutput Pin
Clear IF
DecrementCCPR1L
Configure CCP asOutput Compare
Initialize PORT C
Initialize Timer1
Turn on timer1
NOP
RETFIE
Interrupt Vector Main Program
ResetTimer1
DrivesBuzzer
Compare Lab Specifics
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p p
The code for this lab is inC:\RTC\201_ASP\Lab5-CCP
Complete the following sections:
² Configure the CCP as an Output Comparethat sets the Special Event Flag and CCP1IF
² Configure Timer1 with a clock source of Fosc/4 and a pre-scaler of 1:8
² Configure Special Function Registers toallow the CCP interrupt to occur
What you need to know
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 105201ASP
What you need to know
The registers needed to complete this lab are: ² INTCON (Interrupt Control)
² T1CON (Timer1 Control)
² CCP1CON (CCP1 Control)
² PIE1 (Peripheral Interrupt Enable)
The Interrupt Vector has been provided
The Value of CCPR1L will ³rollover ́ from 0 to0xFF and continue to decrement
Compare Lab Solution
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 106201ASP
p
;
; Set CCP1CON to Output Compare mode with Special Event Trigger; to clear the Timer 1 register pair on a match;****************************************************************
movlw 0x0B ; ### value for CCP1CON movwf CCP1CON ; move to CCP1CON
;; Configure Timer 1 for Fosc/4 operation. 8:1 Prescaler
;;**************************************************************** movlw 0x30 ; ### value for TMR1 movwf T1CON ; ### move to TMR1 control register
;; Enable Timer 1 interrupts, Peripheral Interrupts and ; Global Interrupts
;**************************************************************** bsf PIE1,CCP1IE ; ### enable CCP1 interrupt bsf INTCON,PEIE ; ### enable peripheral interrupts bsf INTCON,GIE ; ### enable global interrupts
Lab Question
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 107201ASP
Question:
The PWM did not require an interrupt in order
to work. Do we need an interrupt to operate in
output compare mode?
Answer:
Not necessarily
² Peripherals always set their associated interrupt
flag, so you have the choice of polling or directly responding to the interrupt.
² The choice is based on the need of your
application.
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 108201ASP v8.0 January 2007
Comparators
Comparator Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 109201ASP
p
Comparator Module:
² Compares analog input voltage to a referenceand outputs a digital result
Vin
Vout
Vref
Comp
Analog Input
(Vin)
Reference Voltage(Vref )
Output
(Vout) +
-
Comparator Reference Voltage
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 110201ASP
Voltage Reference can be either:
² External from a device pin ² Internally generated with the Voltage Reference
Module Provides 16 selectable voltages from 0 to 75% of VDD
² Some devices can also scale VREF+ and VREF-
Some devices also have a fixed reference (0.6V) ² Independent of VDD
VREF+
VDD
VREN
VREF-
8R R R R R
8R
CVREF
VROE
CVREF
To Comparatorsand ADC Module
4 VR<3:0>
15
0
VRSS = 1
VRSS = 0
VRSS = 1
VRSS = 0
VRR
Comparator Interrupts
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 111201ASP
An Interrupt occurs when the comparator output changes ² Some devices share one flag for both
comparators
² Some devices have independent flags Must read the comparator output before
clearing interrupt flags ² Outputs found in the comparator control
register (CMCON or CMxCON0) ² Resets the output mismatch condition
Comparators and Sleep Mode
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 112201ASP
Comparators remain active in Sleep
² A Comparator output change will wake-upcore
After wake-up, the instruction followingthe SLEEP instruction or an InterruptService Routine (ISR) is executed
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 113201ASP v8.0 January 2007
Analog-to-DigitalConverter (ADC)
ADC Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 114201ASP
Analog-to-Digital Converter Module ² Converts analog input signal into an 8 or 10-bit
binary value
² Selectable internal or external reference voltage
² Interrupt can be generated after conversion iscompleted
The interrupt can wake the PICmicro from SLEEP
ADCAnalogInput
DigitalOutput
ADC Control Registers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 115201ASP
ADCS1 ADCS0 CHS2 CHS1 CHS0 ADON
The ADC implements two control registers ² ADCON0 and ADCON1
² Devices with > 8 analog inputs do not have same bitsshown below
ADC Control Register 0 (ADCON0)
ADCS<1:0> A/D Conversion Clock Select bits
Use with ADCS2 in ADCON1
CHSx bits Analog Channel Select bits
GO/DONE 1 = A/D Conversion in progress
0 = A/D Conversion is completed
ADON Enables the ADC module
BIT FUNCTION
GO/DONE
ADC Control Registers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 116201ASP
ADFM ADC Result Registers Format bit
1 = Right Justified, 0 = Left Justified
ADCS2 A/D Conversion Clock Select bit
Use with ADCS<1:0> in ADCON0
PCFG<3:0> Port Configuration Bits
Configures I/O as analog or digital
BIT FUNCTION
ADC Control Register 1 (ADCON1)
The ADC implements two control registers ² ADCON0 and ADCON1
² Devices with > 8 analog inputs do not have same bitsshown below
ADFM PCFG3 PCFG0PCFG2 PCFG1ADCS2
ADC Result Registers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 117201ASP
g
10 bit ADC result in is placed in two registers ² ADRESH and ADRESL
² Left or Right Justified Determined by Format Select bit (ADFM) in ADCON1 register
MSB LSB
MSB LSB
ADRESH
Left Justified (ADFM = 0)
Right Justified (ADFM = 1)
ADRESL
ADRESH ADRESL
ADC Module Diagram
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 118201ASP
ADC
HoldingCapacitor
Conversionclock scaler Fosc
VREF+
pin
VREF-
pin
Vss
ADRESH ADRESL
ADCON0
ADCS1 ADCS0 CHS2 CHS1 CHS0 ADONGO/DONE
ADCON1
ADFM PCFG3 PCFG1 PCFG0PCFG2ADCS2
Conversion CompleteStart Conversion
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7Left Justified Right Justified
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
ADC Module Diagram
PCFG
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 119201ASP
ADC
HoldingCapacitor
Conversionclock scaler Fosc
VREF+
pin
VREF-
pin
Vss
ADRESH ADRESL
ADCON0
ADCS1 ADCS0 CHS2 CHS1 CHS0 ADONGO/DONE
ADCON1
ADFM PCFG3 PCFG1 PCFG0PCFG2ADCS2
Conversion CompleteStart Conversion
0 0 0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
01
Left Justified Right Justified
Port Config Bits
10
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
VddAN7 AN6 AN5 AN4 AN1 AN0AN3 AN2PCFG<3:0>
Timing Considerations for ADC
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 120201ASP
When an A-to-D channel is selectedtime must be taken for the holdingcapacitor to charge
All 10 bit conversions take 11 cycles tocomplete
User must select the appropriate ADC
clocking based on the system clockfrequency
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 121201ASP v8.0 January 2007
Analog-to-DigitalConversion LAB
ADC Lab
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 122201ASP
This Lab will familiarize you with: ² Setting up the ADC module
² Operating a peripheral from the ³Main´ program, not an interrupt vector
² Using the value read from one peripheral(ADC) to drive another peripheral (CCP inPWM mode)
ADC Lab Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 123201ASP
Configure Timer 2
Configure andTurn on ADC
Configure CCP for PWM
Configure PORT C
Enable interrupts
Main Program
Continued onnext page
ADC Lab Overview (cont.)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 124201ASP
Output 4 LSBs of ADC value to LEDs
Start ADC
Put ADC value inCCPR1L
ADC done?
TMR2IF=1
Main Loop NO
YES
NO
YES
Continued fromPrevious Page
ADC Lab Specifics
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 125201ASP
Complete the following sections of codein the project C:\RTC\201_ASP\Lab6-ADC
² Configure the ADC to return a left justifiedvalue
² Set ADC Conversion Clock to FOSC /32
² Turn on ADC unit
² Complete the code to start an ADC and waitfor the conversion to finish in the maincontrol loop
What you need to know
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 126201ASP
This lab does not do the ADC conversion inan interrupt routine. We will use a polling
method.
Writing the value of the ADC conversion into
CCPR1L will change the duty cycle of the
buzzer
ADCON1 and ADCON0 special function
registers are used to complete this lab
ADC Solution
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 127201ASP
;*************************************************************************; Configure ADC: Channel 0, left justified, Tad = 8 * Tosc, turn on ADC
;*************************************************************************clrf ADCON0 ; ### ensure default channel is set to channel 0 bsf ADCON0,ADCS1 ; ### set Tad = Fosc/4 bsf ADCON0,ADON ; ### turn on ADC bsf STATUS,RP0 ; ### point to BANK1 movlw 0x0E ; ### left justify, configure AN0 analog movwf ADCON1
;
; Enable Timer 2 interrupts, Peripheral Interrupts and Global Interrupts;
bsf PIE1,TMR2IE bsf INTCON,GIE bsf INTCON,PEIE bcf STATUS,RP0 ; return to BANK0
;;*************************************************************************; add three lines of code to start the ADC conversion and wait for the; conversion to complete;*************************************************************************
bsf ADCON0,GO ; ### start ADC conversion btfsc ADCON0,GO ; ### Is the conversion done?goto $-1 ; ### no: loop until done
ADC Lab Question
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 128201ASP
Question:Instead of waiting for TMR2IF to be set in
the main program, could we start the ADC
from within an interrupt routine?
Answer:
YES
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 129201ASP v8.0 January 2007
ADDRESSABLE UniversalSynchronous AsynchronousReceiver Transmitter
(AUSART)
AUSART Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 130201ASP
Serial I/O communications peripheral ² Sometimes called Serial Communications
Interface (SCI)
Main Functions: ² Can be synchronous or asynchronous
² Can receive and transmit Full-duplex asynchronous transmit and receive Half-duplex synchronous master and slave
Most common use ² RS-232 communications to a PC serial port
Needs driver for RS-232 level shifter Enhanced (EUSART) features allow interface
with a Local Interconnect Network (LIN) bussystem
AUSART Registers
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 131201ASP
Baud rate generator registers ² SPBRG (8 bit for AUSART) ² SPBRG and SPBRGH (16 bit for EUSART)
Transmit status and control ² TXSTA
Receive status and control ² RCSTA
Transmit data register
² TXREG
Receive data register ² RCREG
TXSTA Register
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 132201ASP
Bit Function
CSRC Clock Source Select
1 = Master Mode (clock generated internally from BRG)
0 = Slave Mode (clock from external source)
CSRC TX9 TXEN SYNC SENB BRGH TRMT TX9D
TX9 Ninth bit transmission enableTXEN Transmit Enable bit, 1 = Tx enabled, 0 = Tx disabled
SYNC AUSART Mode , 1 = Synchronous Mode, 0 = Asynchronous Mode
SENB For EUSART only1 = Send sync break character bit0 = Sync break transmission is completed
BRGH Baud Rate Select, 1 = High Speed, 0 = Low Speed
TRMT Transmit Shift Register (TSR) status
1 = TSR empty, 0 = TSR is full
TX9D Ninth bit of transmit data
RCSTA Register
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 133201ASP
Bit Function
SPEN Serial Port Enable
1 = Serial port enabled (configures RX /DT and TX /CK pins as serial port pins)
0 = Serial port disabled
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
RX9 1 = Enable 9-bit data reception, 0 = 8-bit data
SREN Synchronous mode (Master), 1 = enable single Rx, 0 = disable single Rx
CREN Continuous Receive Enable, 1 = enable, 0 = disable
ADDEN Address Detect Enable bit
1 = enable (enable interrupt and load the Rx buffer when RSR<9> is set)
0 = disable and use 9th
bit for parity
FERR 1 = framing error occurred (Stop bit not detected)
OERR 1 = Overrun error occurred (FIFO was still full when other data wasloaded)
RX9D Ninth bit of received data
Transmit Block Diagram
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 134201ASP
TX9D
SPEN
Baud RateGenerator
TXENMSB LSB
TXREG
Transmit ShiftRegister (TSR)
TX9
DATA BUS
TXIF
InterruptTXIE
Pin Buffer and Control
TRMT
Set TXIF Clear TXIF
Enables SerialPort
Set TRMT bitIndicates shift register is empty
Clear TMRT bitTSR has data in it
Ninth data bit
TX /DTpin
Receive Block Diagram
Enable Serial Port
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 135201ASP
Pin Buffer and Control
SPEN
DataRecovery
Baud RateGenerator
STOP START
RX9
Data Bus
RX9DRCIE
Interrupt
RCREG
Receive Shift Register (RSR)RX /DTpin
FIFO
STOP START
Set RCIF flagClear RCIF flag
ab e Se a o t
RCIF
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 136201ASP v8.0 January 2007
MASTER SYNCHRONOU
SSERIAL PORT (MSSP)MODULE
MSSP Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 137201ASP
The MSSP module can operate in one of two modes:
² SPI (Serial Peripheral Interface) 3 pins are used
² Serial Data Out (SDO)
² Serial Data In (SDI)
² Serial Clock (SCK)
² I2C (Inter-Integrated Circuit) Full Master mode Slave mode (with general address call)
2 pins are used ² Serial Clock (SCL)
² Serial Data (SDA)
The MSSP Control Register (SSPCON) determineswhich mode you are in.
We will cover I 2 C mode only
I2C Conditions
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 138201ASP
Conditions :
² START (S)
² STOP (P)
² ACKNOWLEDGE (A)
² RESTART (R)
² NEGATIVE or NOT-ACKNOWLEDGE (N)
SDA
SCL
SDA pulled LOWwhile SCL isstill HIGH
SDA releasedwhile SCL isstill HIGH
SDA goes LOW during9th clock pulse of SCL
Stop condition quickly followedby a Start conditionRecipient does not drive SDALOW
External IC EEPROM Read
+5V
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 139201ASP
EEPROM
PIC
SCL
SDA
LISTEN LISTEN LISTEN
READMODEGOTO
ADDRESSSTOPDATA
MASTER
SLAVESSTART DATASLAVEADDRESS
BUSY BUSY
WRITEMODE
ACKEEPROMMEMORYADDRESS
RESTARTNACKSTOPACK
MSSP Control Registers(I2C mode)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 140201ASP
(I C mode)
SMP Slew Rate Control bit
CKE Not used in I2C mode
D/A Last byte Rx/Tx was data or address
SMP CKE D/A P S R/W UA BF
CONTROL BITS DETECTION BITS (FLAGS)
P Stop Condition Detected
S Start Condition DetectedR/W Slave :READ/WRITE or Master = transmit in progress
UA Address needs to be updated
BF The SSPBUF register is full
BIT FUNCTION
1 of 3: MSSP Status Register (SSPSTAT)
MSSP Control Registers(I2C mode)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 141201ASP
(I C mode)
SMP Slew Rate Control bit
CKE Not used in I2C mode
D/A Last byte Rx/Tx was data or address
SMP CKE D/A P S R/W UA BF
CONTROL BITS DETECTION BITS (FLAGS)
P Stop Condition Detected
S Start Condition DetectedR/W Slave :READ/WRITE or Master = transmit in progress
UA Address needs to be updated
BF The SSPBUF register is full
BIT FUNCTION
1 of 3: MSSP Status Register (SSPSTAT)
MSSP Control Registers(I2C mode)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 142201ASP
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
WCOL Write Collision Detected
CKP Enables clock
SSPOV A write to the SSPBUF before previous value processed
SSPEN Enables MSSP module
SSPM3 Mode Select Bit
SSPM2
SSPM1
SSPM0
BIT FUNCTION
Mode Select bits
(I C mode)
2 of 3: MSSP Control Register 1 (SSPCON)
CONTROL BITS DETECTION BITS (FLAGS)
MSSP Control Registers(I2C mode)
SSPM3 SSPM2 SSPM1 SSPM0 Mode
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 143201ASP
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
WCOL Write Collision Detected
CKP Enables clock
SSPOV A write to the SSPBUF before previous value processed
SSPEN Enables MSSP module
SSPM3 Mode Select Bit
SSPM2
SSPM1
SSPM0
BIT FUNCTION
Mode Select bits
(I C mode)
2 of 3: MSSP Control Register 1 (SSPCON)
CONTROL BITS DETECTION BITS (FLAGS)
0 0 0 0 SPI Master mode, clock = FOSC/4
0 0 0 1 SPI Master mode, clock = FOSC/16
0 0 1 0 SPI Master mode, clock = FOSC/64
0 0 1 1 SPI Master mode, clock = TMR2 output/2
0 1 0 0 SPI Slave mode, clock = SCK pin, SS pin control enabled
0 1 0 1 SPI Slave mode, clock = SCK pin, SS pin control disabled,SS can be used as I/O pin
0 1 1 0 I2C Slave mode, 7-bit address0 1 1 1 I2C Slave mode, 10-bit address
1 0 0 0 I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 I2C firmware controlled Master mode (Slave idle)
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 I2C Slave mode, 7-bit address with Start and Stop bitinterrupts enabled
1 1 1 1 I2C Slave mode, 10-bit address with Start and Stop bitinterrupts enabled
MSSP Control Registers(I2C mode)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 144201ASP
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
GCEN Generates an interrupt when a call is received (slave mode)
ACKEN Initiate ACK/NACK condition (Transmits ACKDT bit)
ACKSTAT 0 = Acknowledge received from slave (transmit mode)
ACKDT 0 = ACK 1 = NACK (receive mode)
RCEN Enables receive mode
PEN Initiates a STOP condition
RSEN Initiates a RESTART condition
SEN Initates a START conditionSEN Initiates a START condition
BIT FUNCTION
( )
3 of 3: MSSP Control Register 2 (SSPCON2)
CONTROL BITS DETECTION BITS (FLAGS)
MSSP Control Registers(I2C mode)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 145201ASP
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
GCEN Generates an interrupt when a call is received (slave mode)
ACKEN Initiate ACK/NACK condition (Transmits ACKDT bit)
ACKSTAT 0 = Acknowledge received from slave (transmit mode)
ACKDT 0 = ACK 1 = NACK (receive mode)
RCEN Enables receive mode
PEN Initiates a STOP condition
RSEN Initiates a RESTART condition
SEN Initates a START conditionSEN Initiates a START condition
BIT FUNCTION
( )
3 of 3: MSSP Control Register 2 (SSPCON2)
CONTROL BITS DETECTION BITS (FLAGS)
Tx/Rx Buffer (SSPBUF)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 146201ASP
Buffer register containing Tx and Rx data ² SSPBUF interfaces to a shift register (SSPSR) for
shifting data in or out
When full, the Buffer Full (BF) bit in theSSPSTAT register is set
Any write to the SSPBUF register duringTx/Rx of data will be ignored, and the write
collision detect bit (WCOL) of the SSPCONregister will be set
I2C Address Register (SSPADD)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 147201ASP
(SSPADD) Slave mode:
² Contains the slave address of the PIC
² Compared against the received value
Master mode: ² Used to calculate the clock speed(BAUD rate) of the I2C system.
)1(4 v SPADD
FoscBAUD RATE =
*NOTE: FOSC is the frequency of the oscillator not the Instruction Clock TCY
MSSP Interrupts
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 148201ASP
The MSSP interrupt flag (SSPIF) is set inthe PIR1 register with the following events:
² START condition
² STOP condition ² Tx or Rx complete
² Acknowledge transmit
² RESTART condition
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 149201ASP v8.0 January 2007
I2C Based Temp Sensor Lab
I2C Based Temp Sensor Lab Objective
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 150201ASP
Lab Objective
Configure some MSSP control registers toenable I2C communication to the I2C basedTemp sensor on the PICDEM 2 Plus board.
Temperature reading (lowest 4 bits) will bedisplayed on the LEDs.
I2C Lab Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 151201ASP
This lab configures the MSSP as an I2CMaster
The TC74 Temperature Sensor is then
read by the MSSP module
The temperature reading is then sent toPORTB to be displayed on the 4 LEDs
I2C Lab Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 152201ASP
Configure I/0s
Configure MSSP
Initiate I2C start condition
Send Temp Sensor Address
Read Temperature
Main Code
Display Temp LSB on PORTB LEDs
Loop
I2C Lab Specifics
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 153201ASP
Code for the lab is in
C:\RTC\201_ASP\Lab7-I2C
Complete the following sections: ² Disable the slew rate control
We¶ll be using I2C standard rate (100KHz)
² Configure the MSSP to operate as an I2Cmaster and enable the data (SDA) and
clock (SCL) pins ² Start the data transfer and check for
when it has completed
What you need to know
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 154201ASP
Slew rate control is found in theSSPSTAT register
Registers needed to complete thislab are:
² SSPSTAT
² SSPCON
² SSPCON2
I2C Lab Solution
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 155201ASP
;--------------------------------------------------------------; set the slew rate and baud rate for 100 kHZ operation
BANKSEL SSPSTAT ; ### point to correct BANK for SSPSTAT bsf SSPSTAT,SMP ; ### Set for standard speed slew rate
;--------------------------------------------------------------; Configure as I2C master with Fosc/4 Clock source
BANKSEL SSPCON bsf SSPCON,SSPM3 ; ### set to I2C master mode with
; Fosc/4 clock source bsf SSPCON,SSPEN ; ### Enable SDA and SCL pins to
; operate in I2C mode
;--------------------------------------------------------------
BANKSEL SSPCON2 ; Initiate a START condition bsf SSPCON2,SEN ; ### set the SEN bit btfsc SSPCON2,SEN ; ### is it finished?goto $-1 ; no: test again
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 156201ASP v8.0 January 2007
Multiple InterruptLab
Multiple Interrupts Lab
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 157201ASP
This Lab involves: ² Dealing with 2 (or more) concurrent interrupts
² Determining the source of an interrupt
² Deciding which interrupt request will beserviced first
Lab Overview
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 158201ASP
Setup PORTB and enableExternal Interrupts on
³S3´as in Lab 1
Enable Timer1 and
PORTC as In Lab 6
Set up CCP as OutputCompare just as in Lab 6
Main Program
Continued on next slide
NOP
Lab OverviewInterrupt Service Routines
INT ISR CCP ISR
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 159201ASP
Toggle variableCalled
³push_flag´
Clear IF
Clear IF
Call ³debounce´Delay routine
Put -1 in WREG
Put 0 in WREG
Add WREG toCCPR1L
push_fla
gSet ?
INT_ISR CCP_ISR
Return to Main
Return to Main
Lab Overview (cont.)
S
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 160201ASP
Did CCPgenerate the
interrupt?
Did INT generatethe interrupt?
Go to CCPservice routine Service ExternalInterrupt
Interrupt Handler
Savecontext
YES
YES
NO
NO
Return to Main
Lab Specifics
L b i f d i
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 161201ASP
Lab is found in:
² C:\RTC\201_ASP\Lab8-MXINT
The two Interrupt Service Routines (ISRs)are provided:
² INT_ISR ² CCP_ISR
Complete the following sections of code
² When an interrupt occurs, determine the causeand transfer control to the appropriate ISR
² Set the Special Function Registers (SFRs) toenable INT and CCP1 Interrupts to occur
What you need to know for Lab
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 162201ASP
INTCON, and PIR Special FunctionRegisters are used in this lab
Lab Solution
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 163201ASP
Int_Service_Routine
call save_regs; ; save W, STATUS, & PCLATH
btfsc INTCON,INTF ; ### test for INTE interrupt request
goto INTE_ISR
btfsc PIR1,CCP1IF ; ### test for CCP interrupt requestgoto CCP_ISR
Finish_Int ; restore W, STATUS & PCLATH
call Restore_Regs
retfie
Lab Solution ( cont.)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 164201ASP
bsf PIE1,CCP1IE ;### enable CCP1 interrupt
bsf INTCON,INTE ;### enable INTE interrupt
bsf INTCON,GIE ;### enable global interrupts
bsf INTCON,PEIE ;### enable peripheral interrupts bcf STATUS,RP0 ; return to BANK0
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Lab Questions (cont.)
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 166201ASP
Question:
How can this silence be eliminated and the
buzzer continue to run?
Answer:1. Capture S3 in ³Main´ and call ³debounce´
while GIE is set
2. Use a timer to accomplish the delay3. Re-enable interrupts during the INT ISR
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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 167201ASP v8.0 January 2007
201ASP Wrap-Up
Peripherals Class Wrap-up
Today we covered the following
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 168201ASP
Today we covered the following
peripherals on the Mid-Range family ² I/O ports
² Interrupt structure and processing
² Timers (timer0, timer1, timer2) ² CCP Module ( Output Compare, Input Capture,
PWM)
² Comparators and Analog-to-Digital Converters
Voltage Reference
² AUSART ± Serial Port
² I2C using the MSSP module
Final Word
This discussion has followed the standard
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 169201ASP
This discussion has followed the standard
Microchip datasheet flow:
Overview of Peripheral
Register Descriptionand Configuration
Enhanced or Special Features
*Packaging and Electrical Specifications are at the endof the datasheet
Use these sections to: Develop logical flow charts or
pseudo-code (Avoid Spaghetti
Programming!!)
Other Tips: Comment your code thoroughly Choose descriptive names
for user defined registers
Resources
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© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 170201ASP
Visit www.microchip.com for: ² 24/7 technical support
² Application Notes
² Web Seminars
² Code examples ² Datasheets
² and Much More!
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