chapter 0. design of asic and socsoc.yonsei.ac.kr/class/material/logic/ch0.pdf · ¾cores replacing...

Chapter 0. Design of ASIC and SoC

0 - 2

ASIC Design

◈ASIC Design Flow

Design entry and analysis

Technology optimization

Design verification

Layout

0 - 3

ASIC Design Flow

Front-End

Methodology Verification & Sign-off

Layout & Physical Verification

Key Milestones

0 - 4

Design Views

◈ HDL views

Technology independent

◈ Netlist views

Technology dependent

◈ Physical views

0 - 5

ASIC Design Flow

Front-End

Methodology Verification & Sign-off

Layout & Physical Verification

Key Milestones

0 - 6

Design Entry and Analysis

◈Two principal design description methods

HDL (used for > 50K gates) : VHDL / Verilog

Schematic capture (small design, less often used)

◈Design analysis

Simulation : to make sure the function is correct

HDL simulators

0 - 7

Design Simulation

0 - 8

ASIC Design Flow

Front-End

Methodology Verification & Sign-off

Layout & Physical Verification

Key Milestones

0 - 9

Logic Synthesis

Netlist Description

(Verilog, VHDL, EDIF)

HDLDescription(Verilog or

VHDL)

Design Constraints

(Timing, Power, Area)

Logic Synthesis

ASIC Vendor Synthesis

Library

TechnologyIndependent

Input

TechnologyDependent

Output

0 - 10

Test Insertion

◈Inserts structures into design to enable a complete and efficient manufacturing test

0 - 11

Clock Planning

◈Impossible to use an ideal clock to drive all latches

Routability

Circuit drive strength

Clock latency and skew

◈Clock planning inserts the clock network (Clock tree / repowering tree)

0 - 12

Clock Planning

0 - 13

ASIC Design Flow

Front-End

Methodology Verification & Sign-off

Layout & Physical Verification

Key Milestones

0 - 14

Functional Verification

◈Gate level simulation

Make sure the function is not altered or corrupted by the synthesis process

0 - 15

Formal Verification

◈Achieves the same purpose as gate level simulation

◈Approach is different:

Breaks a design down into a set of Boolean/logic expression

Check the Boolean/logic equivalence

Comparison is exhaustive and fast than simulation

0 - 16

Formal Verification

0 - 17

Timing Verification

◈Timing closure : to determine if the design meets the performance target

◈Static timing analysis predicts the timing behavior of a hardware design before manufacture and test

◈It seeks to verify that a signal leaving a storage elements (SE) or primary input (PI) arrives in time and can be latched at next SE or primary output (PO)

0 - 18

Power Estimation

◈Verify the power consumption based on the gate level netlist

◈Spreadsheet method

0 - 19

ASIC Design Flow

Front-End

Methodology Verification & Sign-off

Layout & Physical Verification

Key Milestones

0 - 20

Layout – Routing

0 - 21

Layout (Physical Design)

◈Placement & Routing

Determine the position and interconnect of each circuits on a die

◈Back-annotation

Extracting timing information from layout for static timing analysis

0 - 22

Layout (Physical Design)

0 - 23

SoC (System-on-Chip)

◈Emergence of Very large transistor counts on a single chip

◈Mixed technologies on the same chip

◈Logic, Analog, Memory, ProcessorCreation of Intellectual Property (IP)

◈Reusable core-based designCores replacing standard parts, such as DSP, DRAM, MCU, Flash, and FPGA

◈Today’s chip is tomorrow’s core

0 - 24

SoC (System-on-Chip)

0 - 25

SoC Design Trend

0 - 26

SoC Design Trend

0 - 27

Benefits of Using SoC

◈Reduced size

◈Reduced overall system cost

◈Lower power consumption

◈Increased performance

0 - 28

SoC Design Flow

0 - 29

SoC Co-Design Flow

0 - 30

IP Core types

◈Hard Core(Technology dependent layout)

Predictable area and performance

Lack flexibility

◈Soft Core(RTL)

leave much of the implementation to the designer

Flexible and process-independent

◈Firm Core(Netlist)

◈Each type of core has different modeling and test requirements

0 - 31

DFT (Design-For-Testability)

◈Design and Test become closer

Design Test

Design Test

DesignTest

DesignTest

Pre 90’

Early 90’

Mid 90’

Late 90’

IncreasingIntegration

0 - 32

DFT (Design-For-Testability)

◈ The test process is to provide a measure of the quality of a semiconductor product

◈ DFT is to place the hardware to enable the ability to conduct the quality measurement

◈ Test logic may be addedTo increase the test coverageTo reduce the time it takes to qualify the partTo reduce the cost-of-test

◈ AdvantagesHaving the ability to measure the quality level deterministicallyMaking it easier to generate the necessary vectorsAllowing the cost of test to be reduced in all environments

◈ DisadvantagesNegative impacts on chip design (power, area, timing, pin)It adds tasks and risk to the design scheduleIt adds work and complication to the design methodology flow

0 - 33

SoC Test

RF/AnalogCore

User Defined

Core

User DefinedCore

DRAM

IP

ROM

IP

IP

UDL

BIST Mem BIST Test AccessSoC Test Controller

IO P

ad

IO P

ad

Low costexternal ATE

• Memory test algorithm• Memory BIST, BISR

• Testable design

• Analog Fault modeling• Mixed signal Built-In Self Test

• Built-In Self Calibration

• Testable core design• Logic BIST• Test reuse• Hierarchical testing

• Core access architecture• Parallel access & bypass• Core isolation

• IP-system test interface

• Test spec.• Test hardware

control• Test

scheduling

• Automatic test pattern • Fault simulation• Testability measure• Scan insertion & synthesis• BIST circuit synthesis• Boundary scan insertion & synthesis

Test Automation

0 - 34

Scan Testing

◈ Scan is a test methodology that allows one to control and observe all internal nodes in a synchronous design

◈ Application for finite state machines◈ Combinational and sequential elements tested separately

logic Test◈ Two mode operation◈ Normal mode◈ Test mode◈ Advantage

Structured design is possibleCan use combinational ATPGSignificant reduction of test generation timeHigh fault coverage, typically 99.5 Ease of fault diagnosis

◈ DisadvantageAdditional circuitry is added to FFPerformance penaltyTest time increaseNeed to store Patterns : Motivation for BISTInability to test circuits at full speed

Combinational logic

Q D

C

Q D

C

Q D

C

POPI

Clk

MUX0

MUX

MUX0

0

1

1

1

N/T

Sin

Sout

0 - 35

BIST (Built-In Self-Test)

◈ Capability of a product to carry out an explicit test of itself

Test patterns are generated on-chip

Responses to the test patterns are also evaluated on chip

External operations are required only to initialized the built-in tests and to check the test results (go/no-go)

◈ Advantage

No need for expensive tester

At-speed testing

Thorough test

◈ Disadvantages

Initial Design Investment

Area overhead

Pin overhead

Not effective for random testing resistive circuits

Aliasing problem

CUT

Scan ChainLFSR SignatureReg.

0 - 36

Boundary Scan

◈ Improve testability by reducing the requirements placedon the physical test equipment

◈ Also calledJTAG (Joint Test Action Group) Boundary Scan StandardsIEEE P1149.1

◈ Why use it?Testing interconnections among chipsTesting each chipSnapshot observation of normal system data

◈ Why testing boards?To test board is easier than totest systems

◈ Board Test PhilosophyAs a sorting processAs a repair driverAs a process monitor

SO

core

Bypass

Instruction RegisterSI

TAP