chapter 7 combinational mos logic circuits

1

CMOSDigital Integrated

CircuitsAnalysis and Design

Chapter 7

Combinational MOS Logic Circuits

2

Introduction

• Combination logic circuit– Performing Boolean operations between input and output– Static and dynamic characteristics

• MOS depletion-load gates– Emphasize the load concept– NAND, NOR

• CMOS logic circuit• CMOS transmission gates• Transmission gate (TG) logic circuits• In most general form

– A multiple-input, single-output system– Using positive logic convention

3

MOS logic circuits with depletion nMOS loads

• Two-input NOR gate– Calculation of VOH– Calculation of VOL– General NOR structure with multiple inputs– Transient analysis of NOR gate

• Two-input NAND gate– General NAND structure with multiple inputs– Transient analysis of NOR gate

4

Two-input NOR gate

5

Calculation of VOH, VOL

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6

Generalized NOR structure with multiple inputs

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7

Transient analysis of NOR gate

• The output load capacitance– Being valid for

simultaneous as well as for single-input switching

– The load capacitance Cload will be present at the output node even if only one input is active and all other input are low

– wireloadsbAdbloadgdBgdAgdload CCCCCCC +++++= ,,,,,

8

Two-input NAND gate

9

Calculation of VOH, VOL

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10

Generalized NAND structure with Multiple inputs

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11

Transient analysis of NAND gate

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12

Example 7.1

13

CMOS logic circuits

• CMOS NOR2 gate• CMOS NAND2 gate• Layout of simple CMOS logic gates

14

CMOS NOR2 gate• Consisting

– A parallel-connected n-net– A series-connected complementary p-net

• Operation– Either one or both input are high

• The n-net creates a conduction path between the output node• The p-net is cut off• Output low, VOL=0

– Both input are low• The n-net is cut off• The p-net creates a conduction path between the output node and VDD• Output high, VOH=VDD

15

The switching threshold voltage

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16

The switching threshold voltage

• When both inputs are identical – The parallel-connected nMOS transistors can be represented by a

single nMOS transistor with 2kn– The series-connected pMOS transistors are represented by a single

pMOS transistor with kp/2– Using the inverter switching threshold expression (7.37) for the

equivalent inverter circuit•

• In order to achieve Vth=VDD/2, we have to set VT,n=|VT,p| and kp=4kn

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41

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17

CMOS NAND2 gate

• The n-net in series, the p-net in parallel.

18

NAND2’s inverter equivalent• Assuming (W/L)n,A=(W/L)n,B and (W/L)p,A=(W/L)p,B

– The switching threshold•

• A threshold voltage of VDD/2 is achieved by setting VT,n=|VT,p| and kn=4kp

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19

Layout of simple CMOS logic gates

20

Stick-diagram layout of the CMOS NOR2 gate• The stick-diagram does not carry out any information on the actual

geometry relations of the individual features, but it conveys valuable information on the relative placement of the transistors and their interconnections

21

Complex logic circuits• The simple design principle of

the pull-down network– OR operations are performed

by parallel-connected drivers– AND operations are performed

by series-connected drivers– Inversion is provided by the

nature of MOS circuit operation

• If all input variables are logic high, the equivalent-driver (W/L) ratio of the pull-down network– ( )

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111

22

Complex logic circuits• For calculating the logic-low

voltage level VOL– The value of VOL depends on the

number and the configuration of the conducting nMOS transistors

– Assigning a class number which reflects the total resistance of the current path from Vout node to ground

• A-D ⇒ class 1 ⇒ highest series resistance

• A-E ⇒ class 1⇒ highest series resistance

• B-C ⇒ class 1⇒ highest series resistance

• A-D-E ⇒ class 2• A-D-B-C ⇒ class 3• A-E-B-C ⇒ class 3• A-D-E-B-C ⇒ class 4

• VOL1>VOL2>VOL3>VOL4• We usually start by specifying a

maximum VOL value

• The design objective⇒ determine the driver and load transistor size→ achieves the specified VOLvalue even in the worst case

• Three worst-case paths–

– Guarantee all other input ⇒output low will less than VOL

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driverEA

driverDA

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2

2

23

Complex CMOS logic gates

• The pMOS pull-up network– Must be the dual network of the n-net

• nMOS parallel ⇒ pMOS series• nMOS series ⇒ pMOS parallel

24

Stick-diagram, with arbitrary ordering of poly-Si• The stick diagram layout ⇒ a “first attempt”• An arbitrary ordering of the polysilicon gate column

– The separation between polysilicon must be allow• One diffusion-to-diffusion separation• Two metal-to-diffusion contacts

– Consuming area

25

Stick-diagram, Euler path approach

• Find a Euler-path in the pull-down graph and a Euler path in the pull-up graph with identical ordering of input labels

• The Euler path is defined as an uninterrupted path that traverses each edge (branch) of the graph exactly once

– E-D-A-B-C• The polysilicon column separation has to allow

– Only metal-to-diffusion contact• More compact layout area, simple routing of signals, less parasitic capacitance

26

Full CMOS implementation of XOR

• Two additional inverter are needed• Total 12 transistors

27

AOI and OAI gates

• The AOI gates– Enable the sum-of-products realization of a Boolean function in

one logic stage• The OAI gates

– Enable the product-of-sums realization of a Boolean function in one logic stage

28

Psuedo-nMOS gates

• CMOS gates ⇒ large area• Pseudo-nMOS

– To reduce the number of transistors

– To use a single pMOS transistor as the load device

• with its gate terminal connected to ground

– Disadvantage• Nonzero static power dissipation

– As the Vout is lower than VDD ⇒ the always-on pMOS load device conducts a steady state current

• The value of VOL and the noise margins– Determining by the ratio of pMOS transconductance load to

driver transconductance

29

Example 7.2

30

CMOS full-adder circuit_gate level

• The carry_out signal to generate the sum output– Reduce the circuit complexity– Save chip area

BCACABoutcarryBCACBACBAABC

CBAoutsum

++=+++=

⊕⊕=

_

_

31

CMOS full-adder circuit

32

CMOS transmission gates (pass gates)• Consisting of one nMOS and one pMOS transistor, connected in parallel• The gate voltage applied to these two transistors are also set to be

complementary signals• A bidirectional switch between nodes A and B which is controlled by signal

C– If signal C is logic high

• Low-resistance current path between the nodes A and B– If the signal C is low

• Both transistors will be off • Both transistors must take into account the substrate-bias effect

33

Carry ripple adder• N-bit binary adder

– The full adder as the basic building block– Two n-bit binary numbers as input and produces the binary sum

at the output– The overall speed of the carry ripple adder is obviously limited by

• The delay of the carry bits rippling through the carry chain• A fast carry_out response become essential• Critical path

34

CMOS transmission gates (pass gates)• Consisting of one nMOS and

one pMOS transistor, connected in parallel

• The gate voltage– Complementary signal to the

two transistors• Bidirectional switch between A

and B, controlled by C– Signal C is logic-high

• Both transistors turn on, low resistance current path

– Signal C is logic-low• Both transistors turn off, open,

high-impedance state– Substrate terminal

• nMOS⇒ ground, pMOS ⇒VDD

• Must consider body effect

35

CMOS transmission gates (pass gates)

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36

Replacing the CMOS TG with its resistor equivalent• The total equivalent resistance of the TG

remains relatively constant– Its value is almost independent of the output voltage

• Whereas the individual equivalent resistances are strongly dependent on Vout

– A CMOS TG can be replaced by its simple equivalent resistance for dynamic analysis

37

Two input multiplexer• The implement of CMOS transmission gates in logic circuit design

– Compact circuit structures, requires a smaller number of transistors– The control signal and its complement must be available simultaneously

for TG applications• Two input multiplexer

– If the control input S is logic high• The bottom TG conduct ⇒ output equal to the input B

– If the control input S is logic low• The top TG conduct ⇒ output equal to the input A

38

XOR

39

CMOS TG realization of a three-variable Boolean function

40

Complementary pass-transistor logic (CPL)• The main idea behind CPL is to use a purely nMOS pass-transistor

network for the logic operations, instead of a CMOS TG network– All input are applied in complementary form– The circuit also produces complementary outputs, to be used by

subsequent CPL stage– The CPL circuit consisting

• Complementary input• An nMOS pass transistor logic network to generate complementary outputs• CMOS output inverter to restore the output signal

41

Complementary pass-transistor logic• The elimination of pMOS transistors from

the pass-gate network – Reducing the parasitic capacitances– Higher operation speed– Process complexity

• The Vt,n must be reduced to about 0V through threshold-adjustment implants

– Reducing the overall noise immunity– Making the transistors more susceptible to subthreshold

conduction in the off-mode

– The CPL design style is highly modular• A wide range of functions can be realized by using

the same basic pass-transistor structures

42

Regarding the transistor count• CPL circuits do not always offer a marked advantage over conventional

CMOS• NAND2, NOR2⇒8 transistors• XOR, XNOR functions realized with CPL have a similar complexity as

CMOS realizations– The cross-coupled pMOS pull-up transistors are used to speed up the output

response• Full adder

– The same observation is true for the realization with CPL– consisting of 32 transistors