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Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-1
Chapter 8: Combinational Logic Modules
Department of Electronic Engineering
National Taiwan University of Science and Technology
Prof. Ming-Bo Lin
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-2
Syllabus
ObjectivesFundamentals of combinational logic modulesDecodersEncodersMultiplexersDemultiplexersComparators
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-3
Objectives
After completing this chapter, you will be able to:Understand the features of decoders Understand the features of encoders Understand the features of priority encodersUnderstand the features of multiplexersUnderstand the features of demultiplexersDescribe how to design comparators and magnitude comparatorsDescribe how to design a parameterized module
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-4
Syllabus
ObjectivesFundamentals of combinational logic modulesDecodersEncodersMultiplexersDemultiplexersComparators
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-5
Basic Combinational Logic Modules
DecoderEncoderMultiplexerDemultiplexerComparatorAdder (CLA)Subtracter (subtractor)MultiplierPLA Parity Generator
-
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-6
Options for Modeling Combinational Logic
Verilog HDL primitivesContinuous assignmentBehavioral statementFunctionsTask without delay or event controlCombinational UDPInterconnected combinational logic modules
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-7
Syllabus
ObjectivesFundamentals of combinational logic modulesDecodersEncodersMultiplexersDemultiplexersComparators
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-8
Decoder Block Diagrams
n-to-m decoders
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-9
A 2-to-4 Decoder Example
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-10
A 2-to-4 Decoder Example
// a 2-to-4 decoder with active low outputalways @(x or enable_n)
if (enable_n) y = 4'b1111; else case (x)
2'b00 : y = 4'b1110;2'b01 : y = 4'b1101;2'b10 : y = 4'b1011;2'b11 : y = 4'b0111;
endcase
y28
y25
y26
y27
un1_y28
un1_y25
un1_y26
un1_y27 y[3:0]
0
1
[0][1]
[0][1]
[0][1]
[1][0]
1111[3:0] y[3:0][3:0]
enable
x[1:0] [1:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-11
A 2-to-4 Decoder with Enable Control
// a 2-to-4 decoder with active-high outputalways @(x or enable)
if (!enable) y = 4'b0000; else case (x)
2'b00 : y = 4'b0001;2'b01 : y = 4'b0010;2'b10 : y = 4'b0100;2'b11 : y = 4'b1000;
endcase
y28
y25
y26
y27 y[3:0]
0
1
[0][1]
[0][1]
[0][1]
[1][0]
0000[3:0] y[3:0][3:0]
enable
x[1:0] [1:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-12
Syllabus
ObjectivesFundamentals of combinational logic modulesDecodersEncodersMultiplexersDemultiplexersComparators
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-13
Encoder Block Diagrams
m-to-n encoders
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-14
A 4-to-2 Encoder Example
Q: What is the problem of this encoder?
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-15
A 4-to-2 Encoder Example
// a 4-to-2 encoder using if ... else structurealways @(in) begin
if (in == 4'b0001) y = 0; elseif (in == 4'b0010) y = 1; elseif (in == 4'b0100) y = 2; elseif (in == 4'b1000) y = 3; else
y = 2'bx;end
y22
y23
y24
y25
y[1:0]
ed
ed
ed
ed
[0][1][2][3]
[1][0][2][3]
[2][0][1][3]
[3][0][1][2]
00
01[1:0]
10
11
y[1:0][1:0]
in[3:0] [3:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-16
Another 4-to-2 Encoder Example
// a 4-to-2 encoder using case structurealways @(in)
case (in)4'b0001 : y = 0;4'b0010 : y = 1;4'b0100 : y = 2;4'b1000 : y = 3;default : y = 2'bx;
endcase
y22
y23
y24
y25
y[1:0]
ed
ed
ed
ed
[0][1][2][3]
[1][0][2][3]
[2][0][1][3]
[3][0][1][2]
00
01[1:0]
10
11
y[1:0][1:0]
in[3:0] [3:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-17
A 4-to-2 Priority Encoder
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-18
A 4-to-2 Priority Encoder Example
// using if ... else structureassign valid_in = |in;always @(in) begin
if (in[3]) y = 3; elseif (in[2]) y = 2; elseif (in[1]) y = 1; elseif (in[0]) y = 0; elsey = 2'bx;
end
un1_in_1
y23
valid_in
un1_in_3
y24
y25
y_1[0]
ed
ed
ed
ed
[2][3]
[2][3]
[0][1][2][3]
[1]
[1]
[0]
[3]1
0
1
0
y[1:0]
valid_in
in[3:0] [3:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-19
Another 4-to-2 Priority Encoder Example
// using casex structureassign valid_in = |in;always @(in) casex (in)
4'b1xxx: y = 3;4'b01xx: y = 2;4'b001x: y = 1;4'b0001: y = 0;default: y = 2'bx;
endcase
y23[0]
y24[0]
valid_in
y25
y[1:0]
ed
ed
ed
ed
[2][3]
[1][2][3]
[0][1][2][3]
[0][1][2][3]
[3]11
10[1:0]
01
00
y[1:0][1:0]
valid_in
in[3:0] [3:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-20
Syllabus
ObjectivesFundamentals of combinational logic modulesDecodersEncodersMultiplexersDemultiplexersComparators
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-21
Multiplexer Block Diagramsm-to-1 ( m = 2n ) multiplexers
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-22
A 4-to-1 Multiplexer Example
Gate-based 4-to-1 multiplexers
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-23
An n-bit 4-to-1 Multiplexer Example
// an N-bit 4-to-1 multiplexer using conditional operatorparameter N = 4; //input [1:0] select;input [N-1:0] in3, in2, in1, in0;output [N-1:0] y;assign y = select[1] ?
(select[0] ? in3 : in2) :(select[0] ? in1 : in0) ;
un1_select_2
un1_select_3
un1_select_4
un1_select_5
y[3:0]
ed
ed
ed
ed
[0][1]
[1][0]
[0][1]
[0][1]
[3:0]
[3:0][3:0]
[3:0]
[3:0]
y[3:0][3:0]
in0[3:0] [3:0]
in1[3:0] [3:0]
in2[3:0] [3:0]
in3[3:0] [3:0]
select[1:0] [1:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-24
The Second n-bit 4-to- 1 Multiplexer Example
// an N-bit 4-to-1 multiplexer with enable controlparameter N = 4; input [1:0] select;input enable;input [N-1:0] in3, in2, in1, in0;output reg [N-1:0] y;
always @(select or enable or in0 or in1 or in2 or in3)if (!enable) y = {N{1’b0}};else y = select[1] ?
(select[0] ? in3 : in2) :(select[0] ? in1 : in0) ;
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-25
The Third n-bit 4-to- 1 Multiplexer Example
// an N-bit 4-to-1 multiplexer using case structureparameter N = 8; input [1:0] select;input [N-1:0] in3, in2, in1, in0;output reg [N-1:0] y;always @(*)
case (select)2’b11: y = in3 ;2’b10: y = in2 ;2’b01: y = in1 ;2’b00: y = in0 ;
endcase
un1_select_2
un1_select_3
un1_select_4
un1_select_5
y[7:0]
ed
ed
ed
ed
[0][1]
[1][0]
[0][1]
[0][1]
[7:0]
[7:0][7:0]
[7:0]
[7:0]
y[7:0][7:0]
in0[7:0] [7:0]
in1[7:0] [7:0]
in2[7:0] [7:0]
in3[7:0] [7:0]
select[1:0] [1:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-26
Syllabus
ObjectivesFundamentals of combinational logic modulesDecodersEncodersMultiplexersDemultiplexersComparators
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-27
DeMultiplexer Block Diagrams
1-to-m ( m = 2n ) demultiplexers
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-28
A 1-to-4 DeMultiplexer Example
Gate-based 1-to-4 demultiplexers
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-29
An n-bit 1-to-4 DeMultiplexer Example
// an N-bit 1-to-4 demultiplexer using if ... else structureparameter N = 4; // default widthinput [1:0] select;input [N-1:0] in;output reg [N-1:0] y3, y2, y1, y0;
always @(select or in) begin if (select == 3) y3 = in; else y3 = {N{1'b0}};if (select == 2) y2 = in; else y2 = {N{1'b0}};if (select == 1) y1 = in; else y1 = {N{1'b0}};if (select == 0) y0 = in; else y0 = {N{1'b0}};
end
y37
y27
y17
y07
y3[3:0]
0
1
y2[3:0]
0
1
y1[3:0]
0
1
y0[3:0]
0
1
[0][1]
[1][0]
[0][1]
[0][1]
0000[3:0]
[3:0]
0000[3:0]
[3:0]
0000[3:0]
[3:0]
0000[3:0]
[3:0]y0[3:0][3:0]
y1[3:0][3:0]
y2[3:0][3:0]
y3[3:0][3:0]
in[3:0] [3:0]
select[1:0] [1:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-30
The Second n-bit 1-to-4 DeMultiplexer Example
// an N-bit 1-to-4 demultiplexer with enable controlparameter N = 4; // Default width …output reg [N-1:0] y3, y2, y1, y0;always @(select or in or enable) begin
if (enable)beginif (select == 3) y3 = in; else y3 = {N{1'b0}};if (select == 2) y2 = in; else y2 = {N{1'b0}};if (select == 1) y1 = in; else y1 = {N{1'b0}};if (select == 0) y0 = in; else y0 = {N{1'b0}};
end else beginy3 = {N{1'b0}}; y2 = {N{1'b0}}; y1 = {N{1'b0}}; y0 = {N{1'b0}}; end
end
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-31
Syllabus
ObjectivesFundamentals of combinational logic modulesDecodersEncodersMultiplexersDemultiplexersComparators
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-32
Comparators
A 4-bit comparator
A 4-bit cascadable comparator block diagram
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-33
Types of Comparators
ComparatorCascadable comparator
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-34
Comparators
An 8-bit comparator
Q: What will happen if you set the input value (010) at the rightmost end to other values?
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-35
A Simple Comparator Example
// an N-bit comparator module exampleparameter N = 4; // default size input [N-1:0] a, b;output cgt, clt, ceq;
assign cgt = (a > b);assign clt = (a < b);assign ceq = (a == b);
ceq =
cgt <
clt <
[3:0]
[3:0]
[3:0]
[3:0]
[3:0]
[3:0]
ceq
clt
cgt
b[3:0] [3:0]
a[3:0] [3:0]
Chapter 8: Combinational Logic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-36
A Cascadable Comparator Example
parameter N = 4; // I/O port declarationsinput Iagtb, Iaeqb, Ialtb;input [N-1:0] a, b;output Oagtb, Oaeqb, Oaltb;
// dataflow modeling using relation operatorsassign Oaeqb = (a == b) && (Iaeqb == 1); // =assign Oagtb = (a > b) || ((a == b)&& (Iagtb == 1)); // >assign Oaltb = (a < b) || ((a == b)&& (Ialtb == 1)); // <
un1_Oaeqb =
un1_Oagtb <
un1_Oaltb <
Oaeqb
un2_Oagtb
un2_Oaltb
Oagtb
Oaltb
[3:0]
[3:0]
[3:0]
[3:0]
[3:0]
[3:0]
Ialtb
Iaeqb
Iagtb
b[3:0] [3:0]
a[3:0] [3:0]
Oaltb
Oaeqb
Oagtb
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