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CMOS logic gates
João Canas Ferreira
University of PortoFaculty of Engineering
March 2016
Topics
1 General structure
2 General properties
3 Cell layout
João Canas Ferreira (FEUP) CMOS logic gates March 2016 2 / 37
Static dual CMOS gates
pull-upnetwork
pull-downnetwork
In1
In1
In2
In2
InN
InN
F(In1, In2, ..., InN)
PMOS
NMOS
à Pull- and pull-down networks are dual of each other:
series of switches⇔ parallel switches
João Canas Ferreira (FEUP) CMOS logic gates March 2016 3 / 37
NAND logic gate
A
A
B
B
Out=A•BA B Out0 0 10 1 11 0 11 1 0
à Pull-down network: G = A · B direct path to Gnd
à Pull-up network : F = A + B = AB direct path to VDD
à Generally (self-duality): G(In1, In2, . . .) = F(In1, In2, . . .)
Out = G(In1, In2, . . .)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 4 / 37
NAND logic gate
A
A
B
B
Out=A•BA B Out0 0 10 1 11 0 11 1 0
à Pull-down network: G = A · B direct path to Gnd
à Pull-up network : F = A + B = AB direct path to VDD
à Generally (self-duality): G(In1, In2, . . .) = F(In1, In2, . . .)
Out = G(In1, In2, . . .)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 4 / 37
NOR logic gate
A
A B
BOut = A+B
A B C
A
B
COut = A+B+C
A B Out0 0 00 1 01 0 01 1 1
João Canas Ferreira (FEUP) CMOS logic gates March 2016 5 / 37
Complex CMOS logic gate
A
A
B
B
Out = D+A(B+C)
C
D
C
D
João Canas Ferreira (FEUP) CMOS logic gates March 2016 6 / 37
Building a complex CMOS logic gate
à Design the pull-down network
à Find hierarchically all sub-networks
à Switch parallel⇐⇒ series by hierarchical order
A
B C
D
A
B C
D
12
3
4
A
B
C
D
1
2
3 4
João Canas Ferreira (FEUP) CMOS logic gates March 2016 7 / 37
Building a complex CMOS logic gate
à Design the pull-down network
à Find hierarchically all sub-networks
à Switch parallel⇐⇒ series by hierarchical order
A
B C
D
A
B C
D
12
3
4
A
B
C
D
1
2
3 4
João Canas Ferreira (FEUP) CMOS logic gates March 2016 7 / 37
Building a complex CMOS logic gate
à Design the pull-down network
à Find hierarchically all sub-networks
à Switch parallel⇐⇒ series by hierarchical order
A
B C
D
A
B C
D
12
3
4
A
B
C
D
1
2
3 4
João Canas Ferreira (FEUP) CMOS logic gates March 2016 7 / 37
Building a complex CMOS logic gate
à Design the pull-down network
à Find hierarchically all sub-networks
à Switch parallel⇐⇒ series by hierarchical order
A
B C
D
A
B C
D
12
3
4
A
B
C
D
1
2
3 4
João Canas Ferreira (FEUP) CMOS logic gates March 2016 7 / 37
Criteria for complex CMOS static gates
I Dual circuit is not necessarily obtained by series↔ parallel.
I There may be several dual circuits.
I How to identify a good dual circuit?
Methods
I Use Karnaugh maps to identify dual circuit with good layout propertiesand reduced parasitics.
I Maximize the number of connections to VDD or Gnd
I Put delay critical transistors near the output node
João Canas Ferreira (FEUP) CMOS logic gates March 2016 8 / 37
Criteria for complex CMOS static gates
I Dual circuit is not necessarily obtained by series↔ parallel.
I There may be several dual circuits.
I How to identify a good dual circuit?
Methods
I Use Karnaugh maps to identify dual circuit with good layout propertiesand reduced parasitics.
I Maximize the number of connections to VDD or Gnd
I Put delay critical transistors near the output node
João Canas Ferreira (FEUP) CMOS logic gates March 2016 8 / 37
Example: carry generation (1)
I Carry output of a full adder: F(a, b, c) = ab + bc + ac
I Implement function G(a, b, c) = F
I “0-cover” defines the pull-down circuit
I “1-cover” defines the pull-up circuit
1 1A B
C
1 0
0 0
1 0
0 0
0 1
1 1
1 0
0 1à 0-cover: ab + bc + ac
à 1-cover: a b + b c + a c
João Canas Ferreira (FEUP) CMOS logic gates March 2016 9 / 37
Examplo: carry generation (2)
Pull-down circuit
I Maximize number of connections to VDD
I Critical signal (C) near output
I Factorize: ab + c(a + b)
C
A B
A
B
João Canas Ferreira (FEUP) CMOS logic gates March 2016 10 / 37
Examplo: carry generation (3)
à Series/parallel dual pull-up circuit
A B
C A
B
à Pull-up circuit derived from 1-cover
A B
B
A
C
João Canas Ferreira (FEUP) CMOS logic gates March 2016 11 / 37
Examplo: carry generation (3)
à Series/parallel dual pull-up circuit
A B
C A
B
à Pull-up circuit derived from 1-cover
A B
B
A
C
João Canas Ferreira (FEUP) CMOS logic gates March 2016 11 / 37
Topics
1 General structure
2 General properties
3 Cell layout
João Canas Ferreira (FEUP) CMOS logic gates March 2016 12 / 37
Properties of dual static complex CMOS gates
I Rail-to-rail excursion: large noise margin
I Logic levels do not depend on the size of the devices (ratioless logic)
I Steady-state path from output to Vdd/Gnd:low output resistance
I Very high input resistance (input DC current ≈ 0)
I No direct path between Vdd and Gnd:no static power dissipation
I Delay depends (mainly) on the load capacitance and the equivalentresistance (Ron) of the transistors.
João Canas Ferreira (FEUP) CMOS logic gates March 2016 13 / 37
Properties of dual static complex CMOS gates
I Rail-to-rail excursion: large noise margin
I Logic levels do not depend on the size of the devices (ratioless logic)
I Steady-state path from output to Vdd/Gnd:low output resistance
I Very high input resistance (input DC current ≈ 0)
I No direct path between Vdd and Gnd:no static power dissipation
I Delay depends (mainly) on the load capacitance and the equivalentresistance (Ron) of the transistors.
João Canas Ferreira (FEUP) CMOS logic gates March 2016 13 / 37
Properties of dual static complex CMOS gates
I Rail-to-rail excursion: large noise margin
I Logic levels do not depend on the size of the devices (ratioless logic)
I Steady-state path from output to Vdd/Gnd:low output resistance
I Very high input resistance (input DC current ≈ 0)
I No direct path between Vdd and Gnd:no static power dissipation
I Delay depends (mainly) on the load capacitance and the equivalentresistance (Ron) of the transistors.
João Canas Ferreira (FEUP) CMOS logic gates March 2016 13 / 37
Properties of dual static complex CMOS gates
I Rail-to-rail excursion: large noise margin
I Logic levels do not depend on the size of the devices (ratioless logic)
I Steady-state path from output to Vdd/Gnd:low output resistance
I Very high input resistance (input DC current ≈ 0)
I No direct path between Vdd and Gnd:no static power dissipation
I Delay depends (mainly) on the load capacitance and the equivalentresistance (Ron) of the transistors.
João Canas Ferreira (FEUP) CMOS logic gates March 2016 13 / 37
Properties of dual static complex CMOS gates
I Rail-to-rail excursion: large noise margin
I Logic levels do not depend on the size of the devices (ratioless logic)
I Steady-state path from output to Vdd/Gnd:low output resistance
I Very high input resistance (input DC current ≈ 0)
I No direct path between Vdd and Gnd:no static power dissipation
I Delay depends (mainly) on the load capacitance and the equivalentresistance (Ron) of the transistors.
João Canas Ferreira (FEUP) CMOS logic gates March 2016 13 / 37
Properties of dual static complex CMOS gates
I Rail-to-rail excursion: large noise margin
I Logic levels do not depend on the size of the devices (ratioless logic)
I Steady-state path from output to Vdd/Gnd:low output resistance
I Very high input resistance (input DC current ≈ 0)
I No direct path between Vdd and Gnd:no static power dissipation
I Delay depends (mainly) on the load capacitance and the equivalentresistance (Ron) of the transistors.
João Canas Ferreira (FEUP) CMOS logic gates March 2016 13 / 37
Models for calculating propagation delayà Subsritute transistors by switch and Reqà Include intrinsic capacitance of internal nodes
João Canas Ferreira (FEUP) CMOS logic gates March 2016 14 / 37
Delay is dependent on input patterns
I Delay depends on pull-up/pull-downpath
I “0” to “1” output transition:
I both inputs are zero:0.69× (Rp/2)CL
I one input is zero:0.69× RpCL
I “1” to “0” output transition:
I both inputs are “1”:0.69× 2× RnCL
I includingintr (Elmore delayapproximation):
0.69× (RnCintr + 2× RnCL)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 15 / 37
Delay is dependent on input patterns
I Delay depends on pull-up/pull-downpath
I “0” to “1” output transition:
I both inputs are zero:0.69× (Rp/2)CL
I one input is zero:0.69× RpCL
I “1” to “0” output transition:
I both inputs are “1”:0.69× 2× RnCL
I includingintr (Elmore delayapproximation):
0.69× (RnCintr + 2× RnCL)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 15 / 37
Delay is dependent on input patterns
I Delay depends on pull-up/pull-downpath
I “0” to “1” output transition:
I both inputs are zero:0.69× (Rp/2)CL
I one input is zero:0.69× RpCL
I “1” to “0” output transition:
I both inputs are “1”:0.69× 2× RnCL
I includingintr (Elmore delayapproximation):
0.69× (RnCintr + 2× RnCL)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 15 / 37
Delay is dependent on input patterns
I Delay depends on pull-up/pull-downpath
I “0” to “1” output transition:I both inputs are zero:
0.69× (Rp/2)CL
I one input is zero:0.69× RpCL
I “1” to “0” output transition:
I both inputs are “1”:0.69× 2× RnCL
I includingintr (Elmore delayapproximation):
0.69× (RnCintr + 2× RnCL)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 15 / 37
Delay is dependent on input patterns
I Delay depends on pull-up/pull-downpath
I “0” to “1” output transition:I both inputs are zero:
0.69× (Rp/2)CLI one input is zero:
0.69× RpCL
I “1” to “0” output transition:
I both inputs are “1”:0.69× 2× RnCL
I includingintr (Elmore delayapproximation):
0.69× (RnCintr + 2× RnCL)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 15 / 37
Delay is dependent on input patterns
I Delay depends on pull-up/pull-downpath
I “0” to “1” output transition:I both inputs are zero:
0.69× (Rp/2)CLI one input is zero:
0.69× RpCL
I “1” to “0” output transition:
I both inputs are “1”:0.69× 2× RnCL
I includingintr (Elmore delayapproximation):
0.69× (RnCintr + 2× RnCL)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 15 / 37
Delay is dependent on input patterns
I Delay depends on pull-up/pull-downpath
I “0” to “1” output transition:I both inputs are zero:
0.69× (Rp/2)CLI one input is zero:
0.69× RpCL
I “1” to “0” output transition:I both inputs are “1”:
0.69× 2× RnCL
I includingintr (Elmore delayapproximation):
0.69× (RnCintr + 2× RnCL)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 15 / 37
Delay is dependent on input patterns
I Delay depends on pull-up/pull-downpath
I “0” to “1” output transition:I both inputs are zero:
0.69× (Rp/2)CLI one input is zero:
0.69× RpCL
I “1” to “0” output transition:I both inputs are “1”:
0.69× 2× RnCLI includingintr (Elmore delay
approximation):0.69× (RnCintr + 2× RnCL)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 15 / 37
NAND2: input dependent delay
à NMOS: 0.5 µm/0.25 µm PMOS: 0.75 µm/0.25 µm CL=100 fF
Volt
age
(V)
time (ps)
Source: [Rabaey03]
Inputpattern
Delay (ps)
A=B=0→1 69
A=1, B=0→1 62
A=0→1, B=1 50
A=B=1→0 35
A=1, B=1→0 76
A=1→0, B=1 57
João Canas Ferreira (FEUP) CMOS logic gates March 2016 16 / 37
Transistor sizing (1)à Symmetric (balanced) gates (assuming β = 2)à Size in multiples of (Wmin/Lmin) (multiplying W)
João Canas Ferreira (FEUP) CMOS logic gates March 2016 17 / 37
Transistor sizing (2)
à Starting with the left branchà Starting with the right branch
à A series of transistors has the equivalent size:
(W/L)eq =1
1(W/L)1
+ 1(W/L)2
+ . . .
For constant L:
Weq =1
1W1
+ 1W2
+ . . .
à For parallel devices:
(W/L)eq = (W/L)1 + (W/L)2 + . . .
For constant L:
Weq = W1 + W2 + . . .
João Canas Ferreira (FEUP) CMOS logic gates March 2016 18 / 37
Influence of the number of inputs
à Elmore estimate of the propagationdelay::
tpHL = 0.69((R1 C1 + (R1 + R2) C2
+ (R1 + R2 + R3) C3
+ (R1 + R2 + R3 + R4) CL)
à Equal NMOS transistors:
tpHL = 0.69 Reqn(C1 + 2 C2 + 3 C3 + 4 CL)
à Propagation delay degradessignificantly with increasing number ofinputs (fan-in); in the worst case,quadratically
(1 + 2 + . . . + N = N(N – 1)/2).
João Canas Ferreira (FEUP) CMOS logic gates March 2016 19 / 37
Influence of the number of inputs
à Elmore estimate of the propagationdelay::
tpHL = 0.69((R1 C1 + (R1 + R2) C2
+ (R1 + R2 + R3) C3
+ (R1 + R2 + R3 + R4) CL)
à Equal NMOS transistors:
tpHL = 0.69 Reqn(C1 + 2 C2 + 3 C3 + 4 CL)
à Propagation delay degradessignificantly with increasing number ofinputs (fan-in); in the worst case,quadratically
(1 + 2 + . . . + N = N(N – 1)/2).
João Canas Ferreira (FEUP) CMOS logic gates March 2016 19 / 37
Propagation delay as a function of the number of inputs
Source: [Rabaey03]
à Practical rule: Avoid logic gates with more than four inputs.
João Canas Ferreira (FEUP) CMOS logic gates March 2016 20 / 37
Propagation delay as a function of effective fan-out
à Effective fan-out: F =CloadCinput
Source: [Rabaey03]
João Canas Ferreira (FEUP) CMOS logic gates March 2016 21 / 37
Reducing propagation delay (1)
I Make transistors widerà Useful while external load capacitance is dominant.
I Progressive sizing
à M1 > M2 > M3 >. . . > MN(FET closer to the output is the smallest)
à May reduce delay by more than 20 %
João Canas Ferreira (FEUP) CMOS logic gates March 2016 22 / 37
Reducing propagation delay (1)
I Make transistors widerà Useful while external load capacitance is dominant.
I Progressive sizing
à M1 > M2 > M3 >. . . > MN(FET closer to the output is the smallest)
à May reduce delay by more than 20 %
João Canas Ferreira (FEUP) CMOS logic gates March 2016 22 / 37
Reducing propagation delay (2)
à Consider arrival order of signal
I3
I2
I1
CL
C2
C1M1
M2
M3
1
1
charged
charged
charged0 →1
à delay determined by dischargeof CL, C1 e C2
I3
I2
I1
CL
C2
C1M1
M2
M3
1
1
charged
uncharged
uncharged
0 →1
à delay determined by dischargeof CL
João Canas Ferreira (FEUP) CMOS logic gates March 2016 23 / 37
Reducing propagation delay (3)à Chose structure that allow a smaller fan-in
Example: F = ABCDEFG
à Question: how to select the fastest structure?João Canas Ferreira (FEUP) CMOS logic gates March 2016 24 / 37
Reducing propagation delay (4)
à Buffer insertion
à Question: what is the ideal number of buffers and their sizes?
João Canas Ferreira (FEUP) CMOS logic gates March 2016 25 / 37
Topics
1 General structure
2 General properties
3 Cell layout
João Canas Ferreira (FEUP) CMOS logic gates March 2016 26 / 37
Standard cell ( 1980’s)
Source: [Rabaey03]
Contacts and well not shown
João Canas Ferreira (FEUP) CMOS logic gates March 2016 27 / 37
Standard cell (1990’s)
Mirrored cell
Mirrored cell
No channel
Source: [Rabaey03]
João Canas Ferreira (FEUP) CMOS logic gates March 2016 28 / 37
Structure of a cell (inverter)
cell border
Height: 12 metal tracks
Metal track approx. 3λ + 3λPitch: distance between
repeated objects
Cell height: "12 pitch"
Supply ~ 10 λ
Source: [Rabaey03]
João Canas Ferreira (FEUP) CMOS logic gates March 2016 29 / 37
Variants of inverter cell
Minimum routingin diffusion
Silicidadediffusion
Source: [Rabaey03]
João Canas Ferreira (FEUP) CMOS logic gates March 2016 30 / 37
Two-input NAND gate
Source: [Rabaey03]
João Canas Ferreira (FEUP) CMOS logic gates March 2016 31 / 37
Layout planning (stick diagrams)
Source: [Rabaey03]
à No sizesà Relative positions
João Canas Ferreira (FEUP) CMOS logic gates March 2016 32 / 37
Layout planning of complex cells
A
A B
B
C
C X = C (A+B)
Y
Z
X
X
Gnd
Z
Vdd
Y
C
B A
C
AB
1 Draw two graphs (one for each network) where the nodes represent circuit nodes andedges represent devices.
2 Find a consistent Euler paths through each graph.Euler path: path through all the edges (just once) → Layout with continuous diffusion!
The two paths must be consistent : same sequence of nodes on both paths (just onepoly line for both nMOS and pMOS devices).
João Canas Ferreira (FEUP) CMOS logic gates March 2016 33 / 37
Example: Two implementation alternatives
Source: [Rabaey03]
Cell on the right: no diffusion breaks
João Canas Ferreira (FEUP) CMOS logic gates March 2016 34 / 37
Another example: Logic gate OAI22
A
A B
CX = (A+B)(C+D)
D
C
B
D
X
X
Gnd
Vdd
C
B A
C
AB
D
D
João Canas Ferreira (FEUP) CMOS logic gates March 2016 35 / 37
Wide transistors
One �ngerTwo �ngers
Less diffusion capacitance
Source: [Rabaey03]
João Canas Ferreira (FEUP) CMOS logic gates March 2016 36 / 37
References
à Some of the figures come from the book:
Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, 2ndedition,Prentice Hall, 2003.http://bwrc.eecs.berkeley.edu/icbook/
João Canas Ferreira (FEUP) CMOS logic gates March 2016 37 / 37
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