combinational logic chapter 4. digital circuits 2 4.1 introduction logic circuits for digital...
Post on 15-Jan-2016
251 Views
Preview:
TRANSCRIPT
Combinational Logic
Chapter 4
2Digital Circuits
4.1 Introduction
Logic circuits for digital systems may be combinational or sequential.
A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs.
3Digital Circuits
4.2 Combinational Circuits
Logic circuits for digital system Sequential circuits
contain memory elements the outputs are a function of the current inputs and the
state of the memory elements the outputs also depend on past inputs
4Digital Circuits
A combinational circuits 2
n possible combinations of input values
Specific functions Adders, subtractors, comparators, decoders, encoders,
and multiplexers MSI circuits or standard cells
CombinationalLogic Circuit
n inputvariables
m outputvariables
5Digital Circuits
4-3 Analysis Procedure
A combinational circuit make sure that it is combinational not sequential
No feedback path derive its Boolean functions (truth table) design verification a verbal explanation of its function
6Digital Circuits
A straight-forward procedure
F2 = AB+AC+BCT1 = A+B+CT2 = ABCT3 = F2'T1F1 = T3+T2
7Digital Circuits
F1 = T3+T2 = F2'T1+ABC = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C')(B'+C')(A+B+C)
+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B'C+AB'C'+ABC
A full-adder F1: the sum
F2: the carry
8Digital Circuits
The truth table
9Digital Circuits
4-4 Design Procedure
The design procedure of combinational circuits State the problem (system spec.) determine the inputs and outputs the input and output variables are assigned symbols derive the truth table derive the simplified Boolean functions draw the logic diagram and verify the correctness
10Digital Circuits
Functional description Boolean function HDL (Hardware description language)
Verilog HDL VHDL
Schematic entry Logic minimization
number of gates number of inputs to a gate propagation delay number of interconnection limitations of the driving capabilities
11Digital Circuits
Code conversion example BCD to excess-3 code
The truth table
12Digital Circuits
The maps
13Digital Circuits
The simplified functions z = D'
y = CD +C'D' x = B'C + B'D+BC'D'
w = A+BC+BD Another implementation
z = D' y = CD +C'D' = CD + (C+D)'
x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)' w = A+BC+BD
14Digital Circuits
The logic diagram
15Digital Circuits
4-5 Binary Adder-Subtractor
Half adder 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10 two input variables: x, y two output variables: C (carry), S (sum) truth table
16Digital Circuits
S = x'y+xy' C = xy
the flexibility for implementation S=xy S = (x+y)(x'+y') S' = xy+x'y'
S = (C+x'y')' C = xy = (x'+y')'
17Digital Circuits
18Digital Circuits
Full-Adder The arithmetic sum of three input bits three input bits
x, y: two significant bits z: the carry bit from the previous lower significant bit
Two output bits: C, S
19Digital Circuits
20Digital Circuits
S = x'y'z+x'yz'+ xy'z'+xyz C = xy + xz + yz
S = z (xy)= z'(xy'+x'y)+z(xy'+x'y)'
= z'xy'+z'x'y+z((x'+y)(x+y'))= xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy
21Digital Circuits
Binary adder
22Digital Circuits
Carry propagation when the correct outputs are available the critical path counts (the worst case) (A1,B1,C1) > C2 > C3 > C4 > (C5,S4) > 8 gate levels
23Digital Circuits
Reduce the carry propagation delay employ faster gates look-ahead carry (more complex mechanism, yet
faster) carry propagate: Pi = AiBi
carry generate: Gi = AiBi
sum: Si = PiCi
carry: Ci+1 = Gi+PiCi
C1 = G0+P0C0
C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0
C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0
24Digital Circuits
Logic diagram
25Digital Circuits
4-bit carry-look ahead adder propagation delay
26Digital Circuits
Binary subtractor A-B = A+(2’s complement of B) 4-bit Adder-subtractor
M=0, A+B; M=1, A+B’+1
27Digital Circuits
Overflow The storage is limited Add two positive numbers and obtain a negative
number Add two negative numbers and obtain a positive
number V = 0, no overflow; V = 1, overflow
Example:
28Digital Circuits
4-6 Decimal Adder
Add two BCD's 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out
Design approaches A truth table with 2^9 entries use binary full Adders
the sum <= 9 + 9 + 1 = 19 binary to BCD
29Digital Circuits
BCD Adder: The truth table
30Digital Circuits
Modifications are needed if the sum > 9 C = 1
K = 1 Z8Z4 = 1
Z8Z2 = 1
modification: (10)d or +6
C = K +Z8Z4 + Z8Z2
31Digital Circuits
Block diagram
32Digital Circuits
Binary Multiplier Partial products
– AND operations
Fig. 4.15 Two-bit by two-bit binary multiplier.
33Digital Circuits
4-bit by 3-bit binary multiplier
Fig. 4.16 Four-bit by three-bit binary multiplier.
34Digital Circuits
4-8 Magnitude Comparator
The comparison of two numbers outputs: A>B, A=B, A<B
Design Approaches the truth table
22n
entries - too cumbersome for large n use inherent regularity of the problem
reduce design efforts reduce human errors
35Digital Circuits
Algorithm -> logic A = A3A2A1A0 ; B = B3B2B1B0
A=B if A3=B3, A2=B2, A1=B1and A1=B1
equality: xi= AiBi+Ai'Bi'
(A=B) = x3x2x1x0
(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
(A>B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
Implementation xi = (AiBi'+Ai'Bi)'
36Digital Circuits
Fig. 4.17Four-bit magnitude comparator.
37Digital Circuits
4-9 Decoder A n-to-m decoder
a binary code of n bits = 2n distinct information
n input variables; up to 2n output lines
only one output can be active (high) at any time
38Digital Circuits
An implementation
Fig. 4.18 Three-to-eight-line decoder.
39Digital Circuits
Combinational logic implementation each output = a minterm use a decoder and an external OR gate to
implement any Boolean function of n input variables
40Digital Circuits
Demultiplexers a decoder with an enable input receive information on a single line and transmits it
on one of 2n possible output lines
Fig. 4.19 Two-to-four-line decoder with enable input
41Digital Circuits
Decoder/demultiplexers
第三版內容,參考用 !
42Digital Circuits
Expansion two 3-to-8 decoder: a 4-to-16 deocder
a 5-to-32 decoder?
Fig. 4.20 4 16 decoder constructed with two 3 8 decoders
43Digital Circuits
Combination Logic Implementation
each output = a minterm use a decoder and an external OR gate to
implement any Boolean function of n input variables
A full-adder S(x,y,x)=(1,2,4,7)
C(x,y,z)= (3,5,6,7)
Fig. 4.21 Implementation of a full adder with a decoder
44Digital Circuits
two possible approaches using decoder OR(minterms of F): k inputs NOR(minterms of F'): 2
n k inputs
In general, it is not a practical implementation
45Digital Circuits
4-10 Encoders The inverse function of
a decoder
1 3 5 7
2 3 6 7
4 5 6 7
z D D D D
y D D D D
x D D D D
The encoder can be implemented with three OR gates.
46Digital Circuits
An implementation
limitations illegal input: e.g. D3=D6=1 the output = 111 (¹3 and ¹6) 第三版內容,參考用 !
47Digital Circuits
Priority Encoder resolve the ambiguity of illegal inputs only one of the input is encoded
D3 has the highest priority D0 has the lowest priority X: don't-care conditions V: valid output indicator
48Digital Circuits
■ The maps for simplifying outputs x and y
Fig. 4.22 Maps for a priority encoder
49Digital Circuits
■ Implementation of priority
Fig. 4.23 Four-input priority encoder
2 3
3 1 2
0 1 2 3
x D D
y D D D
V D D D D
50Digital Circuits
4-11 Multiplexers select binary information from one of many input
lines and direct it to a single output line 2
n input lines, n selection lines and one output line
e.g.: 2-to-1-line multiplexer
Fig. 4.24 Two-to-one-line multiplexer
51Digital Circuits
4-to-1-line multiplexer
Fig. 4.25 Four-to-one-line multiplexer
52Digital Circuits
Note n-to- 2
n decoder
add the 2n input lines to each AND gate
OR(all AND gates) an enable input (an option)
53Digital Circuits
Fig. 4.26 Quadruple two-to-one-line multiplexer
54Digital Circuits
Boolean function implementation
MUX: a decoder + an OR gate 2
n-to-1 MUX can implement any Boolean function
of n input variable
a better solution: implement any Boolean function of n+1 input variable
n of these variables: the selection lines the remaining variable: the inputs
55Digital Circuits
an example: F(A,B,C) = (1,2,6,7)
Fig. 4.27 Implementing a Boolean function with a multiplexer
56Digital Circuits
Procedure: assign an ordering sequence of the input variable the rightmost variable (D) will be used for the input
lines assign the remaining n-1 variables to the selection
lines w.r.t. their corresponding sequence construct the truth table consider a pair of consecutive minterms starting
from m0
determine the input lines
57Digital Circuits
Fig. 4.28 Implementing a four-input function with a multiplexer
Example: F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)
58Digital Circuits
Three-state gates
A multiplexer can be constructed with three-state gates
Output state: 0, 1, and high-impedance (open ckts)
Fig. 4.29 Graphic symbol for a three-state buffer
59Digital Circuits
Example: Four-to-one-line multiplexer
Fig. 4.30 Multiplexer with three-state gates
60Digital Circuits
4-12 HDL Models of Combinational Circuits
▓ Modeling Styles:
61Digital Circuits
Gate-level Modeling
▓ The four-valued logic truth tables for the and, or, xor, and not primitives
62Digital Circuits
Gate-level Modeling
Example:
output [0: 3] D;wire [7: 0] SUM;
1. The first statement declares an output vector D with four bits, 0 through 3.
2. The second declares a wire vector SUM with eight bits numbered 7 through 0.
63Digital Circuits
HDL Example 4-1
■ Two-to-one-line decoder
64Digital Circuits
HDL Example 4-2
■ Four-bit adder: bottom-up hierarchical description
65Digital Circuits
HDL Example 4-2 (continued)
66Digital Circuits
Three-State Gates
■ Statement:
gate name (output, input, control);
Fig. 4.31 Three-state gates
67Digital Circuits
Three-State Gates
■ Examples of gate instantiation
68Digital Circuits
Fig. 4.32 Two-to-one-line multiplexer with three-state buffers
69Digital Circuits
Dataflow Modeling
■ Verilog HDL operators
Example:
assign Y = (A & S) | (B & ~S)
70Digital Circuits
HDL Example 4.3
Dataflow description of a 2-to-4-line decoder
71Digital Circuits
HDL Example 4-4
Dataflow description of 4-bit adder
72Digital Circuits
HDL Example 4-5
Dataflow description of 4-bit magnitude comparator
73Digital Circuits
HDL Example 4-6
Dataflow description of a 2-to-1-line multiplexer
Conditional operator (?:)
Condition ? True-expression : false-expression
Example: continuous assignment
assign OUT = select ? A : B
74Digital Circuits
Behavioral Modeling
if statement:if (select) OUT = A;
Behavioral description of a 2-to-1-line multiplexer
HDL Example 4-7
75Digital Circuits
HDL Example 4-8
Behavioral description of a 4-to-1-line multiplexer
76Digital Circuits
Writing a Simple Test Bench
initial block
Three-bit truth table
77Digital Circuits
Writing a Simple Test Bench
Interaction between stimulus and design modules
78Digital Circuits
Writing a Simple Test Bench
Stimulus module
System tasks for display
79Digital Circuits
Syntax for $dispaly, $write, and $monitor:
Example:
Example:
80Digital Circuits
HDL Example 4-9
Stimulus module
81Digital Circuits
HDL Example 4-9 (Continued)
82Digital Circuits
HDL Example 4-10
Gate-level description of a full adder
83Digital Circuits
HDL Example 4-10 (Continued)
top related