constructive computer architecture virtual memory and...
Post on 13-Mar-2021
10 Views
Preview:
TRANSCRIPT
Constructive Computer Architecture
Virtual Memory and Interrupts
ArvindComputer Science & Artificial Intelligence Lab.Massachusetts Institute of Technology
November 13, 2015 http://csg.csail.mit.edu/6.175 L21-1
Address Translation:putting it all together
Virtual Address
TLBLookup
Page TableWalk
Update TLBPage Fault(OS loads page)
ProtectionCheck
PhysicalAddress(to cache)
miss hit
the page is memory memory denied permitted
ProtectionFault
hardwarehardware or softwaresoftware
SEGFAULTWhere?
Resume the instructionNovember 13, 2015 http://csg.csail.mit.edu/6.175 L21-2
Address Translation in Pipeline Machines
Software handlers need a restartable exception on page fault or protection violationHandling a TLB miss needs a hardware or softwaremechanism to refill TLB Methods to overcome the additional latency of a TLB: slow down the clock pipeline the TLB and cache access virtual address caches parallel TLB/cache access
PCInst TLB
Inst. Cache D Decode E M
Data TLB
Data Cache W+
TLB miss? Page Fault?Protection violation?
TLB miss? Page Fault?Protection violation?
November 13, 2015 http://csg.csail.mit.edu/6.175 L21-3
Physical vs Virtual Address Caches?
One cycle in case of a hit (+)cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-)aliasing problems due to the sharing of pages (-)
CPU PhysicalCacheTLB Primary
MemoryVA
PA
Alternative: place the cache before the TLB
CPU
VA
(StrongARM)VirtualCache
PATLB
PrimaryMemory
November 13, 2015 http://csg.csail.mit.edu/6.175 L21-4
Aliasing in Virtual-Address Caches VA1
VA2
Page Table
Data Pages
PA
VA1
VA2
1st Copy of Data at PA
2nd Copy of Data at PA
Tag Data
Two virtual pages share one physical page
Virtual cache can have two copies of same physical data. Writes to one copy not visible
to reads of other!General Solution: Disallow aliases to coexist in cacheSoftware (i.e., OS) solution for direct-mapped cache
VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same PA will conflict in direct-mapped cache (early SPARCs)
November 13, 2015 http://csg.csail.mit.edu/6.175 L21-5
Concurrent Access to TLB & Cache
Index L is available without consulting the TLBcache and TLB accesses can begin simultaneously
Tag comparison is made after both accesses are completedCases: L + b = k L + b < k
L + b > k what happens here?
VPN L b
TLB Direct-map Cache 2L blocks
2b-byte blockPPN Page Offset
=hit?
DataPhysical TagTag
VA
PA
VirtualIndex
k
Partially VA cache!November 13, 2015 http://csg.csail.mit.edu/6.175 L21-6
Virtual-Index Physical-Tag Caches: Associative Organization
VPN L = k-b b
TLB Direct-map2L blocks
PPN Page Offset
=hit?
Data
Phy.Tag
Tag
VA
PA
VirtualIndex
kDirect-map2L blocks
=
After the PPN is known, W physical tags are compared
Allows cache size to be greater than 2L+b bytes
W ways
November 13, 2015 http://csg.csail.mit.edu/6.175 L21-7
Exception handling in a pipeline machine
November 13, 2015 L21-8http://csg.csail.mit.edu/6.175
Exception Handling
PCInst. Mem D Decode E M
Data Mem W+
Illegal Opcode
Overflow Data address Exceptions
PC address Exception
ExternalInterrupts
ExD
PCD
ExE
PCE
ExM
PCM
Cau
seEP
C
Kill D Stage
Kill F Stage
Kill E Stage
Select Handler PC
Kill Writeback
Commit Point
1. An instruction may cause multiple exceptions; which one should we process?2. When multiple instructions are causing exceptions; which one should we process first?
from the earliest stage
from the oldest instructionNovember 13, 2015 http://csg.csail.mit.edu/6.175 L21-9
Interrupt processingInternal interrupts can happen at any stage but cause a redirection only at CommitExternal interrupts are considered only at CommitIf an instruction causes an interrupt then the external interrupt, if present, is given a priority and the instruction is executed again Some instructions, like Store, cannot be undone once
launched. So an instruction is considered to have completed before an external interrupt is taken
November 13, 2015 http://csg.csail.mit.edu/6.175 L21-10
Exception HandlingWhen instruction x in stagei raises an exception, its cause is recorded and passed down the pipeline For a given instruction, exceptions from the later stages of the pipeline do not override cause of exception from the earlier stages If an exception is present at commit: Cause and EPC registers are set, and pc is redirected to the handler PC Epoch mechanism takes care of redirecting the pc
November 4, 2015 http://csg.csail.mit.edu/6.175 L19-11
Killing vs Poisoning
PC
InstMemory
Decode
Register File
Execute
DataMemory
f2d
Epoch
m2cd2e
NextAddrPred
scoreboard
f12f2e2m
wrong path insts are dropped
wrong path insts are poisoned
This affects whether an instruction is removed from sb in case of an interrupt
exte
rnal
inte
rrup
ts c
onsi
dere
d at
Com
mit
November 4, 2015 http://csg.csail.mit.edu/6.175 L19-12
Interrupt processing at Execute
Incoming Interrupt
-if (mem type) issue Ld/St-if (mispred) redirect-pass eInst to M stage
-pass eInst to M stage unmodified
no yes
eInst will contain information about any newly detected interrupts at Execute
November 13, 2015 http://csg.csail.mit.edu/6.175 L21-13
Interrupt processing at Memory stage
Incoming Interrupt
-pass eInst with modified data to Commit
-pass eInst to Commit unmodified
no yesMemory Interrupt?
no yes
-pass new Cause to Commit
November 13, 2015 http://csg.csail.mit.edu/6.175 L21-14
Interrupt processing at Commit
External Interrupt?
EPC<= pc;causeR <= inCause;if (inCause after Reg Fetch) sb.rm;mode <= privilege;Redirect
no yes
Incoming interrupt
no yes no yes
-commit -sb.rm
Incoming interrupt
commit;sb.rm;EPC<= ppc;causeR <= Ext;mode <= privilege;Redirect
EPC<= pc;causeR <= Ext;if (inCause after Reg Fetch) sb.rm;mode <= privilege;Redirect
November 13, 2015 http://csg.csail.mit.edu/6.175 L21-15
Final comment
There is generally a lot of machinery associated with a plethora of exceptions in ISAsPrecise exceptions are difficult to implement correctly in pipelined machinesPerformance is usually not the issue and therefore sometimes exceptions are implemented using microcode
November 4, 2015 http://csg.csail.mit.edu/6.175 L19-16
The code slides follow
One-Cycle SMIPSrule doExecute;
let inst = iMem.req(pc);let dInst = decode(inst, csrf.getStatus);let rVal1 = rf.rd1(fromMaybe(?, dInst.src1));let rVal2 = rf.rd2(fromMaybe(?, dInst.src2));let eInst = exec(dInst, rVal1, rVal2, pc, ?);if(eInst.iType == Ld)
eInst.data <- dMem.req(MemReq{op: Ld, addr:eInst.addr, data: ?});
else if(eInst.iType == St)let d <- dMem.req(MemReq{op: St, addr:
eInst.addr, data: eInst.data});if (isValid(eInst.dst))
rf.wr(fromMaybe(?, eInst.dst), eInst.data);… setting special registers …… next address calculation …
endrule endmoduleNovember 4, 2015 http://csg.csail.mit.edu/6.175 L19-17
Type: Decoded Instructiontypedef struct {IType iType;AluFunc aluFunc;BrFunc brFunc;Maybe#(RIndx) dst;Maybe#(RIndx) src1;Maybe#(RIndx) src2;Maybe#(Data) imm;Maybe#(CsrIndx) csr;
} DecodedInst deriving(Bits, Eq);
typedef enum {Unsupported, NoPermit, Alu, Ld, St, J, Jr, Br,..., Syscall, ERet} IType deriving(Bits, Eq);
November 4, 2015 http://csg.csail.mit.edu/6.175 L19-18
Decodefunction DecodedInst decode(Data inst, Status status);DecodedInst dInst = ?; ...opSystem: begincase (funct3) ...fnPRIV: begin // privilege instdInst.iType = (case(inst[31:20])fn12SCALL: Syscall; // sys call// ERET can only be executed under privilege modefn12ERET: isPrivMode(status) ? Eret : NoPermit;default: Unsupported;
endcase);dInst.dst = Invalid; dInst.src1 = Invalid; dInst.src2 = Invalid; dInst.imm = Invalid; dInst.aluFunc = ?; dInst.brFunc = NT;
end ... endcaseend...return dInst;
endfunctionNovember 4, 2015 http://csg.csail.mit.edu/6.175 L19-19
Set special registersif (eInst.iType==Syscall)begin
csrf.setStatus(statusPushKU(csrf.getStatus)); csrf.setCause(32’h08); // cause for System callcsrf.setEpc(pc);
end elseif (eInst.iType==ERet) begin
cop.setStatus(statusPopKU(cop.getStatus));end
November 4, 2015 http://csg.csail.mit.edu/6.175 L19-20
Redirecting PCif (eInst.iType==Syscall)
pc <= csrf.getTvec;else if (eInst.iType==ERet)
pc <= cop.getEpc;else
pc <= eInst.brTaken ? eInst.addr : pc + 4;
November 4, 2015 http://csg.csail.mit.edu/6.175 L19-21
top related