conversion from one number base to another equation simplification conversion to/from sop/pos...
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Conversion from one number base to another
Equation simplification
Conversion to/from SOP/POS
Minimization using Karnaugh Maps
Minterm and Maxterm Equations
Determining Prime Implicants and Essential Prime Implicants
Logical completeness
Using MUXs and ROMs to implement logic
Timing Analysis
The internal structure of flip-flops
Flip-flop timings
Rising and falling edge triggered flip-flops
Counters and state machines
Generating next state equations from counter sequences.
Implementation using RS, D, T and JK flip-flops
Determining next states from schematics
Moore vs. Mealy State Graphs
Completeness and conflict issues
Creating transition tables and next state equations from state graphs
Verilog code
One-hot encoding
LC3 control
UART
Review for Final Exam
Conversion from one number base to another
Equation simplification
(X + Y)(X + Z) = (X + YZ)
X + XY = X
X + X’Y = X + Y
X + XY = X
Conversion to/from SOP/POS
(X + YZ) = (X + Y)(X + Z)
Minimization using Karnaugh Maps
AB
CD 00 01 11 10
00 1
01 1 1 1 1
11 1 1 1
10 1 1 1
AB + C’D + A’B’C + ABCD + AB’C
AB + C’D + B’C
Minterm and Maxterm Equations
F(ABCD) = m (0,2,4,7,9,12,14,15)
AB
CD 00 01 11 10
00 1 1 1
01 1
11 1 1
10 1 1
BC’D’ + BCD + ABC + A’B’D’ + AB’C’D
Determining Prime Implicants and Essential Prime Implicants
AB
CD 00 01 11 10
00 1 1 1
01 1 1 1 x
11 x x 1
10 1
6 prime implicants
3 essential prime implicants
Logical completeness
Inverter
Inverter AND gate
NAND
AND gate InverterInverter
InverterOR gate
Implementing Logic Functions With Muxes
Implement:
Z = A’B + BC’
4-to-1MUX Z
A B
I0
I1
I2
I3
for AB=00, Z=0
0A B
C 00 01 11 10
0 0 1 1 0
1 0 1 0 0
Implementing Logic Functions With Muxes
Implement:
Z = A’B + BC’
4-to-1MUX Z
A B
I0
I1
I2
I3
0
for AB=01, Z=1
1
A B
C 00 01 11 10
0 0 1 1 0
1 0 1 0 0
Implementing Logic Functions With Muxes
Implement:
Z = A’B + BC’
4-to-1MUX Z
A B
I0
I1
I2
I3
0
1
for AB=11, Z=C’
C’
A B
C 00 01 11 10
0 0 1 1 0
1 0 1 0 0
Implementing Logic Functions With Muxes
Implement:
Z = A’B + BC’
4-to-1MUX Z
A B
I0
I1
I2
I3
0
1
C’
A B
C 00 01 11 10
0 0 1 1 0
1 0 1 0 0
0
Implementing Logic Functions With Muxes
An alternate method
4-to-1MUX Z
A B
I0
I1
I2
I3
0
1
C’
0
Z = A’B + BC’
A=0 B=0
A=0 B=1
A=1 B=0
A=1 B=1
Z = 1 0 + 0 C’ = 0
Z = 1 1 + 1 C’ = 1
Z = 0 0 + 0 C’ = 0
Z = 0 1 + 1 C’ = C’
Using a ROM For Logic
A B C F G H
0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
Specify a truth table for a ROM which implements: F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C
Using a ROM For Logic
A B C F G H
0 0 0 0 10 0 1 0 10 1 0 1 10 1 1 0 01 0 0 0 11 0 1 0 01 1 0 1 11 1 1 1 0
Specify a truth table for a ROM which implements: F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C
Using a ROM For Logic
Specify a truth table for a ROM which implements: F = AB + A’BC’
G = A’B’C + C’
H = AB’C’ + ABC’ + A’B’C
A B C F G H
0 0 0 0 1 00 0 1 0 1 10 1 0 1 1 00 1 1 0 0 01 0 0 0 1 11 0 1 0 0 01 1 0 1 1 11 1 1 1 0 0
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
Timing Analysis
X
A
B = 1
C = 1
D
E
F A
B
AB
E
C
D
CD
F
E+F
X
The internal structure of flip-flops
R
S
Q
Q’
GATE
GS
GRD
Q’
Q
GATE
D
CLK
Q
Q’
D-type Flip-Flop
The internal structure of flip-flops
T-type Flip-Flop
CLK
Q
Q’
T
The internal structure of flip-flops
JK-type Flip-Flop
CLK
Q
Q’
J
K
Flip-flop timingsClock-to-Q
D
CLK
Q
Q’
tCLK ! Q = tNOT + tAND + 2 x tNOR
D
CLK
Q
Q’
tsetup = tNOT + tAND + 2 x tNOR
Flip-flop timingsSetup time
D
CLK
Q
Q’
thold = tNOT
Flip-flop timingsHold time
Flip Flop Timing
CLK
D
Q
tsetup
thold
tCLK ! Q
time
D
CLK
Q
Q’
Falling Edge Triggered DFF
Rising and falling edge triggered flip-flops
Rising Edge Triggered DFF
D
CLK
Q
Q’
Rising and falling edge triggered flip-flops
Generating next state equations from counter sequences.
Desired count sequence = 00 01 00 10 11 00 …
If current state = 00, next state = ?????
Implemented count sequence = 000 001 100 110 011 000 …
Q2 Q1 Q0 N2 N1 N0
0 0 0 0 0 10 0 1 1 0 01 0 0 1 1 01 1 0 0 1 10 1 1 0 0 00 1 0 X X X1 0 1 X X X1 1 1 X X X
N2 = Q2 Q1’ + Q1’ Q0N1 = Q2N0 = Q2’ Q0’ + Q1 Q0’
Implementation using RS, D, T and JK flip-flops
N/A111
N/A011
1101
Set1001
0110
Reset0010
1100
No change000 0
CommentQ+QRS
N/A111
N/A011
1101
Set1001
0110
Reset0010
1100
No change000 0
CommentQ+QRS
0111
Toggle1011
1101
Set1001
0110
Reset0010
1100
No change000 0
CommentQ+QKJ
0111
Toggle1011
1101
Set1001
0110
Reset0010
1100
No change000 0
CommentQ+QKJ
0x11
1x01
x110
x00 0
KJQ+Q
0x11
1x01
x110
x00 0
KJQ+Q
011
101
110
00 0
TQ+Q
011
101
110
00 0
TQ+Q
011
101
110
00 0
Q+QT
011
101
110
00 0
Q+QT
Determining next states from schematics
Q0
Q2
CLK
Q1
CLK
CLK
Q2
D Q
D Q
D Q
Q2
Q1’
Q1’
Q0
Q2’
Q0’
Q1
Q0’
Q2 Q1 Q0
0 0 0
0 0 1 1 0 0 1 1 0
Initial state
Moore vs. Mealy
Moore Mealy Outputs Function of Current
State Only Function of Current
State and Current I nputs Output Timing Outputs Available Af ter
Clock Transition (plus Gate Delays)
Outputs Available Anytime
(Af ter I nputs Stabilize) Delay Output Delayed One
Clock Cycle Output Available on Current Clock Cycle
Logic Requires more Requires less
For general purpose FSMs, the encoding ofthe states is usually not significant
For example, in the following state graph, the Encodings of the state are irrelevant
…Event 1Event 2Event 1
Event 2 Event 3
Completeness Issues
In order for a state graph to be complete:
• It must completely specify the FSM
• Paths leaving a state must specify all POSSIBLE cases
To check for completeness, OR together all of the exiting paths.If the result is “1” then the design is complete.
In order for a state graph to be conflict free:
• It must completely specify the FSM
•For a given set of input conditions, the transition from a state must be unique
To check for conflicts, AND together all pairs of the exiting paths. If the result is “0” for all pairs, the design has no conflicting transitions.
Conflict Issues
Creating transition tables and next state equations from state graphs
The resulting next state and output equations are:
N1 = Q0 + Q1 TDONE’ N0 = TOKEN Q1’ Q0’ CLRT = Q0 SPRAY = Q1
Dataflow OperatorsOperator
TypeOperatorSymbol
OperationPerformed
# ofOperands Comments
Arithmetic *, /, +, - As expected 2
* and / take LOTS of hardware
% Modulo 2Logical ! Logic NOT 1 As in C
&& Logic AND 2 As in C|| Logic OR 2 As in C
Bitwise ~ Bitwise NOT 1 As in C& Bitwise AND 2 As in C| Bitwise OR 2 As in C^ Bitwise XOR 2 As in C~^ Bitwise XNOR 2
Relational <, >, <=, >= As expected 2 As in CEquality ==, != As expected 2 As in CReduction & Red. AND 1 Multi-bit input
~& Red. NAND 1 Multi-bit input| Red. OR 1 Multi-bit input~| Red. NOR 1 Multi-bit input^ Red. XOR 1 Multi-bit input~^ Red. XNOR 1 Multi-bit input
Shift << Left shift 2 Fill with 0's>> Right shift 2 Fill with 0's
Concat { } Concatenate Any numberReplicate { { } } Replicate Any numberCond ?: As expected 3 As in C
IR
ALU
PC
AB
LC-3 InstructionsADD 0001 DR SR1 00 SR20
ADD 0001 DR SR1 imm51
AND 0101 DR SR1 00 SR20
AND 0101 DR SR1 imm51
BR 0000 n z p PCoffset9
JSR 0100 1
JMP 1100 0 00000000 BaseR
LD 0010 PCoffset9DR
LDI 1010 PCoffset9DR
LDR 0110 offset6DR BaseR
LEA 1110 PCoffset9DR
NOT 1001 DR SR 111111
RET 1101
RTI 1000 000000000000
STR 0111 offset6SR BaseR
TRAP 1111 trapvect80000
ST
STI
0011 PCoffset9SR
1011 PCoffset9SR
PCoffset11
1100 0 00000000 111 reserved
JSRR 0100 0 00000000 BaseR
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