cpe 201 digital design lecture 21: registers and counters (1)

CPE 201Digital Design

Lecture 21:

Registers and Counters (1)

Lecture Outline

• Registers

Registers – Introduction

• So far we introduced increasingly complex digital building blocks– Gates, multiplexers, decoders, basic registers, and

controllers• Controllers are good for systems with control

inputs/outputs– Control input: Single bit (or just a few),

representing environment event• e.g., 1 bit representing button pressed

– Data input: Multiple bits collectively representing single entity• e.g., 7 bits representing temperature in binary

Registers – Introduction

• Need building blocks for data– Datapath components, aka register-transfer-level

(RTL) components, store/transform data• Put datapath components together to form a datapath

• We will introduce several datapath components, and simple datapaths– Register: A group of flip-flops each storing one bit of

information– Registers include flip-flops and gates: flip-flops hold

the information, gates control how the information is transferred to the register

– Counter is a register that goes through a predetermined sequence of states

Registers

• Can store data, very common in datapaths

• Basic register: loaded every cycle– Useful for implementing FSM,

stores encoded state– For other uses, may want to

load only on certain cycles

Combinationallogic

State register

I3 I2 I1 I0

Q3Q2Q1Q0

reg(4)

Basic register loads on every clock cycle

How to extend to only load on certain cycles?

Q2Q3 Q1 Q0

4-bit register

Register with Parallel Load

To fully synchronize the system, clock signals should arrive at the same time at all flip-flops.

Therefore we should not control the clock by gates.

Load = 1, we load data

Load =0, register content does not change

• Add 2x1 mux to front of each flip-flop• Register’s load input selects mux input to pass

– Either existing flip-flop value, or new value to load

1 02×1

loadload

(c)(a)

I3 I2 I1 I0

Q3 Q2 Q1 Q0

Basic Example Using Registers

• Parallel transfer• This example will show

how registers load simultaneously on clock cycles– Notice that all load

inputs set to 1 in this example - just for demonstration purposes

Q3 Q2 Q1 Q0

a3 a2 a1 a0

I3 I2 I1 I0

Q3 Q2 Q1 Q0

I3ld1 I2 I1 I0

ld1 ld1

Q3 Q2 Q1 Q0

I3 I2 I1 I0

Basic Example Using Registers

Q3Q2Q1Q0

a3 a2 a1 a0

I3 I2 I1 I0

Q3Q2Q1Q0

I3ld1 I2 I1 I0

ld1 ld1

Q3Q2Q1Q0

I3 I2 I1 I0

R1????R2

–>1111

a3..a0

R1????R2

1111–>0001

R10000R2

0001–>1010

R11110R2

R10101R2

1 2 3 4 5

Register Example using the Load Input: Weight Sampler

• Scale has two displays– Present weight– Saved weight– Useful to compare present

item with previous item

• Use register to store weight– Pressing button causes

present weight to be stored in register

– Register contents always displayed as “Saved weight,” even when new present weight appears

Saved weight

Weight Sampler

Present weight clk

I3 I2 I1 I0

Q3 Q2 Q1 Q0

load3 pounds

0 0 1 1

3 pounds

0 0 1 0

2 pounds1

• Earlier example: Four simultaneous values from car’s computer

• To reduce wires: – computer writes only 1

value at a time, loads into one of four registers

• Was: 8+8+8+8 = 32 wires• Now: 8 +2+1 = 11 wires

Register Example: Above-Mirror Display

2×4 8

8-bit4×1

0001010

Loaded on clock edge

Shorthand notation

32 wires

Shift Register

• Shift right– Move each bit one position right– Shift in 0 to leftmost bit

1 1 0 1 Register contentsbefore shift right

0 1 1 0

Register contentsafter shift right

E.g.: Do four right shifts on 1001, showing value after each shift

A: 1001 (original)

shr_in

• Implementation: Connect flip-flop output to next flip-flop’s input

Shift Register

• To allow register to either shift or maintain value– Control input shr: 0 means maintain value, 1 shift– Input shr_in: value to shift in

• May be 0, or 1

– Use 2x1 muxes• Note: Can easily design shift register that shifts left instead

1 02×1

11 02×1

shr_in

shrshr_in

Q1 (b)

Q3 Q2 Q1 Q0

Rotate Register

• Rotate right: Like shift right, but leftmost bit comes from rightmost bit

1 1 0 1

1 1 1 0

Register contentsbefore rotate right

Register contentsafter rotate right

Shift Register Example: Above-Mirror Display

• Earlier example: 8 +2+1 = 11 wires from car’s computer to above-mirror display’s four registers– Better than 32 wires,

but 11 still a lot – want fewer for smaller wire bundles

• Use shift registers– Wires: 1+2+1=4– Computer sends one

value at a time, one bit per clock cycle

ralcom

8-bit4×1

r disp

i0s1 s0

shrshr_in

Note: this line is 1 bit, rather than 8 bits like before

Multifunction (Universal) Registers

shr_inshl_in

Q2 Q1 Q0Q3

I2 I1 I0I3

shl_inshr_ins1s0

(a) (b)

Operation

Maintain present value

Parallel load

Shift right

Shift left

• Many registers have multiple functions– Load, shift, clear (load all 0s)– And retain present value, of course

• Easily designed using muxes– Just connect each mux input to achieve

desired function

Maintain valueShift leftShift rightShift rightParallel loadParallel loadParallel loadParallel load

NoteOperations0s1

01110000

01001111

OutputsInputs

01010101

00110011

00001111

ld shr shl

Truth table for combinational circuit

Multifunction Registers with Separate Control Inputs

Maintain present valueShift leftShift right

Shift right – shr has priority over shlParallel load

Parallel load – ld has priorityParallel load – ld has priorityParallel load – ld has priority

Operationshlshrld

00001111

00110011

01010101

Q2 Q1 Q0Q3

I2 I1 I0I3

s1shr_in

shr_in

s0shl_in

shl_in

?combi-nationalcircuit

s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl

s0 = ld’*shr’*shl + ld

Register Operation Table

• Register operations typically shown using compact version of table– X means same operation whether value is 0 or 1

• One X expands to two rows• Two Xs expand to four rows

– Put highest priority control input on left to make reduced table simple

Maintain valueShift left

NoteOperations0s1

OutputsInputs

Shift rightShift right

Parallel loadParallel loadParallel loadParallel load

ld shr shl

MaintainvalueShift left

Operationld shr shl

Parallel loadXX1Shift rightX10

Register Design Process

• Can design register with desired operations using simple four-step process

Register Design Example

• Desired register operations– Synchronous clear, synchronous

set, load, shift left

Step 1: Determine mux size

5 operations: above, plus maintain present value (don’t forget this one!) Use 8x1 mux

Step 2: Create mux operation table

Step 3: Connect mux inputs

Step 4: Map control lines

OperationMaintain present valueParallel loadShift leftSynchronous clearSynchronous setMaintain present valueMaintain present valueMaintain present value

s001010101

s100110011

s200001111

7 6 3 2 1

s2s1s0

fromQn-1

Operation

Maintain present valueShift leftParallel load

Set to all 1sClear to all 0s

Inputs Outputs

s2 = clr’*sets1 = clr’*set’*ld’*shl + clrs0 = clr’*set’*ld + clr

Register Design Example

Step 4: Map control linesOperation

Maintain present valueShift leftParallel load

Set to all 1sClear to all 0s

Inputs Outputs

s2 = clr’*sets1 = clr’*set’*ld’*shl + clrs0 = clr’*set’*ld + clr

Q2 Q1 Q0Q3

I2 I1 I0I3

s0shl_in

shl_incombi-nationalcircuitset

Serial Transfer

• A digital system is in the serial mode when information is processed one bit at a time

• Serial transfer of information from A to B

Remember 4-bit Parallel Adder Circuit?

• For small digital circuits, serial addition requires less equipment

4-bit parallel adder

Serial Addition

• Slower compared to parallel addition, but uses less equipment

• Use shift registers– A, B hold data– Use a full adder– Carry out stored in

a D flip-flop

• PA uses more FAs compared to SA

• PA is a combinational circuit, SA is sequential

Which register holds the sum?

Serial Adder using Design Procedure

Present State Inputs Next State Output Flip-Flop inputs

Q (carry) x y Q (carry) S J0 K0

0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

• J0=xy • K0=x’y’= (x+y)’ • S=x y Q

0 x0 x0 x1 xx 1x 0x 0x 0

Serial 4-bit Parallel Adder Circuit

Readings

• Chapter 6– Sections 6.1 – 6.2

cpe 201 digital design lecture 21: registers and counters (1)

register56 register

datapathsbasic register

basic example

load inputs

basic registers

wires12register example

flipflopregisters load

mux input

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