cs 61c: great ideas in computer architecture …cs61c/fa16/lec/11/l11.pdfmips datapath summary cs...

CS61C:GreatIdeasinComputerArchitecture

Lecture11:Datapath

BernhardBoser&RandyKatz

http://inst.eecs.berkeley.edu/~cs61c

Agenda

• MIPSDatapath− add

§ instruction§ registertransferlevel§ circuit§ timing§ control

− and,…− addi,...− beq,…− j− lw,sw

• AndinConclusion,...

CS61c Lecture11:Datapath 2

Processor

CS61c Lecture11:Datapath 3

Processor

Control

Datapath

PC

Registers

Arithmetic&LogicUnit(ALU)

Memory

Bytes

Enable?Read/Write

Address

WriteData

ReadData

Processor-Memory Interface

Program

Data

Datapath: addu - Specs

• GreenCard• MIPSISAdocumentation

CS61c Lecture11:Datapath 4

DatapathDesign:addu• Instruction

• Effect- “Registertransferlevel,RTL”− PC ← PC + 4− R[$rd] ← R[$rs] + R[$rt]

CS61c Lecture11:Datapath 5

Type 31… format(bits) …0

R OpCode(6) rs (5) rt (5) rd (5) shmt (5) funct (6)

0x0 rs rt rd 0 0x21

Circuit:addu

• Registertransferlevel,RTL− PC ← PC + 4− R[$rd] ← R[$rs] + R[$rt]

CS61c Lecture11:Datapath 6

Type 31… format(bits) …0

R OpCode(6) rs (5) rt (5) rd (5) shmt (5) funct (6)

0x0 rs rt rd 0 0x21

Timing:addu

CS61c Lecture11:Datapath 7

Controller

CS61c Lecture11:Datapath 8

Controller

ControlSignals

• cALU− correctALUoperation:add,sub,or,…

• cRegW− Assert(1)towritetodest register− Registersunchangedif0

• Determinedby− OpCode− Func code(R-typeinstructions)

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Control:addu

CS61c Lecture11:Datapath 10

Control:addu

• Control− DeterminedfromOpCode andFunc

• Wewilldesignthecontrollerlater− Fornow,let’sjustremembertherequiredsignals

CS61c Lecture11:Datapath 11

OpCode Func cALU cRegW

0x0 0x21 add 1

Datapathforaddu - Summary

• Registertransferlevel,RTL− PC ← PC + 4− R[$rd] ← R[$rs] + R[$rt]

CS61c Lecture11:Datapath 12

Type 31… format(bits) …0

R OpCode(6) rs (5) rt (5) rd (5) shmt (5) funct (6)

0x0 rs rt rd 0 0x24

OpCode Func cALU cRegW

0x0 0x21 add 1

The61CMysteryChannelPresents…

CS61c Lecture11:Datapath 13

The mystery ofadd and addu

Detective61Ccheckstheevidence

Whichofthefollowingstatementsiscorrect?

CS61c Lecture11:Datapath 14

A B Cin S Cout

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Smoking Gunaka 1-bitaddertruthtable

Answer Statement

A TTisforsigned addition

B TT isforunsigned addition

C TTisincorrect,itssolepurpose istohidethecrime

D For32-bitthisisirrelevant,anyway

E TTisforsigned and unsignedaddition, since(Lecture1)withtwo’scomplement representationtheyaretheSAME

SinisterMotives• What’sthepurposeofhavingtwoinstructions,add addu?

− Midterm“trick”questions?• Overflowdiffersforsigned andunsigned!

− Lecture1• add

− Raisesexceptiononoverflow,assumingoperandsaretwo’scomplementsigned

• addu− Ignoresoverflow− Itcanthereforebeusedforsigned ANDunsignedtwo’scomplementnumbers

− Despiteitsname!• Whataboutexceptionsonunsignedoverflow?

− DesignyourownMIPS!− Nowyouknowwhyyouneedtotake61C!

CS61c 15

Whenuseadd, addu?

• Address(pointer)arithmetic:− signedoverflowmakesnosense− alwaysuseaddu

• Unsignedints− addu−won’treportoverflow!

• Signedints− add ifyoucareaboutoverflow

§ e.g.Fortran− addu ifyoudon’tcareaboutoverflow

§ e.g.C

CS61c Lecture11:Datapath 16

So…

• Sincein61CweprograminC−wealwaysuseaddu− andneveradd?

CS61c Lecture11:Datapath 17

You Got It!

Andafterthisinterlude…

•61Creturnsto−rigorous−alwayscrystalclear−andneverconfusing−engineeringfacts!

•Nomoremystery!

CS61c Lecture11:Datapath 18

Agenda

• MIPSDatapath− add

§ instruction§ registertransferlevel§ circuit§ timing§ control

− and,…− addi,...− beq,…− j− lw,sw

• AndinConclusion,...

CS61c Lecture11:Datapath 19

Datapathforand

• Registertransferlevel,RTL− PC ← PC + 4− R[$rd] ← R[$rs] & R[$rt]

• Sameasadd – exceptcALU− Dittoforsub, or, xor, …

Type 31… format(bits) …0

R OpCode(6) rs (5) rt (5) rd (5) shmt (5) funct (6)

0x0 rs rt rd 0 0x24

OpCode Func cALU cRegW

0x0 0x24 and 1

Agenda

• MIPSDatapath− add

§ instruction§ registertransferlevel§ circuit§ timing§ control

− and,…− addi,...− beq,…− j− lw,sw

• AndinConclusion,...

CS61c Lecture11:Datapath 21

Datapathforaddiu

• Registertransferlevel,RTL− PC ← PC + 4− R[$rt] ← R[$rs] + sign_ext(imm)

• Updateddatapathtosupportimmediate:

Type 31… format(bits) …0

I 0x9 rs (5) rt (5) immediate(16)

NewControlSignals

• cDstReg AddrDst =$rt (not$rd)• cImm ALUB=immediate(not$rt)• cSignExt Signextendimmediate

CS61c Lecture11:Datapath 23

SignExtension

CS61c Lecture11:Datapath 24

Type 31… format(bits) …0

I 0x9 rs (5) rt (5) immediate(16)

31… …0

31… …0

Signextension:

Nosignextension:

Controlforaddiu

Datapathforaddiu - Control

• Registertransferlevel,RTL− PC ← PC + 4− R[$rt] ← R[$rs] + sign_ext(imm)

CS61c Lecture11:Datapath 26

Instr OpCode Func cALU cRegW cRegDst cSignExt cImm

add 0x0 0x20 add 1 0 0 0

addi

Type 31… format(bits) …0

I 0x9 rs (5) rt (5) immediate(16)

Datapathforaddiu - Summary

• Registertransferlevel,RTL− PC ← PC + 4− R[$rt] ← R[$rs] + sign_ext(imm)

CS61c Lecture11:Datapath 27

Instr OpCode Func cALU cRegW cRegDst cSignExt cImm

add 0x0 0x20 add 1 0 0 0

addi 0x9 X add 1 1 1 1

Type 31… format(bits) …0

I 0x8 rs (5) rt (5) immediate(16)

YourTurn- ori

Answer OpCode Func cALU cRegW cRegDst cSignExt cImmA 0xd X or 0 1 0 1B 0xd X or 1 1 0 1C 0x0 0xd or 1 1 0 1D 0xd X ori 1 1 1 1E 0xd X or 1 1 1 1

I 0xd rs (5) rt (5) immediate(16)

YourTurn- ori

Answer OpCode Func cALU cRegW cRegDst cSignExt cImmA 0xd X or 0 1 0 1B 0xd X or 1 1 0 1C 0x0 0xd or 1 1 0 1D 0xd X ori 1 1 1 1E 0xd X or 1 1 1 1

I 0xd rs (5) rt (5) immediate(16)

GorillaTutoring

CS61c Lecture11:Datapath 30

• GorillaSessions−Wednesdays7:30– 9:30pm− 405Sodaor293Cory− 10tutors− review&practicequestions

• PrivateTutoring− 2tutors− 10studentsmax− Sign-upinstructionsonPiazza

Agenda

• MIPSDatapath− add

§ instruction§ registertransferlevel§ circuit§ timing§ control

− and,…− addi,...− beq,…− j− lw,sw

• AndinConclusion,...

CS61c Lecture11:Datapath 31

Datapathforbeq

CS61c Lecture11:Datapath 32

Type 31… format(bits) …0

I 0x5 rs (5) rt (5) offset(16)

• Registertransferlevel,RTL− PC ← PC + 4

+ if (R[$rs]==R[$rt]) then signext(4*off)else 0

Controlforbeq

CS61c Lecture11:Datapath 33

Type 31… format(bits) …0

I 0x4 rs (5) rt (5) offset(16)

Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBranch

addiu 0x9 X X add 1 1 1 1 0

addu 0x0 0x21 X add 1 0 0 0 0

beq

Controlforbeq

CS61c Lecture11:Datapath 34

Type 31… format(bits) …0

I 0x5 rs (5) rt (5) offset(16)

Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBranch

addi 0x8 X X add 1 1 1 1 0

add 0x0 0x20 X add 1 0 0 0 0

beq 0x4 X 1 sub 0 X X 0 1

beq 0x4 X 0 sub 0 X X 0 0

Datapathforbneq

CS61c Lecture11:Datapath 35

Type 31… format(bits) …0

I 0x5 rs (5) rt (5) offset(16)

Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBranch

beq 0x4 X 1 sub 0 X X 0 1

beq 0x4 X 0 sub 0 X X 0 0

bneq 0x5

Agenda

• MIPSDatapath− add

§ instruction§ registertransferlevel§ circuit§ timing§ control

− and,…− addi,...− beq,…− j− lw,sw

• AndinConclusion,...

CS61c Lecture11:Datapath 36

Datapathforj

CS61c Lecture11:Datapath 37

Type 31… format(bits) …0

J 0x2 targetaddress(26)

• Registertransferlevel,RTL− PC[2 … 28] ← target address

jDestinationaddress

CS61c Lecture11:Datapath 38

Type 31… format(bits) …0

J 0x2(6) targetaddress(26)

old 31…28 27…2 1…0

PC

new 31…28 27…2 1…0

PC

Controlforj

CS61c Lecture11:Datapath 39

Type 31… format(bits) …0

J 0x2 targetaddress(26)

Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBranch cJump

addiu 0x9 X X add 1 1 1 1 0 0

addu 0x0 0x21 X add 1 0 0 0 0 0

j 0x2 X X X 0 X X X X 1

Agenda

• MIPSDatapath− add

§ instruction§ registertransferlevel§ circuit§ timing§ control

− and,…− addi,...− beq,…− j− lw,sw

• AndinConclusion,...

CS61c Lecture11:Datapath 40

Datapathforlw

CS61c Lecture11:Datapath 41

Type 31… format(bits) …0

I 0x23 rs (5) rt (5) offset (16)

• Registertransferlevel,RTL− PC ← PC + 4− R[$rt] ← MEM[ R[$rs] + signext(offset) ]

Timingforlw

CS61c Lecture11:Datapath 42

Controlforlw

CS61c Lecture11:Datapath 43

Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBr cJ cLW cMemW

addiu 0x9 X X add 1 1 1 1 0 0 0 0

addu 0x0 0x21 X add 1 0 0 0 0 0 0 0

j 0x2 X X X 0 X X X X 1 X 0

lw 0x23

Controlforlw

CS61c Lecture11:Datapath 44

Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBr cJ cLW cMemW

addiu 0x9 X X add 1 1 1 1 0 0 0 0

addu 0x0 0x21 X add 1 0 0 0 0 0 0 0

j 0x2 X X X 0 X X X X 1 X 0

lw 0x23 X X add 1 1 1 1 0 0 1 0

Datapathforsw

CS61c Lecture11:Datapath 45

Type 31… format(bits) …0

I 0x15 rs (5) rt (5) offset (16)

• Registertransferlevel,RTL− PC ← PC + 4− MEM[ R[$rs] + signext(offset) ] ← R[$rt]

Controlforsw

CS61c Lecture11:Datapath 46

Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBr cJ cLW cMemW

addiu 0x9 X X add 1 1 1 1 0 0 0 0

addu 0x0 0x21 X add 1 0 0 0 0 0 0 0

j 0x2 X X X 0 X X X X 1 X 0

lw 0x23 X X add 1 1 1 1 0 0 1 0

sw 0x2b X X add 0 X 1 1 0 0 X 1

MIPSDatapathSummary

CS61c Lecture11:Datapath 47

Phase Action TimeSlot HardwareUsed1 Fetch instruction tIF InstrMemory2 Decodeinstr,readregisters tID Instr Dec, Register File3 Executeinstruction tEX ALU4 Accessdatamemory tMEM DataMemory5 Writeregister,PC tWB Register File,PC

Note:notallinstructionsareactiveinallphases

YourTurn

Answer Fewest MostA nor lwB bne swC j lwD jr lwE slt sw

CS61c Lecture11:Datapath 48

Whichinstructionisactiveinthefewest/mostphases?

YourTurn

Answer Fewest MostA nor lwB bne swC j lwD jr lwE slt sw

CS61c Lecture11:Datapath 49

Whichinstructionisactiveinthefewest/mostphases?

Agenda

• MIPSDatapath− add

§ instruction§ registertransferlevel§ circuit§ timing§ control

− and,…− addi,...− beq,…− j− lw,sw− dowhile

• AndinConclusion,...

CS61c Lecture11:Datapath 50

MIPS2000,4000,MIPS61C!

int j = -1;do

// a[i] = b[i] * c[i]; …i = i+j;

while (i != 0);

CS61c Lecture11:Datapath 51

Newinstructionthatupdatesi andbranches:dowhile $i, $j, label

dowhile $rt, $rs, label

CS61c Lecture11:Datapath 52

• Registertransferlevel,RTL− R[$rt] = R[$rt] + R[$rs]− PC ← PC + 4

+ if (R[$rs]==R[$rt]) then signext(4*off)else 0

Type 31… format(bits) …0

I 0x61c* rs (5) rt (5) offset(16)

*justreplaceoneofthelessusefulinstructions…

Controlfordowhile

CS61c Lecture11:Datapath 53

Instr OpCode Zero cALU cRegW cRegDst cSignExt cImm cBr cJ cLW cMemW

dowhile 0x61c

Controlfordowhile

CS61c Lecture11:Datapath 54

Instr OpCode Zero cALU cRegW cRegDst cSignExt cImm cBr cJ cLW cMemW

dowhile 0x61c 1 add 1 1 X 0 1 0 0 0

0 add 1 1 X 0 0 0 0 0

Agenda

• MIPSDatapath− add

§ instruction§ registertransferlevel§ circuit§ timing§ control

− and,…− addi,...− beq,…− j− lw,sw

• AndinConclusion,...

CS61c Lecture11:Datapath 55

AndinConclusion,…

• Universaldatapath− CapableofexecutingallMIPSinstructions− Notallunits(hardware)usedbyallinstructions

• 5Phasesofexecution− IF,ID,EX,MEM,WB− Notallinstructionsareactiveinallphases

• Controllerspecifieshowtoexecuteinstructions− Even“new”ones…(dowhile)

CS61c Lecture11:Datapath 56