cs eee f241 introduction jan 16th 2016

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Microprocessor Programming

and Interfacing

Dr. Runa Kumari

Assistant Professor

EEE Department

BITS Pilani Hyderabad Campus

About the Course

2 1/19/2016

Course No. : CS/ECE/EEE/INSTR F241

Course Title : Microprocessor Programming & Interfacing

Instructor-in-charge : Dr. Runa Kumari

Lecture Class Timings : Tue, Thus, Sat 11:00 to 11:50 AM

at F102 and F105

Tutorial Timing : Thursday 8.00 Am at F102, F103 and F105

Lab Timings : Mon, Tue, Wed, Thus, Fri 15:00 to 17:00

Tue, Thus, Sat - 9:00 to 11:00 AM at D-329

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Course description

• Study of Programmer model of X86 processors, processor

architecture, addressing modes and instructions set of X86

processors.

• Assembly programming using different instructions,

subroutines and macros etc.

• Concept of Interrupts.

• Memory Interfacing.

• Programmable peripheral devices.

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Text Books

Text Book:

Barry B Brey, The Intel Microprocessors .Pearson, Eight Ed.

Reference Book:

Douglas V Hall, Microprocessor and Interfacing, TMH,

Second Edition.

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COURSE PLAN

No. Topic to be covered Learning Objective

Ref. To Text

Book and

Reference Book

Compute Architecture,

Memory & I/O organization,

CISC/RISC processors

Introduction to Microprocessor

and Microcomputers

Ch-1 (T1, R1)

2-3 8086 Microprocessor Microprocessor & its

architecture

Ch-2 (T1, R1)

4-6 Addressing Modes Assembly Programming Ch-3 (T1)

Instruction Set & ALP Assembly Programming Ch-4-6, 8 (T1)

13-15 Pin Out, Modes of operation,

Clocking, Buses

8086/8088 Hardware

Specifications Ch-9 (T1)

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COURSE PLAN

Memory Devices, Address

Decoding- Memory Interface 8086-

Memory Interface Ch-10 (T1)

Basic I/O interfacing (I/O mapped

I/O and Memory mapped I/O)

I/O port address decoding

I/O Interfacing

Ch-11.1, 11.2

24-26 Types of interrupts, Vector tables,

Priority Schemes Interrupts

Ch-12.1, 12.2

27-29 8255,8254,ADC,DAC, 8259 Programmable Peripheral

Devices

11.3-11.6, &

12.3-12.6 (T1)

Basic Operation, 8237, Shared Bud,

Disk Memory Systems, Video

Displays

DMA controller Ch-13 (T1)

32-33 ISA, PCI, Com, USB,AGP Bus Interface Ch-15 (T1)

34-36 80186-80286 Advanced microprocessor Ch-16 (T1)

37-39 80386-80486 Advanced microprocessor

Ch-17 (T1)

EVALUATION SCHEME

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Component Duration Marks Date & Time Evaluation type

Test-I 60 min 45 29/02/2016

4:00-5:00 PM Closed Book

Test-II 60 min 45 09/04/2016

4:00-5:00 PM Open Book

Surprise Quiz 15 min each 45 Closed Book

Lab 2Hrs/week 45 - Open / Closed Book

Compre. Exam. 3 hours 120 12/05/2016 AN

Open Book

Total 300

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Chamber Consultation: Room No. D322

Mon-Sat: 12:00 to 13:00 P.M

email: runakumari@hyderabad.bits-pilani.ac.in

Notices: CMS

Make–up: No make-up will be given for Surprise Quiz and Lab final Exam.

For Tests and Comprehensive Examination make-up examination will be given

only in extremely genuine cases for which prior permission of the instructor-in-

charge is required.

Motivation to Study Microprocessors

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Recent Development

– 64 bit laptop

– I5 and I7 processors

Job Market (Leading companies)

– Probably one of most easy and highly paid jobs

– Intel, AMD, Motrola, Sun Microsystems, Texas

Instruments, National Instruments, MIPS Technologies

– Many Microprocessor and Microcontroller based

Companies in India

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Introduction to Microprocessors

Block diagram of a Computer System

ROM/- -/RAM

KBD Display

DISK Printer

ADDRESS/CONTROL/DATA BUS

• First general-purpose, programmable electronic computer system

developed in 1946. (at University of Pennsylvania )

Electronic Numerical Integrator and Calculator (ENIAC), a

huge machine.

over 17,000 vacuum tubes;

500 miles of wires

weighed over 30 tons

about 100,000 operations per second

History

ENIAC - The first Electronic computer (1946)

Programmed by rewiring its circuits.

process took many workers several days

workers changed electrical connections on

plug-boards like early telephone switchboards

Required frequent maintenance.

vacuum tube service life a problem

December 23, 1947, John Bardeen, William Shockley,

and Walter Brattain develop the Transistor at Bell

The First Integrated Circuit – Jack Kilby, Texas Instruments

1 Transistor and 4 Other Devices on 1 Chip

In the year 1958

The Intel 4004 – 2,300 Transistors, 1 MHz operation

THE FIRST COMPUTER ON A SINGLE CHIP

BEGINNING OF LARGE SCALE INTEGRATION TECHNOLOGY

The First Microprocessor -- 1971

• The world's first microprocessor, the Intel 4004, was a

4-bit microprocessor-a programmable controller on a

• It addressed a mere 4096 (12 address lines) 4-bit

memory locations.

• Its instruction set contained only 45 different

instructions.

First General-Purpose Microprocessor -- 1974

8-Bit Intel 8080 and 8085 , Intel Corporation – 4,500

Transistors

Intel 8086 microprocessor (1978)

• Microprocessors that are common today include the

8086/8088, which were the first 16-bit

microprocessors.

• Following these early 16-bit machines were the 80286,

80386, 80486, Pentium, Pentium Pro, Pentium II,

Pentium III, Pentium 4, and Core2 processors.

• The architecture has changed from 16 bits to 32 bits

and to 64 bits.

One of the Most Powerful 16-Bit Microprocessors --

The Motorola 68000

WELL INTO THE LARGE SCALE INTEGRATION ERA

Intel Pentium (IV) microprocessor 2000

In the early 1970s, CMOS technology replaced NMOS-only

logic which started suffering from high power consumption.

Ever since, CMOS has been the dominant digital technology.

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Memory

I/O Interface

Data bus

Processor

Address bus

Control bus

IO device IO device

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CPU on a Single VLSI Chip

WHAT HAPPENS WHEN YOU TURN ON YOUR COMPUTER ?

BIOS –Basic Input Output System

• Resident in ROM

Orchestrates loading the computer's operating system from the hard disk drive

into RAM

OS Loads Program from Disk (Secondary Storage) to RAM (Primary Storage)

(Program -Set of Instructions –Executed by μp)

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Instructions in Microprocessor

WHAT IS INSTRUCTIONS?

Tells the μp what action to perform

• Arithmetic, Logic Operation

• Read Data from Input Device

• Write to memory OR Output Device

• Reset

• Stop

Example: ADD A,B Assembly Language

A,B -Registers

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Instructions in Microprocessor

HOW DOES A MICROPROCESSOR HANDLE AN INSTRUCTION?

Fetch Cycle

The fetch cycle takes the instruction required from memory, stores

it in the instruction register

Execute Cycle

The actual actions which occur during the execute cycle of an

instruction

Microprocessor Data

Control

signals

Bus Microprocessor

-Fetches Instruction

-Executes Instruction

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Size of Microprocessor

SIZE OF A MICROPROCESSOR

• Size of Data Bus

• Size of Registers

• Size of ALU

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Microprocessor Bus

PROCESSOR BUS

ADDRESS BUS:

No of Address lines

• 20 lines –A19–A0

• 1 M Byte of memory can be addressed

DATA BUS:

No of Data lines

• 16 lines –D15–D0

• 64K

CONTROL LINES:

-Active low signals

• MEMR

• MEMW

• IOR

• IOW

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Memory of Microprocessors

PROCESSOR MEMORY

• ROM

Non-Volatile

Read Only

• RAM

Volatile

Random Access Memory

MEMORY DATA SIZE

• Bit Organized

• Nibble Organized

• Byte Organized

Memory

Add Bus

Data Bus

Memory –

Registers to hold bits

4 bits

8 Registers

Address lines : 3 (Unidirectional)

Data lines : 4 (Bidirectional)

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Processors

ISA (Instruction Set Architecture)

• Execution model

• Processor registers

• Address and Data formats

Microarchitecture

• Interconnections -various micro architectural elements of machine

• ALU

• Data Path

• Control Path

Physical Realization

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Processors

WHAT IS THE EFFECT ?

• If Instructions is present anywhere

• Size of Instruction varies

-Complicates Instruction Decoder

CISC (Complex Instruction Set Computer)

Operands for Arithmetic/Logic operation can be in Register/ Memory

RISC (Reduced Instruction Set Computer)

Operands for Arithmetic/Logic operation only in Registers

Register –Register Architecture

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RISC vs CISC

Goal: Multiply data in mem A with B

and put it back in A

MUL A,B

LDA R0,A

LDA R1,B

MUL R0,R1

STR A,R0

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RISC vs CISC

CPU-SPEEDUP

1 Instruction Per Cycle (1 IPC)

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Basic Parallel Techniques

• Pipelining

• Replication

INSTRUCTION PIPELINES

Instruction:

• Fetch

• Decode

• Execute

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VLIW & SUPERSCALAR ARCHITECTURE

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FLYNN’S TAXNOMY

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FLYNN’S TAXNOMY

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FLYNN’S TAXNOMY

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FLYNN’S TAXNOMY

Core duo micro processor

Quad- core microprocessor

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EVOLUTION OF MICROPROCESSOR

cs eee f241 introduction jan 16th 2016

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