delay optimization & logical efforts

1

Delay Optimization And

Logical Efforts

2

Delay in a Logic Gate• Delay has two components: d = f + p• f: effort delay = gh (a.k.a. stage effort)

– Again has two components• g: logical effort

– Measures relative ability of gate to deliver current

– g 1 for inverter• h: electrical effort = Cout / Cin

– Ratio of output to input capacitance– Sometimes called fanout

• p: parasitic delay– Represents delay of gate driving no load– Set by internal parasitic capacitance

3

Effective Resistance for Delay Estimation

• Shockley models have limited value– Not accurate enough for modern transistors– Too complicated for much hand analysis

• Simplification: • Replace Ids(Vds, Vgs) with effective resistance R such that Ids = Vds/R in series

with a switch.– R averaged across switching of digital gate (i.e. during linear mode of

operation)

– Too inaccurate to predict current at any given time because Ids rolls off with Vds increase and R decreases

– But good enough to predict RC delay which is the product of driver resistance and the load capacitance.

)(11

)(

1VtVgsW

LCoxVtVgs

LCoxWR

4

Switch Level RC Delay Model• Use equivalent circuits for MOS transistors ( Usually logic gates use minimum length devices for least delay, area and power consumption)Thus delay of the logic gate depends on the widths of transistors and the capacitance driven by the gate.

– Ideal switch + capacitance and ON resistance– Unit nMOS has effective resistance R,

capacitance C– Unit pMOS has effective resistance 2R(to 3R –

due to lower mobility), capacitance C• Capacitance proportional to width• Resistance inversely proportional to width

5

kgs

dg

s

d

kCkC

kCR/k

kgs

dg

s

d

kC

kC

kC

2R/k

Input capacitance

Output capacitance

Equivalent RC circuit models

6

UNIT Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

d = 6RC

7

Drawing Multiple Input Circuits That Has Resistance Equal To Unit

Inverter

2

2

22

1 1

4

4

8

Example: 3-input NAND• Sketch a 3-input NAND with transistor widths chosen to

achieve effective rise and fall resistances equal to a unit inverter (R).

3

3

3

2 2 2

9

2 2 2

3

3

3

2 2 2

3

3

33C

3C

3C

3C

2C

2C

2C

2C

2C

2C

3C

3C

3C

2C 2C 2C2 2 2

3

3

33C

3C

5C

5C

5C

9C

3-input NAND Caps• Annotate the 3-input NAND gate with gate and diffusion

capacitance.

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Example: 3-input NAND• Estimate worst-case rising and falling delay of 3-input

NAND driving h identical gates.

9C

3C

3C3

3

3

222

5hCY

n2

n1h copies

9 5pdrt h RC

3 3 3 3 3 33 3 9 5

11 5

R R R R R Rpdft C C h C

h RC

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Contamination Delay• Best-case (contamination) delay can be substantially

less than propagation delay.• Ex: If all three inputs fall simultaneously

59 5 33 3cdrRt h C h RC

9C

3C

3C3

3

3

222

5hCY

n2

n1

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Delay Components• Delay has two parts

– Parasitic delay• 9 or 11 RC• Independent of load

– Effort delay• 5h RC• Proportional to load capacitance

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Example• Sketch a 2-input NOR gate with selected

transistor widths so that effective rise and fall resistances are equal to a unit inverter’s. Annotate the gate and diffusion capacitances.

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Electrical Effort:h = Cout / Cin

Nor

mal

ized

Del

ay: d

Inverter2-inputNAND

g = p = d =

g = p = d =

0 1 2 3 4 5

0

1

2

3

4

5

6

Delay Plots

d = f + p =

gh + p

• What about NOR2?

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Computing Logical Effort• DEF: Logical effort is the ratio of the input capacitance of a

gate to the input capacitance of an inverter delivering the same output current.

• Measure from delay vs. fanout plots• Or estimate by counting transistor widths

A Y A

B

YA

BY

1

2

1 1

2 2

2

2

4

4

Cin = 3g = 3/3

Cin = 4g = 4/3

Cin = 5g = 5/3

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Catalog of Gates

Gate type Number of inputs

1 2 3 4 n

Inverter 1

NAND 4/3 5/3 6/3 (n+2)/3

NOR 5/3 7/3 9/3 (2n+1)/3

Tristate / mux 2 2 2 2 2

XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8

• Logical effort of common gates

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Catalog of Gates

Gate type Number of inputs

1 2 3 4 n

Inverter 1

NAND 2 3 4 n

NOR 2 3 4 n

Tristate / mux 2 4 6 8 2n

XOR, XNOR 4 6 8

• Parasitic delay of common gates– In multiples of pinv (1)

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Example: Ring Oscillator• Estimate the frequency of an N-stage ring oscillator

Logical Effort: g = 1Electrical Effort: h = 1Parasitic Delay: p = 1Stage Delay: d = 2Frequency: fosc = 1/(2*N*d) = 1/4N

31 stage ring oscillator in 0.6 m process has frequency of ~ 200 MHz

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Example: FO4 Inverter

• Estimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g = 1Electrical Effort: h = 4Parasitic Delay: p = 1Stage Delay: d = 5

d

The FO4 delay is about

300 ps in 0.6 m process

15 ps in a 65 nm process

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Multistage Logic Networks• Logical effort generalizes to multistage networks

• Path Logical Effort

• Path Electrical Effort

• Path Effort

iG g

out-path

in-path

CH

C

i i iF f g h

10 x y z 20g1 = 1h1 = x/10

g2 = 5/3h2 = y/x

g3 = 4/3h3 = z/y

g4 = 1h4 = 20/z

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Multistage Logic Networks

• Logical effort generalizes to multistage networks• Path Logical Effort

• Path Electrical Effort

• Path Effort

• Can we write F = GH?

iG gout path

in path

CH

C

i i iF f g h

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Paths that Branch

• No! Consider paths that branch:

G = 1H = 90 / 5 = 18GH = 18h1 = (15 +15) / 5 = 6h2 = 90 / 15 = 6F = g1g2h1h2 = 36 = 2GH

5

15

1590

90

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Branching Effort

• Introduce branching effort– Accounts for branching between stages in path

• Now we compute the path effort– F = GBH

on path off path

on path

C Cb

C

iB bih BH

Note:

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Multistage Delays

• Path Effort Delay

• Path Parasitic Delay

• Path Delay

F iD f

iP p

i FD d D P

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Designing Fast Circuits

• Delay is smallest when each stage bears same effort

• Thus minimum delay of N stage path is

• This is a key result of logical effort– Find fastest possible delay– Doesn’t require calculating gate sizes

i FD d D P

1ˆ Ni if g h F

1ND NF P

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Gate Sizes

• How wide should the gates be for least delay?

• Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives.

• Check work by verifying input cap spec is met.

ˆ

ˆ

out

in

i

i

CC

i outin

f gh g

g CC

f

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Example: 3-stage path

• Select gate sizes x and y for least delay from A to B

8 x

x

x

y

y

45

45

AB

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Example: 3-stage path

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27Electrical Effort H = 45/8Branching Effort B = 3 * 2 = 6Path Effort F = GBH = 125Best Stage EffortParasitic Delay P = 2 + 3 + 2 = 7Delay D = 3*5 + 7 = 22 = 4.4 FO4

8 x

x

x

y

y

45

45

AB

3ˆ 5f F

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Example: 3-stage path• Work backward for sizes

y = 45 * (5/3) / 5 = 15x = (15*2) * (5/3) / 5 = 10

P: 4N: 4

45

45

AB

P: 4N: 6 P: 12

N: 3

8 x

x

x

y

y

45

45

AB

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Best Number of Stages• How many stages should a path use?

– Minimizing number of stages is not always fastest• Example: drive 64-bit datapath with unit

inverter

D = NF1/N + P= N(64)1/N + N

1 1 1 1

8 4

16 8

2.8

23

64 64 64 64

Initial Driver

Datapath Load

N:f:D:

16465

2818

3415

42.815.3

Fastest

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Derivation

• Consider adding inverters to end of path– How many give least delay?

• Define best stage effort

N - n1 Extra InvertersLogic Block:n1 Stages

Path Effort F 11

11

N

n

i invi

D NF p N n p

1 1 1

ln 0N N Ninv

D F F F pN

1 ln 0invp

1NF

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Best Stage Effort• has no closed-form

solution

• Neglecting parasitics (pinv = 0), we find = 2.718 (e)

• For pinv = 1, solve numerically for = 3.59

1 ln 0invp

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Review of DefinitionsTerm Stage Pathnumber of stages

logical effort

electrical effort

branching effort

effort

effort delay

parasitic delay

delay

iG gout-path

in-path

CCH

N

iB bF GBH

F iD f

iP pi FD d D P

out

in

CCh

on-path off-path

on-path

C CCb

f gh

f

p

d f p

g

1

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Method of Logical Effort

1) Compute path effort2) Estimate best number of stages3) Sketch path with N stages4) Estimate least delay5) Determine best stage effort

6) Find gate sizes

F GBH

4logN F

1ND NF P

1ˆ Nf F

ˆi

i

i outin

g CC

f

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Limits of Logical Effort

• Chicken and egg problem– Need path to compute G– But don’t know number of stages without G

• Simplistic delay model– Neglects input rise time effects

• Interconnect– Iteration required in designs with wire

• Maximum speed only– Not minimum area/power for constrained delay

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Example 1

Calculate the • a) logical effort• b) parasitic delay• c) effort and • d) delay in the following 6-input AND implementations as a function of the path

electrical effort H. Which implementation is the fastest if a) H=1, b) H=5 and c) H=20?

(a) (b) (c) (d)

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Example 2

• For the path between x and F in the following circuit calculate:

• a. Total delay• b. Path effort and parasitic delay• c. minimum theoritical delay

6

8

420C

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Summary

• Logical effort is useful for thinking of delay in circuits– Numeric logical effort characterizes gates– NANDs are faster than NORs in CMOS– Paths are fastest when effort delays are ~4– Path delay is weakly sensitive to stages, sizes– But using fewer stages doesn’t mean faster paths– Delay of path is about log4F FO4 inverter delays– Inverters and NAND2 best for driving large caps

• Provides language for discussing fast circuits– But requires practice to master