design of low voltage low power neuromorphic systems
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Design of Low Voltage Low Power Neuromorphic Circuits using
Cadence Tools
© Syed Muffassir M.S.Ali 1
Dept. of Electronics and Telecommunication EngineeringShri Guru Gobind Singhji Institute of Engineering and Technology, Nanded, India.
*muffassir@gmail.com ‘ssgajre@sggs.ac.in
Introduction to Neuromorphic Engg
Low Voltage Low Power Design
Translinear Circuits Design
Neuron Circuit Design
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Neuron Circuit Design
WTA Design
Conclusion
References
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Neuromorphic EngineeringNeuromorphic EngineeringNeuromorphic EngineeringNeuromorphic EngineeringBrian-like computing on silicon
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� What is Neuromorphic Circuit Design?An interdisciplinary approach to the design of informationsystems.
� What it is?“As engineers, we would be foolish
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to ignore the lessons of a billion
years of evolution.” C. Mead(1993)
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Exploit the physics of silicon to reproduce the bio-physics of neural systems.
�Drift and diffusion equations form a built-in Barrier . (Vbi versus Nernst Potential)�Exponential distribution of particles.(Ions in biology and electrons/holes in silicon)
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(Ions in biology and electrons/holes in silicon)
Both biological channels and transistors have a gating mechanism that modulates a channel.
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�Massive Parallel Sytems: Huge number of elements that are highly interconnected and works in parallel.
�Collective Computation: Information is distributed over the whole neural system in the processing elements, performing together the computation required.
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required.
�Adaptation: Adapt itself to the processing according the evolution of stimulus.
�Exploitation of all Properties of Structures : Low power consumption, small area, and they do not need large S/N ratio or precision to accomplish the neural information processing.
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LV /LP DESIGNLV /LP DESIGNLV /LP DESIGNLV /LP DESIGN
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� Why Low Voltage?
� Why Low Power?
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� Why CMOS?
� Why Analog?
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� Techniques for Voltage Reduction….
1. Circuits with rail-to-rail operating range.
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2. Technique of cascading stages, instead of a single cascodestage.
3. Supply multipliers.
4. Nonlinear processing of the signals.
� Techniques for Current Reduction….
1. Adaptive Biasing
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2. Subthreshold Biasing
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TranslinearTranslinearTranslinearTranslinear Circuits DesignCircuits DesignCircuits DesignCircuits Design
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In 1975, Barrie Gilbert coined the term translinear to describe a class of circuits whose large-signal behavior hinges both on the precise exponential I/V relationship of the bipolar transistor and on the intimate thermal contact and close matching of monolithically integrated devices.
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In 1975, Barrie Gilbert coined the term translinear to describe a class of circuits whose large-signal behavior hinges both on the precise exponential I/V relationship of the bipolar transistor and on the intimate thermal contact and close matching of monolithically integrated devices.
The word translinear refers to the exponential I/V characteristics of the BJT trans linear
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– its transconductance is linear in its collector current.
In 1975, Barrie Gilbert coined the term translinear to describe a class of circuits whose large-signal behavior hinges both on the precise exponential I/V relationship of the bipolar transistor and on the intimate thermal contact and close matching of monolithically integrated devices.
The word translinear refers to the exponential I/V characteristics of the BJT trans linear
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– its transconductance is linear in its collector current.
Gilbert also meant the word translinear to refer to circuit analysis and design principles that bridge the gap between familiar territory of linear circuits and the uncharted domain of nonlinear circuits.
Consider a closed loop of base-emitter junctions of four closely matched npnbipolar transistors biased in the forward-active region and operating at the same temperature. Kirchhoff’s voltage law (KVL) implies that
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This result is a particular case of Gilberts translinear principle. The product of clockwise currents is equal to the product of the counterclockwise currents.
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(a)Stacked Loop (b) Alternating Loop
Neuron Circuit DesignNeuron Circuit DesignNeuron Circuit DesignNeuron Circuit Design
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A Neuron is an electrically excitable cell that processes and transmits information by electrical and chemical signalling.
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� Soma�Dendrites�Axon
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(a)The Neuron Model (b)The Neuron Circuit
�Differentially Coding the Information:Low noise and low interference.
�Current Mode of Operation: (a) Highly roboust.
(b) Wide dynamic range.
(c) easy implementation of sums .
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(c) easy implementation of sums .
�Weak Inversion Region of Operation of Transistors:LV / LP operation.
� Translinear Circuits: Versatile and efficient.
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where
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The inputs are:
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Parameter Value
Power 0.58nW
Voltage 0.7V
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THD 3.563%
W/L {M1-M12} 32.4u/0.18u
W/L{Mp1-Mp2} 1u/12u
Technology 180nm
[15] [16] [17] [18] ThisCircuit
Process 0.35 2 0.35 0.35 180
Supply Voltage(V) 3V 1.5V 1.5V 2V 0.7V
mµ mµ mµ mµ nm
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Supply Voltage(V) 3V 1.5V 1.5V 2V 0.7V
Power Consumed NA 3.1 6.7 5.5 0.58Wµ Wµ Wµ nW
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Winner Take all Circuit Winner Take all Circuit Winner Take all Circuit Winner Take all Circuit
DesignDesignDesignDesign
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Transient analysis for the sinusoidal input currents of 20nA peak-peak at the frequencies of 1MHz, 2MHz and 5MHz for Iin1, Iin2 and Iin3 is shown. Since the circuit is Winner Take
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Iin3 is shown. Since the circuit is Winner Take All, as expected the output currentfollows the envelope of the input currents.
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Conclusions and Future!Conclusions and Future!Conclusions and Future!Conclusions and Future!
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Neuromorphic Engineering is relatively young field. However, it is already producing some very popular products.
Using these circuits one can realize
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Using these circuits one can realize Neuromorphs which will learn on their own with few thousand neurons easily and efficiently.
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Successfully simulated the neuroncircuit and winner take all circuit which are the building blocks of any neuromorphic systems. The voltage supply for the circuits used is 0.7 V and the power consumption is very low compared
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the circuits used is 0.7 V and the power consumption is very low compared to the results found in literature for respective circuits in the 180nm process
technology paving the way for the efficient realization of the NEUROMOPHS.
ReferencesReferencesReferencesReferences
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1. C. Mead, Analog VLSI and Neural Systems. Reading,MA: Addison-Wesley Publishing Company, 1989.
2. J. W. Nauta and M. Feirtag, “The organization of the Brain,” Scientific American, 1979.
3. W. S. McCulloch and W. H. Pitts, “A Logical Calculus of the Ideas Imminent in Nervous Activity,” Bull.Math.Biophy, vol. 5, pp. 113–133, 1943.
4. E. C. Mead, M. Ismail, Analog VLSI Implementation of Neural Systems.Boston,MA: KluwerAcademic Publishers, 1989.
5. E. A. Vittoz, “Analog VLSI Signal Processing: Why,Where, and How?,” Journal of VLSI Signal Processing, vol. 8, pp. 27–44, 1994.
6. B.Gilbert, “TranslinearCircuits: A Proposed Classification,” Electronics Letters, vol. 11, no. 1, pp.
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6. B.Gilbert, “TranslinearCircuits: A Proposed Classification,” Electronics Letters, vol. 11, no. 1, pp. 14–16, 1975.
7. D. M.Binkley, Tradeoffs and Optimization in Analog CMOS Design. The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England: John Wiley & Sons Ltd, 2008.
8. B. Sekerkiran and U. Cilingiroglu, “Improving the Resolution of Lazzaro Winner-Take-All Circuit,” International Conference on Neural Networks, vol. 2, pp. 1005–1008, 1997.
9. S. Hemati and A. H. Banihashemi, “A Current Mode Maximum Winner-Take- All Circuit with Low Voltage Requirement for Min-Sum Analog Iterative De Decoders,” Proceedings of the 2003 10th IEEE International Conference on Electronics Circuits and Systems, 2003. ICECS 2003, vol. 1, pp. 4–7, 2003.
10. M. Rahman, K. Baishnab, and F. Talukdar, “A Novel High Precision Low Power Current Mode CMOS Winner-Take-All Circuit,” Int.J.Engineering Science and Technology, vol. 2, no. 5, pp. 1384–1390, 2010.
11. J. A. Startzyk and X. Fang, “CMOS Current-Mode Winner-Take-All Circuit with both Excitatory and Inhibitory Feedback,” Electronic Letters, vol. 29,no. 10, pp. 908–910, 1993.
12. A. Fish, V. Milrud, and O. Yadid-Pechit, “High Speed and High Precision Current Winner-Take All Circuit,” IEEE transactions on Circuits and Systems-II,vol. 52, no. 3, pp. 131–135, 2005.
13. D.Moro-Frias, M.T.Sanz-Pascual, and c.A.de la Cruz Blas, “A Novel Current Mode Winner-Take-All Topology,” European Conference on Circuit Theory and Design(ECCTD), no. 20, pp. 134–137, 2011.
14. Z. S. Gnayand E. S. Sinencio, “CMOS Winner-Take-All Circtuis: A Detail Comparison,”
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14. Z. S. Gnayand E. S. Sinencio, “CMOS Winner-Take-All Circtuis: A Detail Comparison,” Proceedings of 1997 IEEE International Symposium on Circuits and Systems ISCAS ’97, vol. 1, pp. 41–44, 1997.
15. Cyril Prasanna Raj P, S.L. Pinjare, “Design and Analog VLSI Implementation of Neural Network” EJSR.Vol.27 No.2 (2009), p.199-216.
16. S. Liu, C. Chang, “CMOS subthreshold four quadrant multiplier based on unbalanced source coupled pairs” Int .J. Electronics, vol.78,No.2, pp 327-332,Feb.1995.
17. W. Liu, S. Liu, “Design of a CMOS low-power and low-voltage four-quadrant analog multiplier” AICSP, pp.307-312, Sept. 2009.
18. M. Gravati, M. Valle, G. Ferri, N. Guerrini, L. Reyes , “A Novel Current-Mode Very Low Power Analog CMOS Four QuadrantMultiplier”, Proc. ESSCIRC,Grenoble,France,2005.
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Syed Muffassir M. S. Ali*, Dr. S. S. Gajre’Shri Guru Gobind Singhji Institute of Engineering and Technology, Nanded
*muffassir@gmail.com, ‘ ssgajre@sggs.ac.in*+91-9637228663
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