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Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads 1
Digital Microelectronic
Circuits
(361-1-3021 )
Parasitic Capacitance and
Driving a Load
Presented by: Dr. Alex Fish
Lecture 5:
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Motivation
Thus far, we have learned how to model our essential
building block, the MOSFET transistor, and how to use
these building blocks to create the most popular logic
family, Static CMOS.
We analyzed the characteristics of a static CMOS inverter,
including its Static and Dynamic Properties.
We saw that both the delay and the power consumption of
a CMOS gate depend on the load capacitance of the gate.
2
20.69pd eq Load dynamic DDt R C P f C V
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
What will we learn today?
Today, we will go back to our MOSFET transistor to try and
understand what parasitic capacitances are inherent to its
structure.
Then, we will develop a model for equivalent capacitance
estimation for delay calculation of a CMOS inverter.
Accordingly, we will examine the optimal sizing of a CMOS
gate.
And finally, we will develop a methodology for sizing a
chain of inverters to drive a large load.
3
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
What will we learn today?
4
5.1 MOSFET Capacitance
5.2 Inverter Delay
Capacitance Model
5.3 Driving a Load
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
MOSFET
CAPACITANCE
So back to our device, let’s see what
parasitic capacitances we have:
5
5.25.1 MOSFET Capacitance
5.2 Inverter Delay
Capacitance Model
5.3 Driving a Load
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
MOSFET Capacitance
One of the important parameters of a MOS Transistor is its
capacitance.
The MOSFET has two major categories of capacitance:
» Gate/Channel Capacitance – capacitance caused by the insulating
oxide layer under the gate.
» Junction Capacitance – pn-Junction capacitance between the
diffusions and the substrate.
6
tox
n + n +L
p-substrate
CDBCSB
CGC
CGDCGS
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Gate Capacitance
The Gate Capacitance includes:
» Gate to Channel Capacitance, CGC:
The main capacitance that is
dependent on the region of operation.
In general:
» Gate Overlap Capacitance, CGDO, CGSO:
A constant (small) capacitance caused
by gate overlap of the diffusions.
7
oxGC ox
ox
C WL C WLt
GSO GDO OverlapC C WC
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Gate Capacitance
Looking at gate capacitance as a function of biasing shows
how it changes.
» In accumulation, the capacitance is across the oxide.
» As VGS grows, the depletion layer decreases the capacitance
(as if the dielectric gets longer)
» Once the channel is formed, the capacitance jumps.
» At pinch-off, the drain capacitance drops to zero.
8
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Gate Capacitance
9
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Gate Capacitance
To model this non-linear behavior, we will use the
following approximations:
10
All capacitance is
towards substrate
Capacitance
symmetrically divided
between source and drain
All capacitance to
Source
GB oxC C WL2
oxGCS GCD
C WLC C
2
3GCS oxC C WL
Question: How do we relate to Velocity Saturation?
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Junction (Diffusion) Capacitance
The Junction Capacitance is the diffusion capacitance of the
MOSFET.
This is measured according to fabrication parameters
11
2
diff bottom sidewalls
j jsw
j diff jsw diff
C C C
C Area C Perimiter
C L W C L W
Diffusion cap is non-linear and
voltage dependent.
For simplicity, we will take it as
constant in this course.
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
MOSFET Capacitance Summary
Dependence of MOS capacitances on W and L:
12
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
MOSFET Capacitance Summary
13
DS
G
B
CGDCGS
CSB CDBCGB
GS GCS GSOC C C
GD GCD GDOC C C
GB GCBC C
SB SdiffC C DB DdiffC C
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
INVERTER DELAY CAPACITANCE MODEL
OK, so we saw that the MOSFET has a bunch of non-linear
parasitic capacitances, which makes them tough to use. To
simplify life we’ll now develop an:
14
5.25.1 MOSFET Capacitance
5.2 Inverter Delay
Capacitance Model
5.3 Driving a Load
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Capacitance Modeling
As we saw, MOSFET capacitances are non-constant and
non-linear.
Therefore, it is hard to solve a general equation for an
arbitrary transition/operation.
Instead, we will develop a simple model that will
approximate the capacitances during a specific transition
that interests us.
In this case, we are looking for the Load Capacitance to
use when finding the gate delay.
Therefore, we will apply a step function to the input of an
inverter and approximate the capacitances according to the
MOSFET parasitics we just learned.
15
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Capacitance Modeling
Let’s look at a CMOS inverter with all
its parasitic capacitances:
» Considering the Gates of the
transistors are the inputs to the
inverter, any capacitor touching the
gate should be considered
input capacitance.
» Considering the Drains of the
transistors are connected to the
inverter output, any capacitor touching
the Drains should be considered
output capacitance.
16
CGDN
CGDP
CGSN
CGSP
CDBP
CSBP
CSBN
CDBN
CGBN
CGBP
G
S
D
B
G
S
D
B
Vin Vout
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Capacitance Modeling
We have to differentiate between output (intrinsic)
capacitances and load (extrinsic) capacitances.
Our total load capacitance is
17
Driver
Load
Cint Cext
Cwire
Cin,2Cout,1
,1 ,2Load out wire inC C C C
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Intrinsic (Output) Capacitance
We’ll now look at what makes up the
intrinsic output capacitance of the driver.
This is primarily made up of diffusion
capacitances:
» Both drain-to-body capacitances have a terminal
with a constant voltage and the other connected
to the output.
» For a simple computation, we will replace them
with an equivalent capacitance to ground.
» These capacitances are very non-linear and we
will not go into their calculation in this course.
18
CDBP
CDBN
CDBP
+CDBN
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Intrinsic (Output) Capacitance
How about feedthrough capacitance?
» Taking the input step as ideal, the gate-to-source
and gate-to-body capacitances don’t contribute to
the propagation delay.
» The source-to-body capacitance is shorted to
the supply, so it doesn’t switch.
What about the gate-to-drain capacitance?
» While the gate voltage rises (Vin), the drain voltage
drops (Vout) and vice versa.
» According to the Miller Effect, we can move this
capacitance relative to ground, doubling its value.
» This can be regarded as overlap capacitance, as
for the majority of the transition the devices are in
cutoff or saturation.
19
CGSP+CGBP
CGSN+CGBN
CGDP+CGDN
2(CGDP
+CGDN)
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
The Miller Effect
A capacitor experiencing identical, but opposite
voltage swings at both its terminals can be
replaced by a capacitor to ground, whose value is
twice the original value.
20
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Summary of Intrinsic Output Cap
21
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Now, to annotate the parasitics during switching, we will
cascade another inverter after the first.
We first add the Wire Capacitance.
Then we add the gate capacitances of
the second inverter.
» These are approximately the oxide
capacitance times the area:
» Again, we can just add the pMOS gate
capacitance to the general capacitance to
ground.
N1
P1 P2
N2
External Capacitance
22
CGN2
CGP2
CW
2 2 2 2 2 2GN GP OX N N P PC C C W L W L
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
External Capacitance
What happened to overlap capacitance and the
Miller Effect on CGD2?
» Remember that this is an approximate model, but…
» L=Leff+2*Lov, so CG=Cox*W*Ldrawn.
» During the transient, for most of the time the load gate’s
transistors are in cutoff or in linear.
» Miller effect won’t appear, because the second gate
won’t switch until tpd1 is over.
Therefore:
» YES, CGD2 and CGS2 contribute to the load capacitance.
» BUT, a good approximation is just CG2=COX*W*L
23
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Summary of Next Stage Input Cap
24
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Parasitic Capacitances - Summary
Altogether, as a very general approximation, we get:
An even more general approximation
with N fan-out gates gives us:
25
N1
P1 P2
N2
CGN2
CGP2
CDBN1
+CW
CGDP1+CGDN1
CDBP1
1 1 1 1 2 22( )load GDP GDN DBP DBN GP GN WC C C C C C C C
load out wire inC C C N C
Miller Diffusion Load
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Last Time…
CMOS Inverter Capacitance Model for tpd.
26
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Last Time…
MOS Capacitance Model
» Driver Cap (Cout or Cint): Diffusion + Miller
» Load Cap (Cin or Cg): Gate cap, no miller
27
load out wire inC C C N C
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
DRIVING A LOAD
Up till now, we discussed device sizing with an
optimal fanout of 1. What happens if we want to
cascade more gates to the output?
28
5.35.1 MOSFET Capacitance
5.2 Inverter Delay
Capacitance Model
5.3 Driving a Load
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
External Capacitance
Up till now, we assumed our inverter was only driving a
copy of itself. This is known as intrinsic or unloaded delay.
But we usually will have a larger fanout, and in some
cases, we will need to drive large loads.
Let’s remember how we defined our load capacitance:
We can now write our delay
equation according to these
components.
29
load diff overlap fanout wire
int ext
C C C C C
C C
int0.69 0.69pd eq load eq extt R C R C C
Driver
Load
Cint Cext
Cwire
Cin,2Cout,1
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Sizing Factor (S)
This means that if we add a larger
load, our delay will increase. This is intuitive, as it means
we have to supply more current from the same source.
If we were to widen our transistors by a factor S, this would
decrease our resistance and increase our intrinsic
capacitance.
30
int0.69pd eq extt R C C
* *
int int eq eqC S C R R S
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Sizing Factor (S)
These two factors trade-off, which is why we get an optimal
inverter size.
However, upsizing our gate doesn’t affect the external
capacitance and therefore decreases the loaded delay.
31
int0.69pd eq extt R C C * *
int int eq eqC S C R R S
* * *
, int int int0.69 0.69 0.69eqpd unloaded eq eq
Rt R C S C R C
S
*
int int 0
int int
0.69 0.69 1 1eq ext ext
pd ext eq p
R C Ct SC C R C t
S SC SC
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Sizing Factor (S)
32
0int
0 int
1
0.69
extp p
p eq
Ct t
SC
t R C
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Driving a Large Load
So now we have a very large load to drive.
We could just use a very large inverter.
» But then someone would have to drive this large
inverter.
So considering we start with a limited input
capacitance, how should we best drive this load?
34
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Inverter Chain
If CL is given:
» How many stages are needed to minimize the
delay?
» How to size the inverters?
Anyone want to guess the solution?
35
CL
In Out
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Delay Optimization Problem #1
To solve an optimization problem, we need a set of
constraints:
» Load Capacitance.
» Number of Inverters.
» Size of input capacitance.
36
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Delay Optimization Problem #1
To explore this problem, we must define
a proportionality factor, γ.
γ is a function of technology*, that describes the
relationship between a gate’s input gate capacitance (Cg)
and its intrinsic output capacitance (Cint):
37
int gC C
* γ is close to 1 for most submicron processes!
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Delay Optimization Problem #1
Now, we will write the delay as a function of γ, and the
effective fanout, f:
We can see that the delay for a certain technology is only a
function of the effective fanout!
38
int gC C
0 01 1extpd p p
g
C ft t t
C
ext
g
Cf
C
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Inverter with Load
So we see that the delay
increases with ratio of load
to inverter size:
tp0 is the intrinsic delay of an unloaded inverter.
γ is a technology dependent ratio.
f is the Effective Fanout – ratio of load to inverter size
39
0 1p p
ft t
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Sizing a chain of inverters
Now we will express the delay
of a chain of inverters:
Assuming a negligible wire capacitance,
for the j-th stage, we get:
And we can write the total delay as:
40
, 1
, 0 0
,
1 1g jj
pd j p p
g j
Cft t t
C
, 1
, 0
1 1 ,
1N N
g j
pd pd j p
j j g j
Ct t t
C
0 1p p
ft t
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Sizing a chain of inverters
We have N-1 unknowns, so we will derive N-1 partial
derivatives:
We receive a set of constraints:
This means that:
» Each inverter is sized up by the same factor, f.
» Each inverter has the same effective fanout, fj=f.
» Each inverter has the same delay, tp0(1+f/ γ).
41
, 1
0
1 ,
1N
g j
pd p
j g j
Ct t
C
,
0pd
g j
t
C
, 1 ,
, , 1 , 1
, , 1
g j g j
g j g j g j
g j g j
C CC C C
C C
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Sizing a chain of inverters
Now this is interesting…
what if we multiply the fanout of each stage?:
We found the ratio between input and load capacitance!
42
, 1 ,2 ,3 ,4 ,
1 1 , ,1 ,2 ,3 , 1 , ,1
N Ng j g g g g NN load load
j
j j g j g g g g N g N g
C C C C C C Cf f
C C C C C C C
,1/ NNload gf C C F
,1
load
g
CF
C
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Sizing a chain of inverters
We defined the overall effective fanout, F, between the input
and load capacitance of the circuit. Using this parameter,
we can express the total delay:
43
Nf F,1
load
g
CF
C
0 1N
pd p
Ft N t
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads 44
Example: 3 Stages
CL= 8 C1
In Out
C11 f f 2
283 f
CL/C1 has to be evenly distributed across N = 3 stages:
S=1 S=2 S=4
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Delay Optimization Problem #2
Great – but what is the optimal Number of Stages?
This is a new Optimization Problem. You are given:
» The size of the first inverter
» The size of the load that needs to be driven
Your goal:
» Minimize delay by finding optimal number and sizes of
gates
So, need to find N that minimizes:
45
0 1N
p p
Ft N t
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Delay Optimization Problem #2
Starting with a minimum sized inverter with Cg,min, and
driving a given load, Cload, we can see that:
» With a small number of stages, we get a large delay due to the
effective fanout (f, F).
» With a large number of stages, we get a large delay due to the
intrinsic delay (Ntp0)
To find the optimal number of stages, we will differentiate
and equate to zero.
46
0 1N
pd p
Ft N t
0pddt
dN ln
0N
N F FF
N exp 1opt
opt
ff
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Delay Optimization Problem #2
This equation only has an analytical solution for the case of
γ=0. In this esoteric case we get:
If we take the typical case of γ=1, we can numerically solve
the equation and arrive at:
47
0lnoptN F
02.718optf e
13.6optf
3.61
logoptN F
exp 1optopt
ff
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Example
We are given:
We need to find the optimal
number of stages, so fopt=4.
So we need 3 stages that will be sized 1, 4, 16.
Let’s inspect what delay we would have gotten with
various number of stages.
48
min
min
64L
in
C C
C C
4
64
log log 64 3opt
L
in
opt f
CF
C
N F
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads 49
Example
1 64
1 8 64
1 644 16
1 642.8 8 22.6
N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
0 1N
pd p
Ft N t
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Normalized delay function of F
Let’s consider the trade offs of
driving loads with various approaches:
» Unbuffered
» Two-Stages
» Optimal FO4 Chain
For a small load, F=10:
» Unbuffered delay: tpd=11tp0
» Two Stage delay: tpd=8.3tp0
» Optimal FO4 Chain: Nopt=2tpd=8.3tp0
50
0 1N
pd p
Ft N t
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Normalized delay function of F
For a slightly larger load, F=100:
» Unbuffered delay: tpd=101tp0
» Two Stage delay: tpd=22tp0
» Optimal FO4 Chain: Nopt=4 tpd=16.6tp0
» We see a large benefit for one extra stage, but the
inverter chain might not be worth it.
How about a really large load, F=10000:
» Unbuffered delay: tpd=10001tp0
» Two Stage delay: tpd=202tp0
» Optimal FO4 Chain: Nopt=7 tpd=33.1tp0
» But we “pay” for this with a large number of stages and
huge final stage inverter (W=1mm)
51
0 1N
pd p
Ft N t
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
What about Energy (and Area)?
How much additional Energy (and Area) does an
inverter chain cost?
» Using a single (minimal) inverter, our capacitance would
be:
» But the capacitance of N stages
52
1
min min min1 1 ... 1 N
N stages LC C fC f C C
1 min minstage LC C C C
1
1 min min1 ... 1 N
stageC fC f C
Overhead!
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
What about Energy (and Area)?
So the overhead cap is:
For example:
53
2
min1 1 ... N
overheadC fC f f
1
min
11
1
NffC
f
min20 , 50LC pF C fF
520400, 5, 400 3.3
50opt
pFF N f
fF
15 117.62 3.3 50 10 9.7
4overheadC pF
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Example Overhead Numbers
For the previous example:
54
Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads
Conclusions
In order to drive a large load, we should:
» Use a chain of inverters.
» Each inverter should increase its size by the same
amount.
» To minimize the delay, we should set the effective fanout
to about 4.
Remember!
» You have to use a whole number of stages (i.e. you can’t
choose 2.5 stages).
» Therefore, choose the closest number of stages for close
to optimal effective fanout..
» Choose according to signal polarity or optimal speed.
» But fewer stages means less power!55
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