ece2030 introduction to computer engineering lecture 1: overview prof. hsien-hsin sean lee school of...
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ECE2030 Introduction to Computer Engineering
Lecture 1: Overview
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee
School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering
Georgia TechGeorgia Tech
22
• Instructor: Prof. Hsien-Hsin “Sean” Lee• Email: leehs@gatech.edu• Course web:
http://www.ece.gatech.edu/~leehs/ECE2030
• My office: Klaus 2318• Teaching Materials:
– Morris Mano and Charles Kime, “Logic and Computer Design Fundamentals,” the 4th edition
– Course notes and handouts (check out course web)– TA: to be announced later
• Attending classes is important !!
ECE2030 Syllabus
33
ECE2030 Syllabus • Grading policy
– 3 Homework assignment: 5% each– 1 Programming assignment: 10%– 3 in-class exams: 15% each – 1 final exam: 30%– [100,90]=A; (90,80]=B; (80,70]=C,(70,55]=D,
(55,0]=F– Will scale…
• All homework: turn-in in the first 5 minutes “in class” of the due day
• All exams: closed books, closed notes, no calculator
• Honor code • Use T-Square (http://tsquare.gatech.edu)
for your homework and exam grades
44
Objective: Digital Design Principle• Number systems• Boolean algebra• Switch and CMOS design • Combinational logic
– Logic gates– Building blocks: de/mux, de/encoder, shifters,
adder/subtractor, multiplier– Logic minimization– Mixed logic
• Sequential logic– Latches, Flip-flops– Counters– State machines: Mealy/Moore machines
55
Objective: Digital Design Principle
• Memory and Programmable Devices– Register, RAM, ROM, PLA, PAL
• Architectural concept– Instruction set architecture (ISA)– Stored-Program Computer and Sequential
Control (von Neumann architecture)– Datapath– Branches
• Processor and Software Convention– MIPS ISA– Procedural calls: Stack
66
Hierarchy of Computation
ProblemProblemProblemProblem AlgorithAlgorithmsmsAlgorithAlgorithmsms
Programming inProgramming inHigh-Level LanguageHigh-Level LanguageProgramming inProgramming inHigh-Level LanguageHigh-Level Language
Compiler/Assembler/Compiler/Assembler/LinkerLinkerCompiler/Assembler/Compiler/Assembler/LinkerLinker
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA) BinaryBinaryBinaryBinary
System architectureSystem architectureSystem architectureSystem architecture
Target Machine Target Machine (one implementation)(one implementation)Target Machine Target Machine (one implementation)(one implementation)Micro-architectureMicro-architectureMicro-architectureMicro-architecture
Functional units/Functional units/Building blocksBuilding blocksFunctional units/Functional units/Building blocksBuilding blocks
Gates Level Gates Level Design Design
Gates Level Gates Level Design Design
TransistorsTransistorsTransistorsTransistors ManufacturingManufacturingManufacturingManufacturing
77
Hierarchy of Computation
ProblemProblemProblemProblem AlgorithAlgorithmsmsAlgorithAlgorithmsms
Programming inProgramming inHigh-Level LanguageHigh-Level LanguageProgramming inProgramming inHigh-Level LanguageHigh-Level Language
Compiler/Assembler/Compiler/Assembler/LinkerLinkerCompiler/Assembler/Compiler/Assembler/LinkerLinker
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA) BinaryBinaryBinaryBinary
System architectureSystem architectureSystem architectureSystem architecture
Target Machine Target Machine (one implementation)(one implementation)Target Machine Target Machine (one implementation)(one implementation)Micro-architectureMicro-architectureMicro-architectureMicro-architecture
Functional units/Functional units/Building blocksBuilding blocksFunctional units/Functional units/Building blocksBuilding blocks
Gates Level Gates Level Design Design
Gates Level Gates Level Design Design
TransistorsTransistorsTransistorsTransistors ManufacturingManufacturingManufacturingManufacturing
System LevelSystem LevelSystem LevelSystem Level
Human LevelHuman LevelHuman LevelHuman Level
RTL Level RTL Level RTL Level RTL Level
Logic Level Logic Level Logic Level Logic Level
Circuit Level Circuit Level Circuit Level Circuit Level
Silicon Level Silicon Level Silicon Level Silicon Level
88
Our Focus in 2030
Hierarchy of Computation
ProblemProblemProblemProblem AlgorithAlgorithmsmsAlgorithAlgorithmsms
Programming inProgramming inHigh-Level LanguageHigh-Level LanguageProgramming inProgramming inHigh-Level LanguageHigh-Level Language
Compiler/Assembler/Compiler/Assembler/LinkerLinkerCompiler/Assembler/Compiler/Assembler/LinkerLinker
Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA)Instruction Set Architecture (ISA) BinaryBinaryBinaryBinary
System architectureSystem architectureSystem architectureSystem architecture
Target Machine Target Machine (one implementation)(one implementation)Target Machine Target Machine (one implementation)(one implementation)Micro-architectureMicro-architectureMicro-architectureMicro-architecture
Functional units/Functional units/Building blocksBuilding blocksFunctional units/Functional units/Building blocksBuilding blocks
Gates Level Gates Level Design Design
Gates Level Gates Level Design Design
TransistorsTransistorsTransistorsTransistors ManufacturingManufacturingManufacturingManufacturing
System LevelSystem LevelSystem LevelSystem Level
Human LevelHuman LevelHuman LevelHuman Level
RTL Level RTL Level RTL Level RTL Level
Logic Level Logic Level Logic Level Logic Level
Circuit Level Circuit Level Circuit Level Circuit Level
Silicon Level Silicon Level Silicon Level Silicon Level
99
Zoom-in a System Component
1010
John BardeenWilliam ShockleyWalter Brattain
Circa. 1947, Bell Labs
Nobel Prize in Physics 1956
G
D S
Switch
1111
Inventors of Integrated Circuits
Robert Noyce
Jack Kilby
Nobel Prize in Physics 2000
“The Tyranny of Numbers” Challenge
1212
Fairchild Traitorous 8
Gordon E. Moore circa. 1965
1313
Moore’s Law
Exponential growthExponential growth
Transistor count will be doubled every 18 monthsTransistor count will be doubled every 18 months Gordon Moore, Intel co-founder
42millions
2,250
10 μm13.5mm2
1.7 billionsMontecito
90 nm596 mm2
1414
A Generic Intel-based PC System
Your CPU hereYour CPU here
1515
Dual-Core Itanium 2 (Montecito)
1616
Integrated Circuit Complexity
Source: Intel
1717
Minimum Feature Size
We are currently at 0.065µm (65nm) and moving towards 0.045µm
1818
Average Transistor Price per year
Source: Dataquest
1919
Processor Market Segmentation
High PerformanceHigh Performance(e.g., Intel 32/64, AMD, Itanium, IBM POWER, BlueGene, Sun T1, etc)(e.g., Intel 32/64, AMD, Itanium, IBM POWER, BlueGene, Sun T1, etc)
High PerformanceHigh Performance(e.g., Intel 32/64, AMD, Itanium, IBM POWER, BlueGene, Sun T1, etc)(e.g., Intel 32/64, AMD, Itanium, IBM POWER, BlueGene, Sun T1, etc)
Embedded / low-powerEmbedded / low-power(e.g., ARM, MIPS, Xscale)(e.g., ARM, MIPS, Xscale)Embedded / low-powerEmbedded / low-power
(e.g., ARM, MIPS, Xscale)(e.g., ARM, MIPS, Xscale)
Special purposeSpecial purpose(e.g., DSP, NVidia)(e.g., DSP, NVidia)Special purposeSpecial purpose
(e.g., DSP, NVidia)(e.g., DSP, NVidia)
2020
Analog Signal vs. Digital
• So, why Digital?
2121
Binary Signals
• So, why Binary?
2222
Voltage Range of Binary Signals
0.0 Volts
1.0 Volts
2.0 Volts
3.0 Volts
4.0 Volts
5.0 Volts
INPUTINPUT OUTPUTOUTPUT
HIGH (1)HIGH (1)
LOW (0)LOW (0)
HIGH (1)HIGH (1)
LOW (0)LOW (0)
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