eng3640 microcomputer interfacing
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ENG3640 Microcomputer Interfacing
Week #3
Assembly Language Design and Structure
ENG3640 Fall 2012 2
Topics Stopping a Program. Software Delay Routine. Assembly Language Design and Structure. Program Structure and Organization. D-Bug12 Utility Routines. The CPU12 Instruction Set
Data Transfer Logical Operations Using the Stack Subroutine Calls Arithmetic Operations (Add, Sub, Mult, Div)
ENG3640 Fall 2012 3
Resources
Huang, Chapter 4 Sections 2.6 Program Loops 2.10 Program Execution Time 4.10 Using D-Bug12 Functions
ENG3640 Fall 2012 4
Stopping a Program1. STOP: stop processing
stops internal clocks, puts the processor in the standby mode
recovery from STOP may be accomplished by RESET^ or an interrupt
2. Stop_here BRA Stop_here BRA (rel) Branch always Opcode: 20 Operation:
PC ← (PC) + $002 + rr
3. End Directive:
any statement following the END directive will be ignored by the assembler.
4. SWI: software interrupt
When executed it stacks the registers, and executes an ISR. Works like a break point in your program.
RECOMMENDED!
ENG3640 Fall 2012 5
Software Delay Routines Software delay routines are used to
synchronize the execution of a program with respect to time:
1. Temporarily display a message
2. To debounce a switch on a keyboard!
3. To wait for an EEPROM to be erased. So in many applications the execution of a
routine must be timed to meet external requirements.
ENG3640 Fall 2012 6
Subroutine Program Flow
Bsr func
Bsr func
func
rts
The rts instruction returns program flow to the instruction following the last subroutine call!
bsr saves the PC on the stack before going to func.
ENG3640 Fall 2012 7
Delay Routines: Issues In order to design a software delay
routine, we must know how to calculate the time it takes to execute the instructions that make up the routine!
Main problem with software delays is that their timing characteristics change if interrupts are used!
Also, the CPU has to have a deterministic instruction execution time (i.e. No pipelining!)
ENG3640 Fall 2012 8
Instruction Timing The instruction execution time is determined
by: 1. Bus Frequency of the CPU2. Number of cycles required by the instruction
The number of cycles depend on many things:
1. Size of opcode.2. The number of arguments.3. Size of the data bus.4. Complexity of execution.
ENG3640 Fall 2012 9
Program Execution Time
The number of cycles executed by each Instruction are detailed in the CPU12 Manual
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CPU12: Instruction Execution Time
To convert the number of cycles to time, we must know the bus frequency of the CPU
CPU12 bus frequency is based on the E-clock.
For the MC68HC12A4 the E-clock (FE) is one half of the oscillator or crystal frequency found on the XTAL and EXTAL inputs.
The crystal frequency of the MC68HC12A4 is 16MHz, so FE = 8MHz
ENG3640 Fall 2012 11
CPU12: Total Execution Time
The total execution time (Tex) is then given by:
Tex = N x TE
where
N = total number of clock cycles
TE = the E-clock period, 1/FE
12
Simple Delay: Implementation
ldx #1 ; [2] E cycles
loop psha ; [2] E cycles
pula ; [3] E cycles
psha ; [2] E cycles
pula ; [3] E cycles
nop ; [1] E cycle
nop ; [1] E cycle
dbne x,loop ; [3] E cycles
Total cycles 15 clock cycles (excluding ldx)@ 8MHz (125 ns) 125 x 15 = 1.875 uS
ENG3640 Fall 2012
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Example1: Simple DelayExample: Write an instruction sequence to create 100 ms time delay.
Solution:1. Previous loop takes 1.875 us2. We have to find out the number that should be
loaded with the index register x?3. 100 ms / 1.875 us 53,333
ENG3640 Fall 2012 14
Example2: 100ms DelayExample: Write an instruction sequence to create 100 ms time delay.
ldx #53333 ; [2] E cycles
loop psha ; [2] E cycles
pula ; [3] E cycles
psha ; [2] E cycles
pula ; [3] E cycles
nop ; [1] E cycle
nop ; [1] E cycle
dbne x,loop ; [3] E cycles
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Subroutine Dly1ms;**********************************************************************************
*
; Subroutine Dly1ms – 1ms delay loop.
; MCU : 68HC12, E=8MHz, no clock stretching, 16-bit bus
; Registers : Preserve index register x.
; Stack Reqs: 2 bytes stack space
Dly1ms pshx ; [2]
ldx #TC1MS ; [2]
d1mslp dex ; [1]
bne d1mslp ; [3/1]
pulx ; [3]
rts ; [5]
We need to find the value
of TC1MS!!
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Dly1ms
N = 14 + (4 * TC1MS) ; 14 cycles outside the loop
; 4 cycles inside the loop
For a delay of 1ms we need
N = TEX/TE = 1ms/125ns = 8,000 cycles
; Recall TE = 1/FE
This requires a loop count TC1MS of:
TC1MS = (N-14)/4 1,996.25 1,996
ENG3640 Fall 2012 17
Program Contents and Organization
The objective is to illustrate the program organization and give an example of a programmable delay and show you how I/O ports can be used within the CPU12.
1. Program Header2. Equates (port definitions e.t.c.)3. Constants4. Variables5. Main Program6. Subroutines
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Program Contents: Header
1.1. Program HeaderProgram Header (functional description of program, list program dependencies, revision date, name)
;****************************************************
;* A simple demonstration program
;* It generates 60 1-second, active low, pulses on PH0
;* MCU : 68HC12A4, E= 8MHz
;* Monitor: D-Bug12
;*
;* Date: 20/09/2012
;* Author: Shawki Areibi
;*****************************************************
ENG3640 Fall 2012 19
Program Contents: Equates1. Equates: should follow the program header. By using
equates you can use symbol names to make the code more readable.
;******************************************************************DDRH EQU $25 ; Port Definition
PORTH EQU $24
BIT0 EQU %00000001
TC1MS EQU 1996 ; Delay Count for 1ms
;******************************************************************
ENG3640 Fall 2012 20
Program Contents: Constansts & Variables
1. Stored constants: The stored constants are defined after all the program code.
2. Variables: Variables are places at the end of the program. One thing unique about variables is that they must be placed in RAM. During development the whole program is placed in RAM, so there is not another origin statement for the variables.
;*********************************************************************************
; Constants
;*********************************************************************************
InitCnt fcb 60 ; initial pulse count
;*********************************************************************************
; Variables
;*********************************************************************************
CurCnt rmb 1 ; LED flash counter
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Program Contents: Main Program1. Main Program: After equates there should be an origin
directive to define the starting location of the program code. The main program follows the ORG directive.
;****************************************************************** ORG $0800Main bset DDRH, BIT0 ; Initialize PORTH, BIT0 bset PORTH, BIT0 movb InitCnt, CurCnt ; Initialize pulse counter ; InitCnt defined in Constant Section ; CurCnt defined in Variable Section
;******************************************************************;* Main loop for output pulse generation;******************************************************************
ENG3640 Fall 2012 22
Cont … Main Program ORG $0800Main ; Initialization Section;******************************************************************;* Main loop for output pulse generation;******************************************************************Pulse bclr PORTH, BIT0 ; Turn pulse off ldd #250 ; Wait for 250ms jsr WaitDms ; WaitDms is a programmable delay bset PORTH, BIT0 ; Turn pulse on ldd #750 jsr WaitDms dec CurCnt ; Count pulses? bne pulse ; No: Another pulse swi ; Yes: Return to monitor
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Program Contents: Subroutines1. All subroutines and interrupt service routines, should follow the main
program. Subroutines themselves should never be contained within the main program code or another subroutine.
;***********************************************************************************
; Subroutine WaitDms – A programmable delay in ms.
; Arguments : The number of ms is passed in ACCD
; Registers : Preserve all registers except CCR.
; Stack Reqs: 6 bytes stack space
; Req. subs : Dly1ms
;************************************************************************************
WaitDms pshd ; preserve ACCD
msdlp jsr Dly1ms ; execute 1ms ACCD times
subd #1
bne msdlp
puld
rts
ENG3640 Fall 2012 24
Program Contents: Subroutines;***********************************************************************************
; Subroutine Dly1ms – 1ms delay loop.
; MCU : 68HC12, E=8MHz, no clock stretching, 16-bit bus
; Arguments : None
; Registers : Preserve all registers except CCR.
; Stack Reqs: 2 bytes stack space
; Req. subs : None
;************************************************************************************
Dly1ms pshx ; preserve IX
ldx #TC1MS ; execute loop TC1MS times
d1mslp dex
bne d1mslp
pulx
rts
ENG3640 Fall 2012 25
Program Organization;**********************************************; Program Header;**********************************************; Equates;**********************************************; Constants;**********************************************; Variables;**********************************************; Main Program;**********************************************; Subroutines;**********************************************
ENG3640 Fall 2012 26
D-Bug12 Utility Routines A stable operating environment is required to
develop microcontroller software. One of the simplest most economical development
environments consist of a monitor/debugger program that resides in ROM and executes in the target environment.
A ROM monitor provides1. Environment for controlled execution of software
2. Utility routines to aid in testing new algorithms.
ENG3640 Fall 2012 27
D-Bug12 Utility Routines The utility routines are presented as C
function definitions in the Motorola Application Note ``Using and Extending D-Bug12 Routines” because the D-Bug12 was written almost entirely in C.
The utility routines are usable when:1. Programming in C
2. Programming in Assembly Language!
ENG3640 Fall 2012 28
D-Bug12 Utility Routines (check Appendix C of Lab Manual of Web)
Function Description Vector Table
Address
main() Start of D-Bug12 $EE80
getchar() Get a character from SCI0 or SCI1 $EE84
putchar Send a character out SCI0 or SCI1 $EE86
getCmdLine() Obtain a line of input from the user $EE8A
sscanhex() Convert an ASCII hex string to binary integer $EE8E
isxdigit() Checks for membership in set[0..9,a..f,A..F] $EE92
toupper() Converts lower case characters to upper case $EE94
isalpha() Checks for membership in the set [a..z,A..Z] $EE96
out2hex() Displays 8-bit number as 2 ASCII hex characters $EE9C
writeEEByte() Write a data byte to on-chip EEPROM $EEA6
eraseEE() Bulk erase on-chip EEPROM $EEAA
ENG3640 Fall 2012 29
Assembly Source for isdigit( c )
;***********************************************************
; isdigit(c)
; Description: A routine to check if an ASCII char is a digit (0..9)
; Arguments: Char is passed in ACCB
; Return value is passed in ACCB and Z bit of CCR
;***********************************************************
Isdigit cmpb #’0’
blo isd_not
Isd_9 cmpb #’9’
bhi isd_not
ldab #1
bra isd_rtn
Isd_not clrb
Isd_rtn rts
ENG3640 Fall 2012 30
Assembly Language Interface
Calling a function from assembly language is simple.1. First push the parameters onto the stack in the proper order.2. Call the function with a JSR instruction.3. The JSR instruction uses a form of indexed indirect
addressing that treats the Program Counter as an index register.
4. Results are returned in the D Accumulator.
1. Char values returned in the D Accumulator are located in B
2. Boolean function results are zero for False and non-zero for True.
5. Called functions preserve only the content of the stack pointer. If other CPU12 register values must be preserved, they must be pushed onto the stack before any of the parameters and restored after deallocating the parameters.
ENG3640 Fall 2012 31
int getchar(void)
Function Description Vector Table
Address
Getchar() Get a character from SCI0 or SCI1 $EE84
The getchar() function retrieves a single character from the control terminal SCI
If a character is not available in the SCI Receive Data Register when the function is called, getchar() waits until one is received.
Because the character is returned as an int, the 8-bit character is placed in the B Acc.
ENG3640 Fall 2012 32
Int printf(char *format)
Function Description Vector Table
Address
Printf() Print arguments to output device (monitor screen) $EE88
The printf() function is used to convert, format, and print its arguments as standard output (the output device could be the monitor screen, printer, LCD, etc) under the control of the format string pointed to by format.
Formatted characters supported by the printf() function are
d,i signed decimal number c single character s string until a `\0’ (NULL)
33
Example: Utilizing getchar(), printf()
CR EQU $0D ; ASCII for Carriage Return
LF EQU $0A ; ASCII for Line Feed
getchar EQU $EE84 ; Address of getchar()
printf EQU $EE88 ; Address of printf()
ORG $1000 ; Start address of vars/constants
msg db “char pressed is %c”,CR,LF,0
ORG $1100 ; Start address of main program
getnewval LDX getchar ; load address of getchar subroutine
JSR 0,X ; get char from keyboard
CMPB #$1B ; check if the char is an ESC char
BEQ terminate ; jump to end of program
PSHD ; push char on stack for printf subroutine
LDD #msg ; second parameter in ACCD
LDX printf ; load address of printf subroutine
JSR 0,X ; print message on terminal
BRA getnewval ; repeat getting new chars
terminate SWI ; end of program
ENG3640 Fall 2012
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Instructions: Classificaions
Data handling (Data Transfer) Arithmetic (Addition, Subtraction, ..) Subroutines Logic Operations (AND, OR, ..) Bit Test and Manipulation Branches and Jumps Conditional Branches
ENG3640 Fall 2012 35
Data Handling: Register Loads
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
LDAA (M) ACCA X X X X X X
LDAB (M) ACCB X X X X X X
LDD (M:M+1) ACCD X X X X X X
LDS (M:M+1) SP X X X X X X
LDX (M:M+1) IX X X X X X X
LDY (M:M+1) IY X X X X X X
LEAS EA SP X
LEAX EA IX X
LEAY EA IY X
To transfer an immediate value or a value from memory to a register, a load instruction is used.
ENG3640 Fall 2012 36
Load Effective Address The last three instructions in previous table are
“load effective address instructions”. Load Effective Address Example leas 4, SP ; SP+4 SP leay d, y ; IY+ACCD IY
ENG3640 Fall 2012 37
Data Handling: Register Store
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
STAA ACCA (M) X X X X X
STAB ACCB (M) X X X X X
STD ACCD (M:M+1) X X X X X
STS SP (M:M+1) X X X X X
STX IX (M:M+1) X X X X X
STY IY (M:M+1) X X X X X
To transfer data from a register to memory, a store instruction is used.
38
Transfers and Exchanges
CPU12 Addressing Modes
Mnemonic Operation CPU11
INH IMM DIR EXT IDX [IDX]
TFR R1,R2 R1 R2 X
SEX R1,R2
Sign Extend
R1 R2
R1 = A, B, CCR
X
TAB ACCA ACCB X X
TAP ACCA CCR X X
TBA ACCB ACCA X X
TPA CCR ACCA X X
TSX SP IX X X
TSY SP IY X X
TXS IX SP X X
TYS IY SP X X
EXG R1,R2 R1 < R2 X
XGDX ACCD < IX X X
To move data between two registers, transfer and exchange instructions are used.
ENG3640 Fall 2012 39
Transfers and Exchanges The CPU12 added a general-purpose transfer and a general-
purpose exchange to replace the CPU11 register specific transfers and exchanges.
tfr a, b ; ACCA ACCB tab ; ACCA ACCB (Compatible CPU11) Note: the tab instruction affects the CCR, whereas the tfr has
no effect on the CCR! If a transfer occurs from a 16-bit register to an 8-bit register,
the Least Significant Byte of the source register is copied to the destination register.
If a transfer occurs from an 8-bit register to a 16-bit register, CPU12 automatically performs a sign extension into the most significant byte of the destination register.
ENG3640 Fall 2012 40
Move Instructions
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
MOVB (M1) (M2) X X X
MOVW (M1:M+1) (M2:M2+1) X X X
The memory-to-memory move instruction is another new instruction that significantly improves code efficiency in the CPU12.
It enables you to either move data from one memory location to another or move immediate data into a memory location without using CPU register.
ENG3640 Fall 2012 41
Move Instructions Examples
************************************************************** movb #$0F, PORTJ ; $0f PORTJ
ldaa #$0F ; CPU11 Equivalent staa PORTJ
*************************************************************** movw 0,x,0,y ; (IX:IX+1) (IY:IY+1)
ldd 0,x ; CPU11 Equivalent std 0,y
ENG3640 Fall 2012 42
The 68HC12 has shift and rotate instructions that apply to a memory location, accumulators A, B and D. A memory operand must be specified using the extended or index addressing modes.
Logical ShiftShift Left (Memory,A,B,D): LSL,LSLA,LSLB,LSLDShift Right (Memory,A,B,D): LSR,LSRA,LSRB,LSRD
Arithmetic Shift, Similar to a Logical shift, but the sign bit remains unchanged.Similar to a Logical shift, but the sign bit remains unchanged.
Shift Left (Memory,A,B,D): ASL,ASLA,ASLB,ASLDShift Right (Memory,A,B,D): ASR,ASRA,ASRB
Cyclic Shift (or Rotation)Left (Memory,A,B): ROL, ROLA,ROLBRight (Memory,A,B): ROR, RORA,RORB
Shift and Rotate Instructions
ENG3640 Fall 2012 43
Shift and Rotate Instructions
A common application for the shift and
rotate?
multiplication and division. Shifts can be
used to multiply or divide by
constant powers of 2.
ENG3640 Fall 2012 44
Boolean Logic, Bit Manipulation
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
ANDA ACCA.(M) ACCA X X X X X X
ANDB ACCB.(M) ACCB X X X X X X
ANDCC CCR.(M) CCR
EORA ACCA XOR (M) ACCA X X X X X X
EORB ACCB XOR (M) ACCB X X X X X X
ORAA ACCA + (M) ACCA X X X X X X
ORAB ACCA + (M) ACCB X X X X X X
ORCC CCR + (M) CCR X
COMA (B) ACCA’ ACCA X X
COM (M)’ (M) X X X X
Boolean logic functions are important for bit manipulation such as setting, clearing or inverting individual bits in a word.
ENG3640 Fall 2012 45
Bit Manipulation “Clearing Bits”
1. Clearing Bits: use the AND Instruction
X.1 = X X.0 = 0
A7A6A5A4 A3A2A1A0
. 0 0 0 0 1 1 1 1
--------------------------
0 0 0 0 A3A2A1A0
ENG3640 Fall 2012 46
Bit Manipulation “Setting Bits”
1. Setting Bits: use the OR Instruction
X + 1 = 1 X + 0 = X
A7A6A5A4 A3A2A1A0
+ 0 0 0 0 1 1 1 1
--------------------------
A7A6A5A4 1 1 1 1
ENG3640 Fall 2012 47
Bit Manipulation “Inverting Bits”
1. Inverting Bits: use the XOR Instruction
X (XOR) 1 = X’ X (XOR) 0 = X
A7A6A5A4 A3A2A1A0
XOR 0 0 0 0 0 0 0 1
--------------------------
A7A6A5A4 A3A2A1A0’
ENG3640 Fall 2012 48
CCR Flag Manipulation
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
CLC 0 C X X
CLI 0 I X X
CLV 0 V X X
SEC 1 C X X
SEI 1 I X X
SEV 1 V X X
There are individual instructions for setting and clearing CCR flags
49
Stack
top element
bottom element
low address
high address
Stack pointer
Figure 4.1 Diagram of the 68HC12 stack
The Stack
Conceptually, a stack is a list of data items whose elements can be accessed from only one end.
A stack element has a top and a bottom. The operation that adds a new item to the top is called
push. The top element can be removed by performing an
operation called pop or pull.
The Stack Pointer (SP) points to the top element or to the memory location above the top element.
ENG3640 Fall 2012 50
Using the STACK
Mnemonic Operation Equivalent Operation
PSHA SP - 1 SP, ACCA (SP) staa 1, -SP
PSHB SP - 1 SP, ACCB (SP) stab 1, -SP
PSHC SP - 1 SP, CCR (SP) none
PSHD SP - 2 SP, ACCD (SP:SP+1) std 2, -SP
PSHX SP – 2 SP, IX (SP:SP+1) stx 2, -SP
PSHY SP – 2 SP, IY (S):SP+1) sty 2, -SP
PULA (SP) ACCA, SP + 1 SP Ldaa 1,SP+
PULB (SP) ACCB, SP + 1 SP Ldab 1,SP+
PULC (SP) CCR, SP + 1 SP none
PULD (SP:SP + 1) ACCD, SP + 2 SP Ldd 2, SP+
PULX (SP:SP + 1) IX, SP + 2 SP Ldx 2, SP+
PULY (SP:SP + 1) IY, SP + 2 SP Ldy 2,SP+
The stack is LIFO data structure. It is an ideal data structure for temporarily storing data from nested routines
ENG3640 Fall 2012 51
Stack Instructions
The CPU12 stack is used by the user program and automatically by the CPU for subroutine calls and interrupts.
The stack is used to Store the return address of subroutines. Communicate variables to the calling subroutine To return values from a subroutine. To save the values of registers when an external/internal interrupt
occurs
ENG3640 Fall 2012 52
Stack Usage Rules
Initialize the stack pointer: Typically the stack pointer is initialized to the last byte of user RAM. This is because the stack grows into lower addresses.
Balance the stack: Always make sure there are as many bytes pulled off the stack as there are bytes pushed onto the stack!Do Not Use Data Above the Stack Pointer: Data will be overwritten and destroyed!
Do Not Use the Stack haphazardly for temporary storage: A common bug is caused by pushing data onto the stack, and then missing the pull because of a conditional branch (i.e., unbalanced stack).
ENG3640 Fall 2012 53
Subroutines An assembly language program is made up of
a main program and subroutines. If the system is interrupt driven, there will be
interrupt service routines (ISR). Hierarchy:
Designing a program hierarchically creates a more reliable and reusable program.
In order to design hierarchically, you must use structured programming constructs and carefully designed routines.
ENG3640 Fall 2012 54
Subroutines
The CPU12 has several instructions to implement subroutines.
Traditional subroutine instructions used for 64K-byte systems are BSR, JSR, RTS
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
BSR SP – 2 SP X
PC (SP:SP+1)
PC + rel PC
JSR SP – 2 SP X X X X X
PC (SP:SP+1)
AD PC
RTS (SP:SP+1) PC X X
SP + 2 SP
55
Subroutines (CALL, RTC) The CPU12 has new instructions to implement subroutines. The new instructions are used for subroutines that may fall on
different memory pages (Expanded Memory). Writing assembly programs to be run in expanded memory
requires an assembler that supports this feature!.
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
CALL SP – 2 SP X X X
PC (SP:SP+1)
SP – 1 SP
PPAGE (SP)
Page PPAGE
AD PC
RTC (SP) PPAGE X
SP + 1 SP
(SP:SP+1) PC
SP + 2 SPENG3640 Fall 2012
ENG3640 Fall 2012 56
Subroutine Program Flow
Bsr func
Bsr func
func
rts
The rts instruction returns program flow to the instruction following the last subroutine call!
jsr/bsr saves the PC on the stack before going to func.
ENG3640 Fall 2012 57
Passing Parameters When passing parameters between two routines,
we can pass the data, or reference to the data.1. The simplest and most efficient method for passing
parameters is to use a register. The calling routine simply places the parameter in a register before jumping to the subroutine. However we are limited by number of registers.
2. The most versatile method to pass parameters is to use the stack. As long as there is enough stack space, any number of parameters can be passed.
58
Issues in Subroutine Calls
1. Parameter passing - Use registers (few parameters)- Use the stack- Use global memory
2. Returning results- Use registers (few results)- Use the stack (caller creates a hole in which the result will be placed)- Use global memory
3. Local variable allocation- Allocated by the callee- The following instruction is the most efficient method of local variable
allocation.
leas -n,sp ; allocate n bytes in the stack for local variables
4. Local variable deallocation- performed by the subroutine- The following instruction is the most efficient method of local variable deallocation.
leas n,sp ; deallocate n bytes from the stack
ENG3640 Fall 2012 59
Stack Usage Conventions
60
Stack Frame- The region in the stack that holds incoming parameters, the subroutine return
address, local variables, and saved registers is referred to as stack frame. - The stack frame is also called activation record.
Local variables
Saved registers
Return address
Incoming parameters
SP
Figure 4.9 Structure of the 68HC12 stack frameENG3640 Fall 2012
ENG3640 Fall 2012 61
Example 4.10 Draw the stack frame for the following program segment after the leas –10,sp instruction is executed:
ldd #$1234pshdldx #$4000pshxjsr sub_xyz…
sub_xyz pshdpshxpshyleas -10,sp…
Solution:The stack frame is shown inFigure 4.10.
$1234
$4000
return address
$1234
$4000
contents of y
10 bytes for localvariables
SP
Figure 4.10 Stack frame of example 4.10
ENG3640 Fall 2012 62
Subroutine Implementation
C Function ExampleFor (j = 0; j<10; ){ j = FuncA(j);}
C Assembly Code ldaa #0 ; initialize jLoop: cmpa #10 ; Compare j to 10 bge EndLoop ; Else (j < 10) psha ; Push Parameter J onto Stack des ; Allocate space for return value bsr FuncA ; Call FuncA pula ; Pull return value from Stack ins ; Deallocate space from Stack bra Loop ; Repeat loop EndLoop:
FuncA: ldaa 3,sp ; load parameter from stack adda #2 ; Add 2 to A staa 2, sp ; Store return value to stack rts ; Return from FuncA
Byte FuncA(byte a){ return a + 2;}
…..
$3FF9
$3FFA
$3FFB
$3FFC
$3FFD
$3FFE
$3FFF
$4000
SP:
RetVal:
Param:
Initial SP:
ENG3640 Fall 2012 63
Subroutine ImplementationAddr Opcodes Label Instruction Description
0000 main …0010 0720 bsr sub1 ;SP–2 -> SP, PC => (SP:SP+1), PC+rel->PCX012 ….
X030 20ce bra main ; PC + rel = main -> PC
X032 sub1 ….X040 160051 jsr sub2 ;SP – 2 -> SP, PC ->(SP:SP+1), sub2 -> PCX043 ….X050 3d rts ;(SP:SP+1) -> PC, SP+2 -> SP
X051 sub2 ….X060 3d rts ;(SP:SP+1) -> PC, SP+2 -> SP
ENG3640 Fall 2012 64
Basic Subroutine Techniques Never branch out of or into a subroutine: this can cause a
disastrous bug! A subroutine should always have a single entry point and a single exit.
Preserve Registers: we have two choices, either preserve the registers in the calling routine, or preserve the registers in the subroutine.
Subroutine Documentation: One of the advantages of using subroutines is for reuse and portability. If the routine is well documented it can be reused easily i.e. Subroutine name and function, MCU and monitor dependencies, Stack requirements …..
ENG3640 Fall 2012 65
Addition Instructions
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
ABA ACCA+ACCB ACCA X X
ABX ACCB+IX IX X X
ABY ACCB+IY IY X X
ADCA (M)+ACCA+C ACCA X X X X X X
ADCB (M)+ACCB+C ACCB X X X X X X
ADDA (M)+ACCA ACCA X X X X X X
ADDB (M)+ACCB ACCB X X X X X X
ADDD (M:M+1)+ACCD ACCD X X X X X X
DAA Decimal Adjust ACCA X X
Addition instructions can be either 8-bit additions or 16-bit additions.
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8-Bit Binary Addition Example ldaa #$3a ; $3a ACCA adda #$7c ; ACCA + $7c ACCA The CPU operation 1111 H N Z V C $3A 0011 1010 1 1 0 1 0 + $7C + 0111 1100 $B6 1011 0110NOTE: The CPU does not know if the
arguments are signed, unsigned or BCD!!
Flags?
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Affected Flags? The flags are set according to the Boolean formulas
in the adda instruction description. The half-carry flag, H, indicates a carry out of bit 3. The negative flag, N, indicates a negative result, i.e.
a result is negative if bit 7 of result is set. The zero flag, Z, is not set since result is not zero! The overflow flag, V, is set since the addition
resulted in a two’s complement overflow (How can we easily tell?) If two arguments have the same sign and the result has the opposite sign, then the V flag is set.
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Unsigned Interpretation
If the arguments are both unsigned numbers, the addition can be interpreted as follows:
$3A 58 $7C 124 ------ ------ $B6 182 8-bit unsigned numbers can range from 0 to 255. If
the result exceeds 255, then the C flag will be set, and the 8-bit result will be incorrect!
So if you are using unsigned numbers and the C flag were set we would branch to an error routine or use C flag to calculate a 16-bit result.
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Signed Interpretation
If the arguments are both signed numbers, the addition can be interpreted as follows:
$3A +58
$7C +124
------ ------
$B6 (-74) 8-bit signed numbers can range from -128 to +127.
If the result exceeds the range, the overflow flag, V, will be set.
So if you are using signed numbers and the V flag were set, we know that the result is incorrect.
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Subtraction Instructions
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
SBA ACCA-ACCB ACCA X X
SBCA ACCB-(M)-C ACCA X X X X X X
SBCB ACCB-(M)-C ACCB X X X X X X
SUBA ACCA-(M) ACCA X X X X X X
SUBB ACCB-(M) ACCB X X X X X X
SUBD ACCD-(M:M+1) ACCD X X X X X X
NEG 0 - (M) (M) X X X
NEGA 0 - ACCA ACCA X X
NEGB 0 - ACCB ACCB X X
Subtraction instructions can be either 8-bit/16-bit subtractions or negate instructions
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Multiplication
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
EMUL 16 x 16 Multiply, Unsigned
X
EMULS 16 x 16 Multiply, Signed
X
MUL 8 x 8 Multiply, Unsigned
X X
The CPU12 multiplication instructions represent a significant improvement over the CPU11.The CPU11 mul executes in 10 cycles whereas the CPU12 mul takes only 3 cycles.
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Multiplication: MUL unsigned
8-bit unsigned 8-bit unsignedA B
X
16-bit unsigned
D
The mul instruction can be used for integers or mixed numbers.
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Unsigned Multiply Instructions
Example:
Mult ldaa #$20 ;$20 ACCA
ldab #$35 ;$35 ACCB
mul ; $20 x $35 = 06A0 ACCD
Interpretation (8-bit integers)
$20 32
x $35 x 53
------------- -------------
$06A0 1696
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Division
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
EDIV 32 by 16 Divide, Unsigned
X
EDIVS 32 by 16 Divide, Signed
X
FDIV 16 by 16 Fractional
Divide, unsigned
X X
IDIV 16 by 16 integer
Divide, unsigned
X X
IDIVS 16 by 16 integer, Divide, signed.
X
The CPU12 division instructions represent a significant improvement over the CPU11.The CPU11CPU11 idiv and fdiv execute in 41 cycles whereas the CPU12 version take only 12 cycles.
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Unsigned Integer Division: IDIV
16-bit unsigned 16-bit unsignedD X
/
16-bit unsigned
X
dividend divisor
quotient 16-bit unsigned remainder
D
Condition codesZ: set if result is $0000; cleared otherwiseV: 0, clearedC: set if denominator was $0000; cleared otherwise
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Compares and Tests
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
CBA ACCA-ACCB X X
CMPA ACCA-(M) X X X X X X
CPD ACCD-(M:M+1) X X X X X X
CPS SP – (M:M+1) X X X X X
CPX IX – (M:M+1) X X X X X X
CPY IY – (M:M+1) X X X X X X
TST (M) - 0 X X X X
TSTA ACCA - 0 X X
TSTB ACCB - 0 X X
Compare instructions are used to compare two arguments and set the appropriate flags for a conditional branch instruction.
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Cont .. Compare and Test
Remarks:
1. Operations performed are similar to subtraction instructions except that the result is not saved!
2. The CBA instruction compares content of ACC A and ACC B and sets Z if result is $00, sets N if MSB of result is `1’, sets V if two’s complement overflow resulted, and sets C if there was a borrow.
3. The test instructions are simply compare to zero.
They are useful only for signed branches.
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Bit Test and Manipulation
CPU12 Addressing Modes
Mnemonic Operation CPU11 INH IMM DIR EXT IDX [IDX]
BITA ACCA . (M) X X
BITB ACCB . (M) X X
BCLR (M). Msk’ (M) X X X X
BSET (M) | msk (M) X X X X
bclr and bset are used to set or clear bits in a word in memory.
bita and bitb are bit testing instructions.
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Example: Bit Manipulation
************************************************************
* Clear MSB, LSB of memory location pointed to by
Index register x ($81 = %1000 0001)
bclr 0,x,$81
************************************************************* Set MSB of memory location pointed to by Index register y ($80 = %1000 0000) bset 0,y,$80
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Branch Instructions
S X I
7 6 5 4 3 2 1 0
H N Z V C
Four types of branch instructions:
- Unary (unconditional) branch: always execute (e.g BRA)
- Simple branches: branch is taken when a specific bit of CCR is in a specificstatus
- Unsigned branches: branches are taken when a comparison or test of unsignednumbers results in a specific combination of CCR bits
- Signed branches: branches are taken when a comparison or test of signedquantities results in a specific combination of CCR bits
Two categories of Branches
- Short Branches: in the range of -128 ~ +127 bytes (8-bit offset is added)
- Long Branches: in the range of 64KB (16-bit offset is added)
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Jump Instruction
Label Instruction*********************************************************START CBA
BEQ SKIP JMP NOT_EQUAL
SKIP INCANOT_EQUAL END
The program counter will be loaded by the address NOT_EQUAL
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Conditional Branches
1. The branch and jump instructions always perform the jump or branch when they are executed (unconditional!)
2. Conditional branch instructions branch only if certain conditions are satisfied.
3. The conditions are always based on the contents of the condition code register.
4. Conditional branches are used to implement conditional and loop constructs.
5. The CPU11 and CPU12 have different conditional branches (simple, conditional branches for signed numbers and unsigned numbers)
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Table 2.2 Summary of short branch instructions
Mnemonic Function
Unary Branches
BRABRN
Branch alwaysBranch never
Equation or Operation
Simple Branches
Mnemonic Function
BCCBCSBEQBMIBNEBPLBVCBVS
Branch if carry clearBranch if carry setBranch if equalBranch if minusBranch if not equalBranch if plusBranch if overflow clearBranch if overflow set
1 = 11 = 0
Unsigned Branches
Mnemonic Function
BHIBHSBLOBLS
Branch if higherBranch if higher or sameBranch if lowerBranch if lower or same
C = 0C = 1Z = 1N = 1Z = 0N = 0V = 0V = 1
Equation or Operation
Equation or Operation
C + Z = 0C = 0C = 1
C + Z = 1
Mnemonic Function Equation or Operation
Signed Branches
BGEBGTBLEBLT
Branch if greater than or equalBranch if greater thanBranch if less than or equalBranch if less than
N V = 0Z + (N V) = 0Z + (N V) = 1
N V = 1
When a short-branch instruction is executed, a signed 8-bit offset is added to the value in the program counter when a specified condition is met.
The numeric range of the short branch offset value is $80 (-128) to $7F (+127) from the address of the instruction immediately following the branch instruction.
Short Branch Instructions
84
Assembly Programming – Programming Concepts
if(a>=20){ // if body}
If-Then C Code:
If-Then Assembly Code: cmpa, #20 ; If Cond. (A>=20) blo EndIf ; Branch !(A>=20)=>(A<20)
; If BodyEndIf:
If Cond.
!(A>=20) If Body
A>=20
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Assembly Programming – Programming Concepts
if(a>=20) { // if body}else { // else body}
If-Then-Else C Code:
If-Then-Else Assembly Code: cmpa, #20 ; If-Else Cond. (A>=20) blo Else ; Branch !(A>=20)=>(A<20)
; If Body bra EndIf ; Branch EndIfElse: ; Else Body ;EndIf:
If–ElseCond.
A>=20
Else Body
!(A>=20)
If Body
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Assembly Programming – Programming Concepts
for(J=0; J<10; J++){ // loop body}
For Loop C Code: J=0
Loop Cond.
!(J<10)
Loop Body
J++
J<10
For Loop Assembly Code: ldaa #0 ; Loop Init. (J=0)Loop: cmpa #10 ; Loop Cond. (J<10) bge EndLoop ; Branch !(J<10)=>(J>=10)
; Loop Body adda #1 ; Loop Iter. (J++) bra Loop ; Repeat LoopEndLoop:
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Assembly Programming – Programming Concepts
while(i!=0){ // loop body}
While Loop C Code:
Loop Cond.
!(i!=0)
Loop Body
i!=0
While Loop Assembly Code:
Loop: cmpa, #0 ; Loop Cond. (i!=0) beq EndLoop ; Branch !(i!=0)=>(i==0)
; Loop Body bra Loop ; Repeat LoopEndLoop:
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Table 2.3 Summary of long branch instructions
Mnemonic Function
Unary Branches
LBRALBRN
Long branch alwaysLong branch never
Equation or Operation
Simple Branches
Mnemonic Function
LBCCLBCSLBEQLBMILBNELBPLLBVCLBVS
Long branch if carry clearLong branch if carry setLong branch if equalLong branch if minusLong branch if not equalLong branch if plusLong branch if overflow is clearLong branch if overflow set
1 = 11 = 0
Unsigned Branches
Mnemonic Function
LBHILBHSLBLOLBLS
Long branch if higherLong branch if higher or sameLong branch if lowerLong branch if lower or same
C = 0C = 1Z = 1N = 1Z = 0N = 0V = 0V = 1
Equation or Operation
Equation or Operation
C + Z = 0C = 0C = 1
C + Z = 1
Mnemonic Function Equation or Operation
Signed Branches
LBGELBGTLBLELBLT
Long branch if greater than or equalLong branch if greater thanLong branch if less than or equalLong branch if less than
N V = 0Z + (N V) = 0Z + (N V) = 1
N V = 1
For every short branch instruction, a corresponding long branch instruction exists.
When a long-branch instruction is executed, a signed 16-bit offset is added to the value of the program counter when a specific condition is met.
Long Branch Instructions
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Simple Conditional Branches
Branch Complementary Branch
Test Mnemonic Condition TEST Mnemonic Condition
R = M BEQ Z = 1 R =/ M BNE Z = 0
Carry BCS C = 1 No Carry BCC C = 0
Positive BPL N = 0 Negative BMI N = 1
Overflow BVS V = 1 No Overflow BVC V = 0
Always BRA --- Never BRN ---
Are all based on the value of a single CCR flag. Branch never, brn on the CPU11 can be used as a three cycle no-
op instruction. However on the CPU12 it takes only a single cycle so it has no advantage over the nop instruction.
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Bit Conditional Branches
CPU12 Addressing Modes
Mnemonic Condition CPU11 INH IMM DIR EXT IDX [IDX]
BRCLR (M).msk = 0 X X X X
BRSET (M)’.msk = 0 X X X X
BRCLR and BRSET are branch instructions that are conditional on individual bits or a bit field within a word.
Syntax is brclr M, msk, AD
brset M, msk, AD
Where: M = memory location containing bits to be tested, msk = the bit mask, AD = destination address
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Example
************************************************************* Branch to bar if bits 7 and 3 of out_reg are clear brclr out_reg,%10001000,bar
Note: The operation of these two instructions is the same as the code using logic instructions.
************************************************************* Branch to bar if bits 7 and 3 of out_reg are set ldx #out_reg brset 0,x,%10001000,bar
Cont … CONDITIONAL BRANCH INSTRUCTIONS
DECREMENT & BRANCH DBEQ COUNTER - $01 COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL PC
DBNE COUNTER - $01, COUNTER IF COUNTER <>0, THEN (PC)+$0003 +REL PC
INCREMENT & BRANCH IBEQ COUNTER + $01 COUNTER IF COUNTER =0, THEN (PC)+$0003 +REL PC
IBNE COUNTER + $01 COUNTER IF COUNTER <>0, THEN (PC)+$0003 +REL PC
TBEQ IF COUNTER = 0, THEN PC+$0003 + REL PC TBNE IF COUNTER <>0, THEN PC+$0003 + REL PC
FUNCTION MNEMONIC OPERATION
TEST & BRANCH
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Example:
************************ ldx #20loop: nop psha pula dbne x,loop
************************ ldx #FAloop: nop psha pula ibne x,loop
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Flow Diagrams Flow diagrams are a widely used tool for
graphically designing and documenting programs.
They provide a good way to visualize the program structure.
They are simple and widely used. The main problem with flow diagrams is that
they can be time consuming to create.
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Process Blocks A process block represents a structured block
of code. To be structured, it always has a single entrance and a single exit
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Decision Blocks
Decision blocks are used to conditionally execute processes.
They represent a high-level language if and an assembly language conditional branch instruction.
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Connectors
There are two types of connectors used: 1. Start and termination connectors (represent entrance and
exit of a flow diagram).
2. Continuation connectors (used if a flow diagram is complex and spans more than a single page).
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Sequence Construct
The first and most obvious construct is a simple sequence of processes.
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If Construct The if construct is used to conditionally execute a
process. The if construct translates to a decision block in the flow diagram and a conditional branch in assembly code.
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If-Else Construct The if-else construct is used to conditionally execute
one of two mutually exclusive processes.
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If-Else-If-Else Construct The if-else-if-else construct is used to conditionally
execute one of several mutually exclusive processes.
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The Case Construct The case construct is essentially the same as the if-
else-if-else construct.
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The Do-While Loop The do-while loop runs a process, and if a condition
is true, it repeats the process.
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The While Loop The while loop tests a condition, and if the condition
is true, it repeats one or more processes.
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The For Loop The for loop is a while loop with loop parameters and
operations defined in an argument list.
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I/O Data Conversions
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I/O Data Conversions
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CPU11 versus CPU12 The CPU12 executes programs much faster than
the CPU11 for several reasons:
1. CPU12 has a 16-bit data bus, so it can fetch opcodes and arguments with fewer bus cycles.
2. CPU12 can run at a higher bus frequency than the CPU11.
3. It has added circuitry for complex instructions such as multiplies and divides.
4. The CPU12 also has an instruction queue that allows it to fetch the next instruction while it is executing the current instruction!
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I/O Data Conversions
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I/O Data Conversions
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I/O Data Conversions
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I/O Data Conversions
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ExampleThe WriteEEByte() function is called as follows:
WriteEEByte: EQU $FE1C
;
;
ldab #$55 ; write $55 to EEPROM
pshd ; place the data on the stack
ldd EEAddress ; EEaddress to write data
jsr [WriteEEByte, pcr] ; call the routine
pulx ; remove the parameter from stack
;********************************************************************************
Could also use
ldx WriteEEByte ; load the address of WriteEEByte()
jsr 0,x ; call the routine
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