epc2022 – enhancement mode power...
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eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 | | 1
EPC2022
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.
EPC2022 eGaN® FETs are supplied only inpassivated die form with solder bumps. Die Size: 6.05 mm x 2.3 mm
• High Speed DC-DC Conversion• Motor Drive• Industrial Automation • Synchronous Rectification • Inrush Protection • Class-D Audio
EFFICIENT POWER CONVERSION
Maximum Ratings
VDSDrain-to-Source Voltage (Continuous) 100
V
IDContinuous (TA = 25˚C, RθJA = 2.5˚C/W) 90
APulsed (25˚C, TPULSE = 300 µs) 390
VGSGate-to-Source Voltage 6
VGate-to-Source Voltage -4
120
TJ Operating Temperature -40 to 150˚C
TSTG Storage Temperature -40 to 150
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150˚C)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics (TJ= 25˚C unless otherwise stated)
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.9 mA 100 V
IDSS Drain Source Leakage VDS = 80 V, VGS = 0 V 0.1 0.7 mA
mAIGSS
Gate-to-Source Forward Leakage VGS = 5 V 1 9 mA
Gate-to-Source Reverse Leakage VGS = -4 V 0.1 0.7
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 13 mA 0.8 1.4 2.5 V
RDS(on) Drain-to-Source On Resistance VGS = 5 V, ID = 25 A 2.4 3.2 mΩ
VSD Source-to-Drain Forward Voltage VIS = 0.5 A, VGS = 0 V 1.8
Thermal Characteristics
RθJC Thermal Resistance, Junction to Case 0.4 ˚C/W
RθJB Thermal Resistance, Junction to Board 1.1 ˚C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1) 42 ˚C/W
TYP UNIT
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate shorted to source.
HAL
www.epc-co.com/epc/Products/eGaNFETs/EPC2022.aspx
EPC2022 – Enhancement Mode Power Transistor
VDSS , 100 V RDS(on) , 3.2 m ID , 90 A
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 | | 2
EPC2022
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
CISS Input Capacitance
pFCOSS Output Capacitance
RG Gate Resistance Ω
COSS(ER)E�ective Output Capacitance,
Enegy Related (Note 2)
COSS(TR)E�ective Output Capacitance,
Time Related (Note 3)
nCQGD Gate-to-Drain Charge
QG(TH) Gate Charge at Threshold
Source-to-Drain Recovery Charge
QGS Gate-to-Source Charge
QOSS Output Charge
QRR
QG Total Gate Charge 16
1680
1260
107
Note 2: COSS(ER) is a �xed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 50% BVDSS.Note 3: COSS(TR) is a �xed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 50% BVDSS.
VDS = 50
VDS = 0 to 50 V, VGS = 0 V
V, VGS = 0 V
VDS = 50 V, VGS = 5 V, ID= 25 A
VDS = 50 V, ID = 25 A
VDS = 50 V, V = 0 VGS
CRSS Reverse Transfer Capacitance
1400
7
840
1090
1410
0.3
13
3.4
2.4
2.1
71
0
300
200
100
00 0.5 1.0 1.5 2.0 2.5 3.0
I D –
Dra
in Cu
rrent
(A)
Figure 1: Typical Output Characteristics at 25°C
VDS – Drain-to-Source Voltage (V)
VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V
I D –
Dra
in Cu
rrent
(A)
VGS – Gate-to-Source Voltage (V) 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
300
200
100
0
25˚C125˚C
VDS = 3 V
25˚C125˚C
VDS = 3 V
8
6
4
2
02.5 3.0 3.5 4.0 4.5 5.0
R DS(o
n) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ)
VGS – Gate-to-Source Voltage (V)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 25 AID = 50 AID = 100 AID = 150 A
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
R DS(
on) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ
)
VGS – Gate-to-Source Voltage (V)
25˚C125˚C
VDS = 3 V
25˚C125˚C
ID = 25 A
8
6
4
2
0
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 | | 3
EPC2022
All measurements were done with substrate shortened to source.
Capa
citan
ce (p
F)
0 20 40 60 10080
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
2500
2000
1500
1000
500
0
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capa
citan
ce (p
F)
1000
100
10
00 20 40 60 10080
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure 6: Gate Charge
V GS
– Ga
te-to
-Sou
rce V
olta
ge (V
)
5
4
3
2
1
00 1510 5
QG – Gate Charge (nC)
ID = 25 AVDS = 50 V
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
I SD –
Sour
ce-to
-Dra
in Cu
rrent
(A)
VSD – Source-to-Drain Voltage (V)
Figure 7: Reverse Drain-Source Characteristics
300
200
100
0
25˚C125˚C
VGS = 0 V
Figure 8: Normalized On-State Resistance vs. Temperature
Norm
alize
d On
-Sta
te R
esist
ance
RDS
(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.80 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 25 AVGS = 5 V
Figure 9: Normalized Threshold Voltage vs. Temperature
Norm
alize
d Th
resh
old
Volta
ge
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.600 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 13 mA
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 | | 4
EPC2022
Figure 12: Transient Thermal Response Curves
I G –
Gate
Curre
nt (m
A)
VGS – Gate-to-Source Voltage (V)
Figure 10: Gate Leakage Current60
50
40
30
20
10
00 1 2 3 4 5 6
25˚C125˚C
0.1
1
10
100
1000
0.1 1 10 100
I D – D
rain
Curre
nt (A
)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
Pulse Width 100 ms
10 ms 1 ms
100 µs
Figure 11: Safe Operating Area
tp, Rectangular Pulse Duration, seconds
Z θJB
, Nor
mal
ized T
herm
al Im
peda
nce
0.5
0.050.02
Single Pulse
0.01
0.1
Duty Cycle:
Junction-to-Board
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 10+1
1
0.1
0.01
0.001
0.0001
0.5
0.050.02
Single Pulse
0.01
0.1
Duty Cycle:
0.2
tp, Rectangular Pulse Duration, seconds
Z θJC
, Nor
mal
ized T
herm
al Im
peda
nce
0.5
Junction-to-Case
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
TJ = Max Rated, TC = +25°C, Single Pulse
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 | | 5
EPC2022
2022
YYYY
ZZZZ Die orientation dot
Gate Pad bump is under this corner
Part Number
Laser Marking
Part #Marking Line 1
Lot_Date CodeMarking Line 2
Lot_Date CodeMarking Line 3
EPC2022 2022 YYYY ZZZZ
DIE MARKINGS
TAPE AND REEL CONFIGURATION4mm pitch, 12mm wide tape on 7” reel
7” reel
a
d e f g
c
b
Note 1: MSL 1 (moisture sensitivity level 1) classi�ed according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.
Dieorientation
dot
Gatesolder bar is
under thiscorner
Die is placed into pocketsolder bar side down
(face side down)
Loaded Tape Feed Direction
2022
YYYY
ZZZZ
EPC2022 (note 1) Dimension (mm) target min max
a 12.00 11.70 12.30b 1.75 1.65 1.85
c (see note) 5.50 5.45 5.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10
f (see note) 2.00 1.95 2.05 g 1.50 1.50 1.60
Side View
DIE OUTLINESolder Bump View
(685
)
SEATING PLANE
(785
)
100 ±
20
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
A
f
d X30
B
gX4e
c
X30
X28
Pad 1 is Gate
Pads 2,5,6,9,10,13,14,17,18,21,22,
25,26,29 are Source
Pads 3,4,7,8,11,12,15,16,19,20,23,
24,27,28 are Drain
Pad 30 is Substrate
DIM
Micrometers
MIN Nominal MAX
A 6020 6050 6080B 2270 2300 2330c 2047 2050 2053d 717 720 723e 210 225 240f 195 200 205g 400 400 400
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2016 | | 6
EPC2022
Information subject to change without notice.
Revised July, 2016
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012
RECOMMENDEDLAND PATTERN (units in µm)
RECOMMENDEDSTENCIL DRAWING (units in µm)
Land pattern is solder mask definedSolder mask opening is 180 µmIt is recommended to have on-Cu trace PCB vias
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
6050
180
700
X30
2300
400
2030
X30
X28
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.
Additional assembly resources available at http://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx
6050
400X34
2300
1330
2050
720
200X35
R 60
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