explicit gate delay model for timing evaluation

Explicit Gate Delay Model for Timing Evaluation

Muzhou Shao : University of Texas at AustinD.F.Wong : U. of Illinois at Urbana- ChampaignHuijing Cao : Motorola, Inc.Youxin Gao : Synopsys, Inc., Li-Pen Yuan : Synopsys, Inc., Li-Da Huang : University of Texas at AustinSeokjin Lee : University of Texas at Austin

• One part of stage delay

• Crucial in timing synthesis/optimization

Value of Gate Modeling

• Switch-resistor model

• k-factor functions

• Lookup table model

Previous Gate Delay Model

Previous Gate Delay Model – cont.

• k-factor functions Delay/transition are functions of input signal

and gate load.

• Lookup table model Delay/transition is tabulated for each input,

load pair.

Previous Gate Delay Model – cont.

• Switch-resistor model Structure:

• step voltage source• linear driver resistance

Advantages:• Simple• Stage delay

Trends in DSM

• The increasing of resistive shielding of interconnect.

• The output impedance of gate reduces relatively.

Trends in DSM – cont.

• Step input --> piecewise

• C_eff is needed in gate modeling.

Our New Approach

• Gate modeling work independent of its load.

• Can be easily integrated into timing analysis.

• Concise circuit structure.

Based on a second-order circuit.

Structure of Explicit Gate Model

Parameters of Gate Model

• Totally 5 unknown parameters 4 unknown parameters in the model circuit.

• R1 , R2, C1, C2

1 unknown parameters in the input signal.•

• With two operating points, two poles are obtained.

Parameters of Gate Model – cont.

• Another two operating points, another two poles.

Parameters of Gate Model – cont.

Parameters of Gate Model – cont.

Obtain Operating Points

There are four operating points of the gate output needed in the deduction.

- Run SPICE twice to obtain the two groups of (vi, ti).

- Obtained from k-factor functions

• The gate intrinsic delay and signal regenerating ability.

is defined as tp tr .

Another Parameter

Another Parameter – cont.

• Choose an operating point of 50% power supply as (50%VDD, t50%).

Another Parameter – cont.

Two Ways to Set up the Model

• Solving nonlinear equations.

• “optimize” function of transit analysis in HSPICE.

Focus of the Experimental Results

• Can be pre-computed.

• The saving of runtime is obvious.

• The accuracy issue is focused on.

• 36 gates of different types and technologies.• The gate load is randomly generated.• The input signal is also randomly chosen.• 3,600 experimental results all together.• MOS transistor model level is from 13 to 49.

Experimental Results

• Statistic results of computation errors in gate delay model.

Experimental Results– cont.

Waveforms obtained from HSPICE simulations

Waveform Comparisons (Driving Pin)

Waveforms obtained at the fan-out point.

Waveform Comparisons (Sink Pin)

• The test results on the clock tree of a commercial IC .

Another Test Case

Conclusion

• Independent of gate load.• Can be pre-characterized.• No effective capacitance iteration.• Compatible with interconnect timing analysis.