fe-i4 digital test bench

FE-I4 Digital Test Bench

Tomasz Hemperek

Introduction

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SystemVerilog OVM Methodology Can to use rtl, syntchesis, post route/layout

models

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FE-I4 Top View

ANALOGARRAY

(digital part)

DIGITALARRAY

END OF COLUMN

END OF CHIP

COMMAND DECODER

REGISTER MEMORY

PLL

PLL

DATA OUTPUT

- verilog model

- Implementation (rtl/gate)

Chip Interface overview

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FE-I4

DETECTOR(PIX)

OUTPUT(RECIVE)

MANUAL

SLOW COMAND(CMD)

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OVM OVC (Open Verification Component)

Transaction

Sequences

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Example Sequence of Transaction:

- send reset

- write register 10

- send trigger

Slow control transaction

Transaction is an abstract (human readable) information that will be translated (by driver) to correct signal sequence

File: /digital/FEI4_A\/TB/cmd/sv/cmd_transfer.sv

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Slow control sequence

Sequence define transaction sequence. It is possible to run one sequence inside another one.

File: digital/FEI4_A/TB/cmd/sv/cmd_master_seq_lib.sv

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Verification environment (test)

Verification environment connect all interfaces (OVC) blocks.

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For FE-I4 we heve 4 OVC:

- PIX

- CMD

- REVEIVE

- MANUAL

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Virtual sequence

Virtual Sequence defines top sequence of sequences. Sequences can be from different interfaces! Can be started in parallel or one after another.

MANUAL(rst):- reset hi- reseet low

CMD (rst):

- reset cmd. - clear reg. - clear sr

CMD (defult)

- reg 12 val X - reg 25 val X.....

PIX (random hits)

- pix. 5 hit=100ns - pix 2000. hit=40ns...

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Scoreboard

FE-I4

COMMANDS

PIXEL HITS

RECEIVED DATA

SCOREBOARD:

CHECK !

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Test

TEST

TOP SEQUENCER

SEQ A

SEQ DSEQ B

SEQ C

SEQ E

SCOREBOARD

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Example test

TEST : clear_sr

SEQUENCER: clear_sr_top_seq

reset_seq configure_seq

clear_sr_seq

SCOREBOARD : clear_sr_scoreboard

read_sr_seq

Example result

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Status

All blocks are instantiated and connected (need some polishing and sync with main integration)

Few test are written and are working but needs much more

Need to define manual interface

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BACKUP SLIDES

Slow control transaction

Transaction is an abstract (human readable) information that will be translated (by driver) to correct signal sequence

File: /digital/FEI4_A\/TB/cmd/sv/cmd_transfer.sv

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Slow control sequence

Sequence define transaction sequence. It is possible to run one sequence inside another one.

File: digital/FEI4_A/TB/cmd/sv/cmd_master_seq_lib.sv

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Virtual sequence

Virtual Sequence defines top sequence of sequences. Sequences can be from different interfaces! Can be started in parallel or one after another.

File: digital/FEI4_A/TB/top_tb/sv/top_seq_lib.sv

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Receive transaction

File: digital/FEI4_A/TB/receive/sv/receive_transfer.sv

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Example scoreboard

Scoreboard receives information from monitors (inputs, outputs). Gathered data can be checked for correctness.

File: digital/FEI4_A/TB/top_tb/sv/cmd_scoreboard_lib.sv

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Test DefinitionTest organize everything together. You have multiple tests to test different functions.

File: digital/FEI4_A/TB/top_tb/tests/top_test_lib.sv

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Example result

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How to add test Create sequences Create a scoreboard Create a test Run simulation

How to run simulation:- see vsim_top procedure in digital/FEI4_A/TB/vsim.tcl

- change the parameter OVM_TESTNAME to your test class name

“vsim +OVM_TESTNAME=test_example_top -novopt top_tb_top”

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