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2008 4th International IEEE Conference "Intelligent Systems"

Implementation of Centroid DefuzzifierBlock Using CMOS Circuits

M. Mokarram, A. Khoei, Kh. Hadidi, K. Gheysari

(I)

Abstract-A voltage input current output multiplier and acurrent input voltage output divider circuit to realize thecentre of gravity defuzzifier strategy is described in thispaper. The proposed circuit has a compact architectureoperating at higher speed and higher input voltage rangecompared to previously presented structures. The transistorsoperate in the both saturation and ohmic regions. The circuitoperates with a single supply voltage of 3.3V in a 0.35 JimCMOS technology. The total harmonic distortion (TUD) ofmultiplier is less than 1.1%, the linearity error is also less than3%, and -3db frequency is more than 180 MUz with voltage

input range of 3 Vp _p • Simulation results are given to verify

the functionality of the proposed circuits.

Index Terms-defuzzifier, multiplier, divider, CMOS

I. INTRODUCTION

A fuzzy processor consists of four fundamental units,which are the fuzzification unit, decision making logic unit,defunzzification unit, and knowledge base. In the past,most fuzzy processors are implemented by software, but ahard-ware implemented one is more suitable for real-timeapplications. For hardware realization, the fuzzy processorsare almost implemented with digital circuits in the earlieryears, but the defuzzification units are usually not includedin these designs because the digital multiplier and dividercircuits used to realize the centre of gravity (COG)defuzzifier will occupy large chip area. The roles thesedefuzzifiers should play in these fuzzy processors areusually replaced off-chip microprocessors. Therefore, thebandwidth of a microprocessor dominates the limitation ofthe speed of a fuzzy processor. For this reason, manycircuits have been proposed to realize the fuzzy processorsto overcome these shortcomes[2].

The input for the defuzzification process is a fuzzy setand the output is a single number. As much as fuzzinesshelps the rule evaluation during the intermediate steps, thefinal output for each variable is generally a single crispnumber. So, given a fuzzy set that encompasses a range ofoutput values, we need to return one number, therebymoving from a fuzzy set to a crisp output. Perhaps the mostpopular defuzzification method is the centroid calculation,

Majid Mokarram najafabad is with Microelectronics ResearchLaboratory Urmia University, Urmia, Iran (e-mail:st_m.mokarram@urmia.ac.ir).

Abdollah Khoei is with Microelectronics Research Laboratory UrmiaUniversity, Urmia, Iran (e-mail: a.khoei@urmia.ac.ir).

Khayrollah Hadidi is with Microelectronics Research LaboratoryUrmia University, Urmia, Iran (e-mail: kh.hadidi@urmia.ac.ir).

Kazem Gheysari is with Microelectronics Research Laboratory UrmiaUniversity, Urmia, Iran (e-mail: st_k.Gheysari@urmia.ac.ir).

which returns the center ofarea under the curve [3].In this paper, we propose an analog voltage-mode

defuzzifier circuit, which is designed based on the voltage­input current-output four quadrant analog multiplier circuitand current-input voltage-output divider circuit. This circuittakes the advantages of analog approach, like high speed,small chip area; it also has the advantages of feweradder/subtractor circuits.

II. CIRCUIT DESCRIPTION

There are several defuzzification methods. Below weshow the most common ones when rules fire individually.In this paper we optimize the center of area defuzzificationmethod.

A. The Center ofArea Method

The center of area generates the center of gravity of thepossibility distribution of the inferred fuzzy output. In thecase of a discrete universe, the equation is:

I..uAwjpjZ - _J=_I _

o - n

L,uz{WJ )J=1

Where n is the number of quantization levels of theoutput. The block diagram of this defuzzifier is shown inFig. 1.

output

Fig. 1. The block diagram ofdefuzzifier

As illustrated in Eq. (I) and the block diagram ofcentroid difuzzifier method, we need divider, multiplier andadder circuits.

B. Quarter-Square Multiplier

The differential squaring circuit is illustrated in Fig.2.One of the input voltages is applied to the gates (x) and theother one to the sources (y) of transistors MI-M4 which arebiased with appropriate common-mode voltages X and Y insaturation region. Therefore the drain current of eachtransistors can be calculated as:

978-1-4244-1739-1/08/$25.00 © 2008 IEEE 2-26

Y+Y/2 Y-Y/2Fig. 2. The multiplier using Differential Squaring Circuit

X+XI2

X-XI20-----+-------'

I = f1Cox (W)[v _V ]2d 2 L GS TH (2)

output of attenuator circuit, so that the attenuator circuitchanges to the circuit that is shown in Fig. 4.

Fig. 4. The input block of multiplier circuit with voltage level shifter

Where VTH is threshold voltage of NMOS transistors,

the differential output current of the circuit proportional tothe multiplication of two input signals which is calculatedas:

10 = (Idl +1d3 )-(Id2 + Id4 )= ~ox (:)X2XXY (3)

10 =JlCox(:)XY (4)

As transistor Ml works in saturation region the outputvoltage of that circuit becomes:

1-II rot II ro2 II RL (5)

V gmb Vout = 1 1 X in

-llrotllro21lRL +-g~ gm

So the gain ofattenuator circuit can be calculated as:

1In above equations RL == - andAv < 1. So that both

gminput-signals are attenuated before applying to multiplierinputs. A complete wide-range, high-speed voltage-inputand current-output analog multiplier can be constructed byabove principle as shown in Fig.5.

The proposed multiplier has been simulated using Hspiceand level 49 BSIM3V3 parameters. The circuit operateswith a single supply voltage of 3.3V in a 0.35 Jlm CMOStechnology. The DC-characteristic ofmultiplier is shown inFig. 6. for Vx in x-axis and some different values of Vyfrom -1.5V to +1.5V

All these transistors have to be biased in saturationregion to reach correct answer of above equations. Thevalue of Y+y/2 should be in lower voltage so that the inputrang of above multiplier is decreased. To increase the inputvoltage range and apply biasing of transistors in saturationregion we used the circuit that is shown in Fig.3 in theinput ofabove multiplier.

Fig. 3. The input block of multiplier circuit

When the attenuator circuit is used in X input ofmultiplier, voltage level shifter have to be used at the

A = Vout

v V;n

1-II rot II ro2 II RLgmb (6)

vee

Y+y/2 .,

GNDFig. 5. The complete ofwide-range analog multiplier circuit

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~

lout

r- Y-y/2

Fig. 6. DC-characteristic of proposed circuit for Vx in x-axis

For constant value of x, the frequency response ofproposed circuit is shown in Fig. 7. The band wide is morethan 180 Mhz.

,(----------

12 = fJVd>(V2 - VTN - ~ Vd> ) (8)

13 = kfJVd>(VOU1 -VTN -~Vd,)=lin +kI2 (9)

Where Vds is the common drain-to-source voltage drop

for the three bottom transistors while fJ is the current gain

ratio ofMI and M2. Therefore from the three equations (7­9) output equation of divider can be written as:

(V - V )= (V; - VJ lin (10)O~ 2 k I

d

The circuit in Fig. 8 has been simulated as Fig. 9 which

shows the variation of the output voltage VOlit

as a function

of the numerator current I IN for different values of the

denominator currents I D •

Id=O.zu,~----+----.-....-..-----~------- ..--.-..-..+--------------··-+·---------------+·····------------1--··-7"-······----t-

T\--_..._-

2 ~~.---~-----------------+ ..---- ..-------..-+---.-....--------f---··----······----f-··-----·--·······f----------.---- ..,j.

Vout

lin

Fig .9. Simulation results for the divider circuit.

:

............-!-... IId =O.7u

...... '--":'Id~JU~f····+···············-·.;.·········-·-""·--r··--

,~·-·-~----------------·t·-··--··-------··-+--····-----------f-----···-·····-·-+··------···-~+-----------·----:.Id~O.3u

,~----+-------......-----!--------.--.-..-..+--------------·.-+..···----------+-/----·--------1---- .--....----1·

'Id =O.4u

: Id~ZU

l~ ~ ' -: i , --------..-.."1"-.--------------:.

o ..--:·-----------·--·t....----------··t·--....·---------[--·-------·------[-------·-·....·--r------------·---·}·

v

~~----·-------i-·-·----·-··-+------·---··~··--------·--j----··-----·+·------------f---·····-----·I-----------.+..-.---t-\--I

l------

o 1 () F~llOflCVllogllHi~~Z] 1 lltl<

Fig. 7. Bandwidth of proposed multiplier for constant value ofx

,----

·255 ,~----··-----.I------------+-··--·----·--~-----------·+--·--··--·--+--------·--·f····-·-----·-I---------····I--- ..-t\::::-\

1 225 ~~-----·------t------···---+···----------~-----·-----·+-----··-----+···---···---~--··---------t-----·----·-·i----+\ -------

j; lI

C. Divider Circuit

The divider circuit is a current-input, voltage-outputdivider that is shown in Fig. 8 [1]

Vdd

GND

Fig. 10. Differential-input trasconductor circuit

(11 )

VI+

D. Transconductor Circuit

As the input signals of difuzzifier is in voltagedifferential form so the transconductor circuit is used toapply the summation of input signals to current-inputdivider block.

A class-AB differential-input trasconductor circuit isshown in Fig .10 [4] in which the output current can becalculated as:

lout = p(T7r +V:ff Y

GNU

vee

Fig. 8. The Referenced divider circuit

The division is performed by means of transistors MI,M2, M3 at the bottom layer, all of them being constrainedto operate in the triode region. While VI and V2 are fixedbias voltages, the following relations hold for the draincurrents of the triode transistors [1]:

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Vdd

GND

Fig. 11. Fully differential class-AB transconductor

[1] C. Dualibe, M. Verleysen and G.A. Jespers "Design of AnalogFuzzy Logic Controllers in CMOS Technologies" 2003 KluwerAcademic Publishers New York.

[2] Chuen-Yau Chen, Chun-Yueh Huang and Bin-Da Liu, "A Current­Mode Defuzzifier Circuit to Realize the Centroid Strategy," IEEEInternational Symposium on Circuits and Systems, June 9-12, 1997,Hong Kong.

[3] L. C. Jain, N.M. Martin, "Fusion of Neural Networks, FuzzySystems and Genetic Algorithms: Industrial Applications, "Published in Australia Date: 11/01/98

[4] C. Sawigun and J. Mahattanakul, "A Low-Voltage CMOS LinearTransconductor Suitable for Analog Multiplier Application," IEEEInternational Symposium on Circuits and Systems, 2006,

[5] F.1. Pelayo, I. Rojas, 1. Ortega and A. Prieto, "CURRENT-MODEANALOGUE DEFUZZIFIER" Electronics letters 29th April 1993Vol29N09

[6] Chi-Hung Lin and Mohammed Ismail, "A 1.8V Low-Power CMOSHigh-Speed Four Quadrant Multiplier with Rail-to-Rail DifferentialInput," IEEE 1998, vol 1, pp.37-40,

[7] S. Caiqin and R. L. Geiger, "A ±5-V CMOS Multiplier," IEEE 1.of Solid-State Circuits, vol. SC-22, No.6, pp. 1143-1146, Dec, 1987

[8] B. Boonchu and W. Surakampontorn, "CMOS Class-AB Voltage­Mode Multiplier," Pros. IEEE, PP. 1489-1492,2005

[9] G. Han and E. Sanchez Senencio, "CMOS TransconductanceMultiplier: A Tutorial," IEEE Trans. on Cir. & Syst. II, vo1.45, no.12, pp. 1550-1563, Dec. 1998.

[10] P. Prommee, M. Somdunyakanok, K. Poorahong, P.Phruksarojanakun and K. Dejhan, "CMOS WIDE-RANGE FOUR­QUADRANT ANALOG MULTIPLIER CIRCUIT," Pros. IEEE, PP.197-200, Dec, 2005.

Two input voltages X and Y applied to the multiplier andsummation of output currents of multipliers is applied todivider and the other input of divider is the summation oftrasconductors output current and the input oftrasconductors are Xs as shown in Fig. 9, where X is outputof rule-base and Y is singleton.

REFERENCES

CONCLUSIONS

In this paper, a voltage-mode center of area defuzzifiercircuit based on quarter-square multiplier and voltage-inputcurrent-output divider circuits is proposed. This circuit hasbeen simulated with HSPICE. The experimental resultsindicate that the proposed circuit can work well. Besidesthe functional testing, its transient response is also tested.Rely on this design, a general purpose fuzzy processor canbe achieved

Current~

Current~Rule-base 2 -t

Rule-base 1 ~

Where /3 = /31 = /32 = /33 = /34 .According to (12), it

is clearly seen that the transconductance gain is a square­root function ofthe bias current lB.

The total detailed bloke diagram of center of areadifuzzifier method becomes as Fig .12.

II: 1 WWhere ~-~_~~~ and P="2 f1 ° CoxL is a

MOSFET's transconductance parameter and V. =~ is anref ~p

effective voltage ofMI [4].Fig.11 shows the class AB linear transconductor which is

realized by cross-coupling pair of non-lineartransconductors of Fig. 10. Assuming that MI-M4 are of

identical dimensions, it can be found that for ~ ~Ii 'the

differential output current is linearly dependent on thedifferential input voltage that is shown in equation(12).[4]

+Rule-base n V

Current~

+ Output ofV dIfuzzlD.er

Fig. 12. The total bloke diagram of center ofarea difuzzifier method

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