index preamble structure hollistic fix key concept key research area key application industrial...

INDEXINDEX

• PREAMBLE STRUCTURE• HOLLISTIC FIX• KEY CONCEPT• KEY RESEARCH AREA• KEY APPLICATION• INDUSTRIAL APPLICATION• RESEARCH• HOW WE STUDY• KEY JOBS• PROJECTS ONE CAN DO• TRENDS

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PREMBLE STRUCTUREPREMBLE STRUCTURE

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TEACHERS INTRODUCTION1. NAME OF THE INSTRUCTOR SACHIN DUBEY &

SUMITA GUPTA

2. CABIN LOCATION 209 B

3. TELEPHONENO.9837284395

4. EMAIL-ID tec603.bmas@gmail.com

5. MEETING HOURS–1:00PM To 2.00 P.M

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TEACHERS INTRODUCTION1. NAME OF THE INSTRUCTOR YASHU SWAMI

CABIN LOCATION 317

3. TELEPHONENO.EXTN-210

4. EMAIL-ID tec603.hcst@gmail.com

5. MEETING HOURS– 1.30 P.M To 3.30 P.M

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TEACHERS INTRODUCTION1. NAME OF THE INSTRUCTOR RAGHVENDRA

SHARMA

2. CABIN LOCATION 310

3. TELEPHONENO.

4. EMAIL-ID tec603.aec@gmail.com

5. MEETING HOURS– 11.45 A.M To 12.30 P.M

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PRE REQUISITES Concept of electronics, electricity

(12th standard)

Electric charge – a property of some subatomic particles, which determines their electromagnetic interactions. Electrically charged matter is influenced by, and produces, electromagnetic fields.Electric current – a movement or flow of electrically charged particles, typically measured in amperes.Electric field – an influence produced by an electric charge on other charges in its vicinity.Electric potential – the capacity of an electric field to do work on an electric charge, typically measured in volts.Electromagnetism – a fundamental interaction between the magnetic field and the presence and motion of an electric charge.

HOLLISTIC FIX………ContinuedHOLLISTIC FIX………Continued

Working Principles of Transistor, Semiconductor Devices (MOSFET, JFET, BJT, PN Junction Diode etc, and Sequential & Combinational Logic Circuits).

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PRE REQUISTES(5th Semester)

HOLLISTIC FIX ………ContinuedHOLLISTIC FIX ………Continued

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•To give the information regarding the VLSI technology and Design. Complex Electronic Designing using advanced EDA tools, Simulation and Circuit Analysis.

HOLLISTIC FIX …….ContinuedHOLLISTIC FIX …….Continued

SCOPE IN RELATED FIELDS…

ASIC Designing, Advance High Speed Communication, Nanotechnology.

Image Processing through VLSI Circuit Applications.  Miniaturization of Bio-Medical instruments and

Measurements using precise VLSI circuits.  • •

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VLSI Design Flow Chart

0: Introduction Slide 11

Functional Design

& Verification

Logic Design & Verification

Circuit Design & Verification

System Specification

Physical Design

Layout Verificati

on

Fabrication

& Testing

VLSI DesigningFunctional Designing

Coding the Functions, Requirements according to their Specification through any HDL.

Logic DesigningConverting the Functional Design into Logic Circuit

i.e. through Gates, Resistors, Capacitors etc…Circuit Designing

Converting the Logic Circuit to Transistor Level Circuit, i.e. Gate Level Circuit design to Transistor Level.

Physical Design Conversion of Transistor Level Circuit (Schematic)

into Layout Design.0: Introduction Slide 12

VLSI TECHNOLOGY & DESIGN

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FPGA

Contains thousands, or even more of logic gates with programmable interconnects.

Cost Effective Chip Designing Style.

Programming of interconnects is accomplished by programming of RAM.

Design Flow of FPGA chip starts with behavioral Description i.e. Programming using HDL e.g. Verilog, VHDL etc….

Next Step - -> Mapping - -> Placement & Routing.

Largest Advantage :- Short Turn-around time.  

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GATE ARRAY In terms of Fast Prototyping, GA ranks Second after FPGA.

Propagation Delay Less

GA implementation requires Two-Step Manufacturing process: Phase 1: based on generic masks. Phase 2: Defining metal interconnects between the transistors of the

array.

Since Patterning of metallic interconnects is done at the end of chip fabrication process, turn-around time can be reduced.

Dedicated Areas for Channels for inter-cell routing.

Modern GA use Multiple Layers for Channel Routing

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FULL CUSTOM DESIGN STYLES

Cells are Pre-Designed for general use.Same Cells are utilized in many different chip

designs.Entire mask design is done anew without use

of any library.Development Cost is High.Used in Memory Chips, High Performance

Microprocessors & FPGA Masters.

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STANDARD CELL DESIGN STYLES

Most Prevalent Full Custom Design Styles.Also Called as Polycell.In this Design Style, all the commonly used logic

cells as pre-developed, characterized and stored in Standard Cell Library.

Typical Library may contain few hundreds of Inverters, NAND, NOR, Flip-Flops etc… with different characteristics.

Used in Microprocessors, Digital Signal Processing Chips, Complex Logic Modules etc…

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Comparison of Design Styles

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Comparison of Design Styles

BMAS ENGG COLLEGE, AGRA has developed some material for VLSI DESIGN STYLES. It can be read from following link- http://sachindubey.co.nr/

 Video presentation on vlsi design styles by

Prof S.Srinivasan, Deptt of Electrical Engineering, IIT Madras can be seen on the link:- www.youtube.com/watch?v=7NcKhTYOMMQ

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Comparison of Design Styles

DEVICE FABRICATION

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n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

  CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified

manufacturing process Detailed information is discussed about the step by step fabrication processes listed.

Crystal Growth Epitaxy Oxidation Diffusion Photo Lithography Etching CVD Metallization

    Detailed information can be received from the site : http://sachindubey.co.nr/   Also watch the link about Information- http://nptel.iitm.ac.in/showVideo.php?v=nvmo9voRiSs   http://nptel.iitm.ac.in/showVideo.php?v=9SnR3M3CIm4

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CMOS FABRICATION

VLSI CIRCUIT DESIGN

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g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFF ON

ON OFF

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CMOS VLSI Design0: Introduction Slide 16

CMOS Inverter

A Y

0 1

1 0

VDD

A=0 Y=1

GND

OFF

ON

A Y

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CMOS VLSI Design0: Introduction Slide 21

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

A=1

B=1

Y=0

ON

OFF OFF

ON

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CMOS VLSI Design0: Introduction Slide 22

CMOS NOR Gate

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

A

BY

Channel length modulation

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Channel length modulation in a MOSFET is caused by the increase of the depletion layer width at the drain as the drain voltage is increased. This leads to a shorter channel length and an increased drain current. An example is shown in Figure . The channel-length-modulation effect typically increases in small devices with low-doped substrates. An extreme case of channel length modulation is punch through where the channel length reduces to zero. Proper scaling can reduce channel length modulation, namely by increasing the doping density as the gate length is reduces.

Channel length modulation

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Current-Voltage characteristics of a MOSFET with and without channel length modulation. (Nd = 1017 cm-3, L = 1 m)

Sub-threshold currentThe basic assumption of the MOS capacitor

analysis in section is that no inversion layer charge exists below the threshold voltage. This leads to zero current below threshold. The actual sub-threshold current is not zero but reduces exponentially below the threshold voltage as:

The sub-threshold behavior is critical for dynamic circuits since one needs to ensure that no charge leaks through transistors biased below threshold.

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Field dependent mobilityThe mobility is the inversion layer is distinctly

lower than in bulk material. This is due to the fact the electron wavefunction extends into the oxide and the carrier mobility is lowered due to the lower mobility in the oxide. Higher electric fields at the surface - as typically obtained in scaled devices - push the electron wavefunction even more into the oxide yielding a field dependent mobility. The mobility at the surface, msurface, varies with the electric field, , in the following way:

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Punch throughPunch through in a MOSFET is an extreme case

of channel length modulation where the depletion layers around the drain and source regions merge into a single depletion region. The field underneath the gate then becomes strongly dependent on the drain-source voltage, as is the drain current. Punch through causes a rapidly increasing current with increasing drain-source voltage. This effect is undesirable as it increases the output conductance and limits the maximum operating voltage of the device.

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ScalingThe reduction of the dimensions of a MOSFET has

been has dramatic during the last three decades. Starting at a minimum feature length of 10 mm in 1970 the gate length was gradually reduced to 0.15 mm minimum feature size in 2000, resulting in a 13% reduction per year. Proper scaling of MOSFET however requires not only a size reduction of the gate length and width. It also requires a reduction of all other dimensions including the gate/source and gate/drain alignment, the oxide thickness and the depletion layer widths. Scaling of the depletion layer widths also implies scaling of the substrate doping density.

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RESEARCH AREA OF VLSI DESIGN

NANOTECHNOLOGY.Nanoelectronics holds some answers for how we

might increase the capabilities of electronics devices while we reduce their weight and power consumption. Some of the nanoelectronics areas under development, which you can explore in more detail by following the links provided in the next section, include the following topics.

Improving display screens on electronics devices. This involves reducing power consumption while decreasing the weight and thickness of the screens.

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LOW POWER VLSI DESIGNING.Low power has emerged as a principal theme in today’s

electronics industry.The need for low power has caused a major paradigm

shift where power dissipationhas become as important a consideration as

performance and area. This article reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties.

 The article concludes with the future challenges that

must be met to design low power, high performance systems.

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MIXED SIGNAL DESIGNINGMixed signal designs have both analogue and digital

subsections combined. Overall operation of the system relies on both functionality of each section, and interoperation between the analogue/digital subsections.

 Reasons why do we need Mixed Signal Designs are • Lower cost (fewer devices, footprint, pcb area)• Allows complexity not feasible with isolated

analogue/digital sub-systems• Allows approaches not possible with separated

solutions. 

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VLSI TESTING AND TESTABILITYIncreasing Transistor DensityFeature size reduces by ~10.5%/year leading to

density increase of ~22.1%/year. Wafer and chip size increases in combination with process innovations double this to ~44%/year. This indicates that # of transistors double every 18 to 24 months (Moore’s Law).

 Test ComplexityIncreasing transistor density impacts testing as test

complexity increases due to access restrictions.In the worst case, computational time for test

pattern generation increases exponentially with # of PIs and on-chip FFs.

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HOW WE STUDY......?

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Tutorial Plan Handouts + LAN Server

Reference Sources Handouts + LAN Server

Lecture Plan Handouts + LAN Server

Individual Assignments LAN Server

Group Assignments Handouts + LAN Server

UPTU Paper Mapping LAN Server

I Google Will be shared by individual Gmail Ids

PROJECTS THAT CAN BE DONEFPGA Kit based projects that can done are as-

 Seven Segment Digital clock Traffic Light Controller.Math Coprocessor 

EDA Software based projects that can be done:-

Layout design of 4-bit ADC Design of 16-bit RAM.Layout circuit designing of precise Butterworth Chebyshev

filter 

Encourage the students to design their own Microprocessor (Math Coprocessor) of their own brand.

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TOP COMPANIES OF VLSI WITH THEIR LINKS

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PUBLIC SECTOR

ISROwww.isro.org

Electronics Corporation of India Limited. www.ecil.co.in

Bharat Electronics Limited.www.bel-india.com

Hindustan Aeronautics Limited.www.hal-india.com

Defense Research & Development Organization.www.drdo.org

Semiconductors Complex Ltd.www.scl.com

PRIVATE SECTOR

CADENCE DESIGN SYSTEMSwww.cadence.com/

ST microelectronicswww.st.com

FREESCALE semiconductorshttp://www.freescale.com/

Texas Instrumentswww.ti.com

Motorola Electronicswww.motorola.com

Virage Logicwww.viragelogic.com/

THANK YOU

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