introduction to cmos vlsi design lecture 25: package, power, clock, and i/o david harris harvey mudd...
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Introduction toCMOS VLSI
Design
Lecture 25: Package, Power,
Clock, and I/ODavid Harris
Harvey Mudd College
Spring 2007
25: Package, Power, and I/O Slide 2CMOS VLSI Design
Outline Packaging Power Distribution Clock Distribution I/O
25: Package, Power, and I/O Slide 3CMOS VLSI Design
Packages Package functions
– Electrical connection of signals and power from chip to board
– Little delay or distortion– Mechanical connection of chip to board– Removes heat produced on chip– Protects chip from mechanical damage– Compatible with thermal expansion– Inexpensive to manufacture and test
25: Package, Power, and I/O Slide 4CMOS VLSI Design
Package Types Through-hole vs. surface mount
25: Package, Power, and I/O Slide 5CMOS VLSI Design
Multichip Modules Pentium Pro MCM
– Fast connection of CPU to cache– Expensive, requires known good dice
25: Package, Power, and I/O Slide 6CMOS VLSI Design
Chip-to-Package Bonding Traditionally, chip is surrounded by pad frame
– Metal pads on 100 – 200 m pitch– Gold bond wires attach pads to package– Lead frame distributes signals in package– Metal heat spreader helps with cooling
25: Package, Power, and I/O Slide 7CMOS VLSI Design
Advanced Packages Bond wires contribute parasitic inductance Fancy packages have many signal, power layers
– Like tiny printed circuit boards Flip-chip places connections across surface of die
rather than around periphery– Top level metal pads covered with solder balls– Chip flips upside down– Carefully aligned to package (done blind!)– Heated to melt balls– Also called C4 (Controlled Collapse Chip Connection)
25: Package, Power, and I/O Slide 8CMOS VLSI Design
Package Parasitics
Chip
Signal P
ins
PackageCapacitor
Signal P
ads
ChipVDD
ChipGND
BoardVDD
BoardGND
Bond Wire Lead Frame
Package
Use many VDD, GND in parallel
– Inductance, IDD
25: Package, Power, and I/O Slide 9CMOS VLSI Design
Heat Dissipation 60 W light bulb has surface area of 120 cm2
Itanium 2 die dissipates 130 W over 4 cm2
– Chips have enormous power densities– Cooling is a serious challenge
Package spreads heat to larger surface area– Heat sinks may increase surface area further– Fans increase airflow rate over surface area– Liquid cooling used in extreme cases ($$$)
25: Package, Power, and I/O Slide 10CMOS VLSI Design
Thermal Resistance T = jaP
– T: temperature rise on chip
– ja: thermal resistance of chip junction to ambient
– P: power dissipation on chip Thermal resistances combine like resistors
– Series and parallel ja = jp + pa
– Series combination
25: Package, Power, and I/O Slide 11CMOS VLSI Design
Example Your chip has a heat sink with a thermal resistance
to the package of 4.0° C/W. The resistance from chip to package is 1° C/W. The system box ambient temperature may reach
55° C. The chip temperature must not exceed 100° C. What is the maximum chip power dissipation?
25: Package, Power, and I/O Slide 12CMOS VLSI Design
Example Your chip has a heat sink with a thermal resistance
to the package of 4.0° C/W. The resistance from chip to package is 1° C/W. The system box ambient temperature may reach
55° C. The chip temperature must not exceed 100° C. What is the maximum chip power dissipation?
(100-55 C) / (4 + 1 C/W) = 9 W
25: Package, Power, and I/O Slide 13CMOS VLSI Design
Power Distribution Power Distribution Network functions
– Carry current from pads to transistors on chip– Maintain stable voltage with low noise– Provide average and peak power demands– Provide current return paths for signals– Avoid electromigration & self-heating wearout– Consume little chip area and wire– Easy to lay out
25: Package, Power, and I/O Slide 14CMOS VLSI Design
Power Requirements VDD = VDDnominal – Vdroop
Want Vdroop < +/- 10% of VDD
Sources of Vdroop
– IR drops– L di/dt noise
IDD changes on many time scalesclock gating
Time
Average
Max
Min
Power
25: Package, Power, and I/O Slide 15CMOS VLSI Design
Power System Model Power comes from regulator on system board
– Board and package add parasitic R and L– Bypass capacitors help stabilize supply voltage– But capacitors also have parasitic R and L
Simulate system for time and frequency responses
VoltageRegulator
Printed CircuitBoard Planes
Packageand Pins
SolderBumps
BulkCapacitor
CeramicCapacitor
PackageCapacitor
On-ChipCapacitor
On-ChipCurrent Demand
VDD
Chip
PackageBoard
25: Package, Power, and I/O Slide 16CMOS VLSI Design
Bypass Capacitors Need low supply impedance at all frequencies Ideal capacitors have impedance decreasing with Real capacitors have parasitic R and L
– Leads to resonant frequency of capacitor
104
105
106
107
108
109
1010
10-2
10-1
100
101
102
frequency (Hz)
impedance
1 F
0.03
0.25 nH
25: Package, Power, and I/O Slide 17CMOS VLSI Design
Frequency Response Use multiple capacitors in parallel
– Large capacitor near regulator has low impedance at low frequencies
– But also has a low self-resonant frequency– Small capacitors near chip and on chip have low
impedance at high frequencies Choose caps to get low impedance at all frequencies
frequency (Hz)
impedance
25: Package, Power, and I/O Slide 18CMOS VLSI Design
Clock Distribution On a small chip, the clock distribution network is just
a wire– And possibly an inverter for clkb
On practical chips, the RC delay of the wire resistance and gate load is very long– Variations in this delay cause clock to get to
different elements at different times– This is called clock skew
Most chips use repeaters to buffer the clock and equalize the delay– Reduces but doesn’t eliminate skew
25: Package, Power, and I/O Slide 19CMOS VLSI Design
Example Skew comes from differences in gate and wire delay
– With right buffer sizing, clk1 and clk2 could ideally arrive at the same time.
– But power supply noise changes buffer delays
– clk2 and clk3 will always see RC skew
3 mm
1.3 pF
3.1 mmgclk
clk1
0.5 mm
clk2clk3
0.4 pF 0.4 pF
25: Package, Power, and I/O Slide 20CMOS VLSI Design
Review: Skew Impact
F1
F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tskew
CL
Q1
D2
F1
clk
Q1
F2
clk
D2
clk
tskew
tsetup
tpcq
tpdq
tcd
thold
tccq
setup skew
sequencing overhead
hold skew
pd c pcq
cd ccq
t T t t t
t t t t
Ideally full cycle is
available for work Skew adds sequencing
overhead Increases hold time too
25: Package, Power, and I/O Slide 21CMOS VLSI Design
Cycle Time Trends Much of CPU performance comes from higher f
– f is improving faster than simple process shrinks– Sequencing overhead is bigger part of cycle
0 .0 1
0 .1
1
1 0
1 0 0
8 0 3 8 68 0 4 8 6P e n tiu mP e n tiu m II / III
Spe
cInt
95
1985 1988 1991 1994 1997 2000
1.2 0.8 0 .6 0.35 2.0
Process
100
200
500VD D = 5 VDD = 3.3
VDD = 2.5
50Fan
out-
of-4
(F
O4)
Inve
rter
Del
ay (
ps)
0.25
1 0
1 0 0
1 0 0 0
8 0 3 8 68 0 4 8 6P e n tiu mP e n tiu m II / II I
MH
z
1 9 8 8 1 9 9 1 1 9 9 4 1 9 9 7 2 0 0 01 9 8 5
1 0
1 0 0
1 9 8 5 1 9 8 8 1 9 9 1 1 9 9 4 1 9 9 7
8 0 3 8 68 0 4 8 6P e n tiu mP e n tiu m II / II IF
O4
inve
rte
r de
lays
/ cy
cle
50
20
2 0 0 0
25: Package, Power, and I/O Slide 22CMOS VLSI Design
Solutions Reduce clock skew
– Careful clock distribution network design– Plenty of metal wiring resources
Analyze clock skew– Only budget actual, not worst case skews– Local vs. global skew budgets
Tolerate clock skew– Choose circuit structures insensitive to skew
25: Package, Power, and I/O Slide 23CMOS VLSI Design
Clock Dist. Networks Ad hoc Grids H-tree Hybrid
25: Package, Power, and I/O Slide 24CMOS VLSI Design
Clock Grids Use grid on two or more levels to carry clock Make wires wide to reduce RC delay Ensures low skew between nearby points But possibly large skew across die
25: Package, Power, and I/O Slide 25CMOS VLSI Design
Alpha Clock Grids
PLL
gclk grid
Alpha 21064 Alpha 21164 Alpha 21264
gclk grid
Alpha 21064 Alpha 21164 Alpha 21264
25: Package, Power, and I/O Slide 26CMOS VLSI Design
H-Trees Fractal structure
– Gets clock arbitrarily close to any point– Matched delay along all paths
Delay variations cause skew A and B might see big skew A B
25: Package, Power, and I/O Slide 27CMOS VLSI Design
Itanium 2 H-Tree Four levels of buffering:
– Primary driver– Repeater– Second-level
clock buffer– Gater
Route around
obstructionsPrimary Buffer
Repeaters
Typical SLCBLocations
25: Package, Power, and I/O Slide 28CMOS VLSI Design
Hybrid Networks Use H-tree to distribute clock to many points Tie these points together with a grid
Ex: IBM Power4, PowerPC– H-tree drives 16-64 sector buffers– Buffers drive total of 1024 points– All points shorted together with grid
25: Package, Power, and I/O Slide 29CMOS VLSI Design
Input / Output Input/Output System functions
– Communicate between chip and external world– Drive large capacitance off chip– Operate at compatible voltage levels– Provide adequate bandwidth– Limit slew rates to control di/dt noise– Protect chip against electrostatic discharge– Use small number of pins (low cost)
25: Package, Power, and I/O Slide 30CMOS VLSI Design
I/O Pad Design Pad types
– VDD / GND
– Output– Input– Bidirectional– Analog
25: Package, Power, and I/O Slide 31CMOS VLSI Design
Output Pads Drive large off-chip loads (2 – 50 pF)
– With suitable rise/fall times– Requires chain of successively larger buffers
Guard rings to protect against latchup– Noise below GND injects charge into substrate– Large nMOS output transistor– p+ inner guard ring– n+ outer guard ring
• In n-well
25: Package, Power, and I/O Slide 32CMOS VLSI Design
Input Pads Level conversion
– Higher or lower off-chip V– May need thick oxide gates
Noise filtering– Schmitt trigger
– Hysteresis changes VIH, VIL
Protection against electrostatic discharge
AY
VDDH
VDDLA Y
VDDL
A Y
weak
weak
A
Y
25: Package, Power, and I/O Slide 33CMOS VLSI Design
ESD Protection Static electricity builds up on your body
– Shock delivered to a chip can fry thin gates– Must dissipate this energy in protection circuits
before it reaches the gates ESD protection circuits
– Current limiting resistor– Diode clamps
ESD testing– Human body model– Views human as charged capacitor
PADR
Diodeclamps
Thingate
oxides
Currentlimitingresistor
DeviceUnderTest
1500
100 pF
25: Package, Power, and I/O Slide 34CMOS VLSI Design
Bidirectional Pads Combine input and output pad Need tristate driver on output
– Use enable signal to set direction– Optimized tristate avoids huge series transistors
PAD
Din
Dout
En
Dout
En Y
Dout
NAND
NOR
25: Package, Power, and I/O Slide 35CMOS VLSI Design
Analog Pads Pass analog voltages directly in or out of chip
– No buffering– Protection circuits must not distort voltages
25: Package, Power, and I/O Slide 36CMOS VLSI Design
MOSIS I/O Pad 1.6 m two-metal process
– Protection resistors– Protection diodes– Guard rings– Field oxide clamps
Out
En
Out
PAD
In
264 185
In_bIn_unbuffered
600/3
240
160
90
4020
48
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