introduction to vlsi programming high performance dlx

Introduction to VLSI Programming High Performance DLX

(course 2IN30)Prof. dr. ir.Kees van Berkel

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Demonstrator ICsIC Si date # MOSt remark ZaP 87/09 7k feasibility Mill/DfT 92/02 Test compiler; DfT demo DDD 93/05 44k Low-power DDR 93/06 111k Low-power, audible demo ImageNet 94/05 1 week! Heterogeneous timing DDD2 94/09 22k Single-rail, lower power ImageNet-2 95/09 SingleTrack 80C51 95/08 40k Low power, low EME ADPCM 96/03 37k Low power speech codec Mozart 96 Exotic technology PCA5007/10 98 products X, Y, … 98…99 …

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Added value

• 1985: modularity, ease of design(no value added to product!)

• 1990: low power(ESPRIT project )

• 1992: low noise, low EME (Electro-Magnetic Emission)

• 2000: ...

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Added value: low power DCC Error Corrector

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A sync-async “arms race”

DCC error corrector date yy/mm

area [mm2]

power [mW]

synchronous 93 3.4 2.60

async (double-rail) 93/05 7.0 0.41

synchronous 94 3.3 0.60

async (single-rail) 94/09 3.9 0.08

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Added value: Low Power

Synchronous 80C51 - Asynchronous 80C51

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Add

ed v

alue

:

Low

EM

Em

issi

on

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Roadblock: circuit sizethe 80C51 learning curve

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

40005000600070008000900010000

area [gate equivalents]

time

[us]

en

ergy

[nJ]

1995/6 1999/4

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“Just in time” processing

Asynchronous

DSP circuitfifo

DC/DC

in out

Vdd

Vdd’

fifoAsynchronous

DSP circuit

Asynchronous

DSP circuit.

Asynchronous

DSP circuit

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ADPCM

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ADPCM

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ADPCM

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Industrialization of the Technology• Philips Semiconductors Zürich (1994 Dec):

“We want to set a world record in low power, .. by using asynchronous technology.”

• Their choice for a vehicle: the 80C51 micro-controller (used in many consumer products).

• Result: 4× less power, minimal EME.

• Follow-up: pager baseband ICs, …

In parallel: transfer and upgrade of tools + design flow

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Pager Baseband Controller ICsMyna pager:

– FLEX™ protocol– 32 alphanumeric messages– a single AAA battery (1V)– up to 25 weeks battery life

Pager baseband controller ICs:– PCA5007, PCA 5010 – http://www.semiconductors.philips.

com/pip/PCA5007– http://www.win.tue.nl/pa/wsinap/

async.html

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1998-Sep: the PCA 5007

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A new generation of pagers:a common platform for all standards

PCA 5007Baseband Controller

LCD

# M

MemoryReceiverI

Q

I2C

EMI

25V

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EMI: a critical design factor (Electro-Magnetic Interference)

• Antenna signal may be as small as 25V.

• Clock harmonics of synchronous micro-controllers interfere with RF (X00 MHz).

• With asynchronous 80C51: signal decoding by means of (standard-specific) software. (This also enables upgrading/downloading!)

• Furthermore: no shielding is required between controller and RF receiver.

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PC

A50

07 b

lock

dia

gram

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Contactless smartcard IC (ESPRIT project DESCALE)

Power regulator

80C51 micro-controllerDES engineUARTRAM, ROM, EEPROM

13.56 MHz clock

power (a few mW)

bi-directional communication (106 kbit/s)

Radio link:

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Contactless smartcard ICProperties

a) low average power

b) lower peak power

c) speed adaptation

Merits

Maximum speed for received power (a,c)

Robust operation against voltage drops (c)

Smaller buffer capacitor (b,c)

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Conclusion

• First asynchronous VLSI circuits on the market (high volume sales).

• Prospects for more async products look good.• Added value: low power, EME performance.• Added costs: test, IC area, being different.

• Asynchronous VLSI technology:– there is room for it in market niches, – … but it may contribute to main-stream VLSI.

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Bibliography• Computer Architecture; a Quantitative Approach (3rd

Ed.); John L Hennessy & David A Patterson; Morgan Kaufmann Publishers Inc, 1996.

• ARM System Architecture; Steve Furber; Addison Wesley, 1996.

• DSP Processor Fundamentals, Architectures and Features; Phil Lapsey et al (Berkeley Design Technology Inc.), IEEE, 1996.

• www.handshakesolutions.com• www.arm.com/news/6936.html • www.research.philips.com/

newscenter/archive/2004/handshake.html

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Lab-work and report

You are allowed to team up with a colleague (Not mandatory.)

Report: more than listing of functional Tangram programs:• analyze the specifications and requirements;• present design options, alternatives, trade-offs;• motivate your design choices;• explain functional correctness of your Tangram programs;• analyze & explain {area, time, energy} of your programs.