ivanovici1 mapld 2005 / 152 assessing application performance in degraded network environments –...
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Ivanovici 1 MAPLD 2005 / 152
Assessing Application Performance in Degraded Network Environments
– An FPGA-based Approach –
Mihai Ivanovici CERN, Geneva & POLITEHNICA University, Bucharest
Dr. Razvan Beuran CERN, Geneva & POLITEHNICA University, Bucharest
Dr. Neil Davies Predictable Network Solutions, Bristol
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Outline
Motivation Application performance assessment methodology
Network emulator architecture Implementation considerations The hardware platform
Experimental results Short-lived HTTP transfers over large delay connections
Conclusions & future work Acknowledgements
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Motivation
Rationale: methodology for assessing the effects of network quality degradation on applications
CERN’s interest Long-distance networks have high costs must make
an optimal use of resources
What affects applications is not so much “quality” as the “quality degradation” (ΔQ) experienced This is something we can reproduce in the laboratory
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Influence of quality degradation on application outcome
Interaction of Quality Degradation (ΔQ) and User-Perceived Quality (UPQ) for VoIP (G.711)
Applications only care about the outcome, not the mechanisms
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Networks = Degraded Environments
Assess application performance under varying network conditions
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Assessing application performance
Simultaneously Measure the network quality degradation (ΔQ) Assess the UPQ for the application under test
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Reproducible & controllable conditions
Network emulation Hybrid technique that uses real applications Wide range of network conditions
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The architecture
Replaceable modular components
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Implementation philosophy
Use of message passing Abstraction reusability & independent module design Asynchronous concurrent processes (18)
Use of Handel-C The concept of channels (CSP, Occam) Rapid development and translation into hardware Easy debugging due to channel-based architecture
Flexible (custom) design Other projects: GE tester, sniffers, traffic emulators
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The hardware platform
1 Altera Stratix FPGA (25 k LEs) 2 GE PHYs 128 MB SDRAM 2 MB SSRAM 1 FLASH memory 3V3 PCI connector IP cores:
MAC IP core PCI controller SDRAM controller
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Architectural choice – SDRAM access
Direct access / semaphore Client / Server architecture
Inter-domain data transfers using channels are slow (4 cycles per word)
Inter-domain data transfers using dual-port on-chip RAM are fast (1 cycle/word)
8-word burst SDRAM operations
>600 lines of code ~300 lines of code
Achieved rate: 400 Mb/s Achieved rate: 1 Gb/s
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The SDRAM Serverwhile( 1 ) prialt { case sdram_read_request_channel ? operation: par { sdr0_read_burst8(memory_address, context); sdr1_read_burst8(memory_address, context); } sdram_read_response_channel ! (unsigned 1) 1; break;
case sdram_write_request_channel ? operation: par { sdr0_write_burst8(memory_address, context); sdr1_write_burst8(memory_address, context); } sdram_write_response_channel ! (unsigned 1) 1; break; }
Channel selection
Read 8-word burstsfrom SDRAM #0 & #1
Confirm operation completion
Write 8-word burststo SDRAM #0 & #1
Confirm operation completion
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HTTP test resultsSite download duration vs. offered
background traffic load
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Current emulators
Do exist Mainly software based
Packet by packet systems Independent loss and delay applied to packets
unrealistic behaviour False packet reordering Intra-stream contention not modeled
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Why another emulator?
More realistic scenarios Intra-stream and inter-stream contention
Correlated loss and delay, natural induced jitter
Phase / mode changes in network Topology or environment changes (e.g. wireless)
More flexibility and control on the degradation models
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Conclusions
Methodology for assessing application performance
Network emulator Use FPGA 1 G/s bidirectional High-accuracy operation Realistic effects through the use of intra- and inter-
stream contention mechanisms
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Future work
Emulate multiple hops Implement server with vacations algorithms Aggregate models of queues and wires into one
single model Build a new board
Bigger and faster FPGA External (USB connected) Larger SDRAM
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Acknowledgments
Brian Martin and Jaroslav Pech for designing the board
Matei Ciobotaru for implementing the low-level libraries for access to board components
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