lecture 3: cmos transistor theory - university of pittsburgh · lecture 3: cmos transistor theory...

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Introduction toCMOS VLSI

Design

Lecture 3: CMOS Transistor Theory

David Harris

Harvey Mudd CollegeSpring 2004

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3: CMOS Transistor Theory Slide 2CMOS VLSI Design

OutlineIntroductionMOS CapacitornMOS I-V CharacteristicspMOS I-V CharacteristicsGate and Diffusion CapacitancePass TransistorsRC Delay Models

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3: CMOS Transistor Theory Slide 3CMOS VLSI Design

IntroductionSo far, we have treated transistors as ideal switchesAn ON transistor passes a finite amount of current– Depends on terminal voltages– Derive current-voltage (I-V) relationships

Transistor gate, source, drain all have capacitance– I = C (ΔV/Δt) -> Δt = (C/I) ΔV– Capacitance and current determine speed

Also explore what a “degraded level” really means

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MOS Transistors MOS Transistors -- Types and SymbolsTypes and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact

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The MOS TransistorThe MOS Transistor

Polysilicon Aluminum

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Controlling current flow in an Controlling current flow in an nFETnFET..

Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.

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© Digital Integrated Circuits2nd DevicesIntroduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.

Controlling current flow in a Controlling current flow in a pFETpFET..

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What is a Transistor?What is a Transistor?

VGS ≥ VT

RonS D

A Switch!

|VGS|

A MOS Transistor

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I-V Curves

ResistorI = V/R

DiodeI = Is*exp(k*V-Vt)

Current (I) vs. Voltage (V)I = f(V)

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10-4

VDS

I D(A

)

MOSI = f(Vgs, Vds)

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3: CMOS Transistor Theory Slide 10CMOS VLSI Design

Terminal VoltagesMode of operation depends on Vg, Vd, Vs

– Vgs = Vg – Vs

– Vgd = Vg – Vd

– Vds = Vd – Vs = Vgs - Vgd

Source and drain are symmetric diffusion terminals– By convention, source is terminal at lower voltage– Hence Vds ≥ 0

nMOS body is grounded. First assume source is 0 too.Three regions of operation– Cutoff– Linear– Saturation

Vg

Vs Vd

VgdVgs

Vds+-

+

-

+

-

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3: CMOS Transistor Theory Slide 11CMOS VLSI Design

MOS CapacitorGate and body form MOS capacitorOperating modes– Accumulation– Depletion– Inversion

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg < 0

(b)

+-

0 < Vg < Vt

depletion region

(c)

+-

Vg > Vt

depletion regioninversion region

In general, MOS gate capacitance is not constant

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© Digital Integrated Circuits2nd DevicesCopyright © 2005 Pearson Addison-Wesley. All rights reserved.

MOS Transistors MOS Transistors –– Operating regions Operating regions

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3: CMOS Transistor Theory Slide 13CMOS VLSI Design

nMOS CutoffNo channelIds = 0

+-

Vgs = 0

n+ n+

+-

Vgd

p-type body

b

g

s d

d

s

g

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3: CMOS Transistor Theory Slide 14CMOS VLSI Design

nMOS LinearChannel formsCurrent flows from d to s – e- from s to d

Ids increases with Vds

Similar to linear resistor

+-

Vgs > Vt

n+ n+

+-

Vgd = Vgs

+-

Vgs > Vt

n+ n+

+-

Vgs > Vgd > Vt

Vds = 0

0 < Vds < Vgs-Vt

p-type body

p-type body

b

g

s d

b

g

s d Ids

d

s

g

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n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

Linear Region Linear Region VVgsgs>>VVtt & & VVgdgd>>VVtt

Positive Charge on Gate:Channel exists, Current Flows

since Vds > 0Ids = k’(W/L)((Vgs-Vt)Vds-Vds

2/2)

R

Vgd

Vgs

Ids

Vds

I=V/R

R= 1/(k’(W/L)(Vgs-Vt))

Ids

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3: CMOS Transistor Theory Slide 16CMOS VLSI Design

nMOS SaturationChannel pinches offIds independent of Vds

We say current saturatesSimilar to current source

+-

Vgs > Vt

n+ n+

+-

Vgd < Vt

Vds > Vgs-Vt

p-type bodyb

g

s d Ids

d

s

g

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n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-

Saturation: Saturation: VVgsgs>>VVtt & & VVgdgd<<VVtt

Positive Charge on Gate:Channel exists, Current Flows

since Vds > 0But: channel is “pinched off”

Ids = (k’/2)(W/L)(Vgs-Vt)2

Vgd

Vgs

Ids

Ids

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3: CMOS Transistor Theory Slide 18CMOS VLSI Design

I-V CharacteristicsIn Linear region, Ids depends on– How much charge is in the channel?– How fast is the charge moving?

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© Digital Integrated Circuits2nd DevicesCopyright © 2005 Pearson Addison-Wesley. All rights reserved.

MOS Transistors MOS Transistors –– Regions Transitions Regions Transitions

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3: CMOS Transistor Theory Slide 20CMOS VLSI Design

Channel ChargeMOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

Qchannel =

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate

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3: CMOS Transistor Theory Slide 21CMOS VLSI Design

Channel ChargeMOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

Qchannel = CVC =

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate

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3: CMOS Transistor Theory Slide 22CMOS VLSI Design

Channel ChargeMOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

Qchannel = CVC = Cg = εoxWL/tox = CoxWLV =

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate

Cox = εox / toxCox = 8.6*fF/um2

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3: CMOS Transistor Theory Slide 23CMOS VLSI Design

Channel ChargeMOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

Qchannel = CVC = Cg = εoxWL/tox = CoxWLV = Vgc – Vt = (Vgs – Vds/2) – Vt

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate

Cox = εox / tox

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3: CMOS Transistor Theory Slide 24CMOS VLSI Design

Carrier velocityCharge is carried by e-Carrier velocity v proportional to lateral E-field between source and drainv =

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3: CMOS Transistor Theory Slide 25CMOS VLSI Design

Carrier velocityCharge is carried by e-Carrier velocity v proportional to lateral E-field between source and drainv = μE μ called mobilityE =

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3: CMOS Transistor Theory Slide 26CMOS VLSI Design

Carrier velocityCharge is carried by e-Carrier velocity v proportional to lateral E-field between source and drainv = μE μ called mobilityE = Vds/LTime for carrier to cross channel:– t =

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3: CMOS Transistor Theory Slide 27CMOS VLSI Design

Carrier velocityCharge is carried by e-Carrier velocity v proportional to lateral E-field between source and drainv = μE μ called mobilityE = Vds/LTime for carrier to cross channel:– t = L / v

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3: CMOS Transistor Theory Slide 28CMOS VLSI Design

nMOS Linear I-VNow we know– How much charge Qchannel is in the channel– How much time t each carrier takes to cross

dsI =

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3: CMOS Transistor Theory Slide 29CMOS VLSI Design

nMOS Linear I-VNow we know– How much charge Qchannel is in the channel– How much time t each carrier takes to cross

channelds

QIt

=

=

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3: CMOS Transistor Theory Slide 30CMOS VLSI Design

nMOS Linear I-VNow we know– How much charge Qchannel is in the channel– How much time t each carrier takes to cross

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QIt

W VC V V VL

VV V V

μ

β

=

⎛ ⎞= − −⎜ ⎟⎝ ⎠

⎛ ⎞= − −⎜ ⎟⎝ ⎠

ox = WCL

β μ

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Computed CurvesComputed Curves

Vgs = 5v

Vgs = 4.5v

Vgs = 4.0v

Linear Resistor

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3: CMOS Transistor Theory Slide 32CMOS VLSI Design

nMOS Saturation I-VIf Vgd < Vt, channel pinches off near drain– When Vds > Vdsat = Vgs – Vt

Now drain voltage no longer increases current

dsI =

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3: CMOS Transistor Theory Slide 33CMOS VLSI Design

nMOS Saturation I-VIf Vgd < Vt, channel pinches off near drain– When Vds > Vdsat = Vgs – Vt

Now drain voltage no longer increases current

2dsat

ds gs t dsatVI V V Vβ ⎛ ⎞= − −⎜ ⎟

⎝ ⎠

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3: CMOS Transistor Theory Slide 34CMOS VLSI Design

nMOS Saturation I-VIf Vgd < Vt, channel pinches off near drain– When Vds > Vdsat = Vgs – Vt

Now drain voltage no longer increases current

( )2

2

2

dsatds gs t dsat

gs t

VI V V V

V V

β

β

⎛ ⎞= − −⎜ ⎟⎝ ⎠

= −

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3: CMOS Transistor Theory Slide 35CMOS VLSI Design

Computed Curves

Vgs = 5v

Vgs = 4.5v

Vgs = 4.0v

Linear Resistor

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3: CMOS Transistor Theory Slide 36CMOS VLSI Design

nMOS I-V Summary

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V VVI V V V V V

V V V V

β

β

⎧⎪ <⎪⎪ ⎛ ⎞= − − <⎜ ⎟⎨ ⎝ ⎠⎪⎪

− >⎪⎩

Shockley 1st order transistor models

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3: CMOS Transistor Theory Slide 37CMOS VLSI Design

ExampleWe will be using a 0.180 μm process for your project– From TSMC Semiconductor– tox = 40 Å– μ = 180 cm2/V*s– Vt = 0.4 V

Plot Ids vs. Vds

– Vgs = 0, 0.3,…, 1.8 – Use W/L = 4/2 λ

( )14

28

3.9 8.85 10350 120 /100 10ox

W W WC A VL L L

β μ μ−

−

⎛ ⎞• ⋅ ⎛ ⎞= = =⎜ ⎟⎜ ⎟⋅ ⎝ ⎠⎝ ⎠180

40155

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3: CMOS Transistor Theory Slide 38CMOS VLSI Design

pMOS I-VAll dopings and voltages are inverted for pMOSMobility μp is determined by holes– Typically 2-3x lower than

that of electrons μn

Thus pMOS must be wider to provide same current– Often, assume μn / μp = 2

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CurrentCurrent--Voltage RelationsVoltage RelationsLongLong--Channel DeviceChannel Device

Cut-off (VGS – VT < 0) “no current” (not really)

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IIDD versus Vversus VDS DS short channel deviceshort channel device

-4

VDS(V)0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10-4

VDS(V)

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

Long Channel Short Channel

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RabaeyRabaey’’ss unified modelunified modelfor manual analysisfor manual analysis

S D

G

B

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Transistor Model Transistor Model for Manual Analysisfor Manual Analysis

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Simple Model versus SPICE Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS (V)

I D(A

)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

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Even Simpler:Even Simpler:The Transistor as a SwitchThe Transistor as a Switch

VGS ≥ VT

RonS D

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

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The Transistor as a SwitchThe Transistor as a Switch

This week’s Lab – find Req for our TSMC 180nm process

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Saturation EffectsSaturation Effects

Which is the resistor?

Discharge of 1pf capacitor, with Vgs of 3,4,5 volts. Also, 12k resistor.

d

s

g

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3: CMOS Transistor Theory Slide 47CMOS VLSI Design

More on CapacitanceAny two conductors separated by an insulator have capacitanceGate to channel capacitor is very important– Creates channel charge necessary for operation

Source and drain have capacitance to body– Across reverse-biased diodes– Called diffusion capacitance because it is

associated with source/drain diffusion

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3: CMOS Transistor Theory Slide 48CMOS VLSI Design

Gate CapacitanceApproximate channel as connected to sourceCgs = εoxWL/tox = CoxWL = CpermicronWCpermicron is typically about 2 fF/μm

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9ε0)

polysilicongate

49

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The Gate Capacitance The Gate Capacitance

tox

n+ n+

Cross section

L

Gate oxide

xd xd

L d

Polysilicon gate

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W

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DynamicDynamic Behavior of MOS TransistorBehavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB

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Physical visualization of FET Physical visualization of FET capacitancescapacitances

Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.

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© Digital Integrated Circuits2nd DevicesCopyright © 2005 Pearson Addison-Wesley. All rights reserved.

MOS Capacitances Behavior !MOS Capacitances Behavior !

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Gate Capacitance Gate Capacitance –– BehaviorBehavior

S D

G

CGC

S D

G

CGCS D

G

CGC

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

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Measuring the Gate CapMeasuring the Gate Cap

2 1.52 1 2 0.5 0

3

4

5

6

7

8

9

103 102 16

2

VGS (V)

VGS

Gat

e C

apac

itanc

e (F

)

0.5 1 1.5 22 2

I

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3: CMOS Transistor Theory Slide 55CMOS VLSI Design

Diffusion CapacitanceCsb, Cdb

Undesirable, called parasitic capacitanceCapacitance depends on area and perimeter– Use small diffusion nodes– Comparable to Cg

for contacted diff– ½ Cg for uncontacted– Varies with process

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Diffusion CapacitanceDiffusion Capacitance

Bottom

Side wall

Side wallChannel

SourceND

Channel-stop implantNA1

Substrate NA

W

xj

L S

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Final construction of the Final construction of the nFETnFET RC RC modelmodel

Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.

CG

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Summary of MOSFET Operating Summary of MOSFET Operating RegionsRegions

Strong Inversion VGS > VTLinear (Resistive) VDS < VDSAT

Saturated (Constant Current) VDS ≥VDSAT

Weak Inversion (Sub-Threshold) VGS ≤VTExponential in VGS with linear VDS dependence