low power, high-throughput ad converters
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Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Scan-Flash ADCLow Power, High-Throughput AD Converters
Melvin EzePennsylvania State University
eze@cse.psu.edu
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Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Outline
• ADC Converters• Flash ADC• Scan-Flash Architecture• Target Specifications• Schedule• References
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Analog-Digital Converters
• DSP is really wonderful but…• Real World Signals are Analog:
– Continuous time– Continuous amplitude
• DSP can only process:– Discrete time– Discrete amplitude
• Need for data conversion from Analog to Digital and back
AnalogPre-Processing
A/DConversion
DSP
D/AConversion
AnalogPost-Processing
Filters
?
000..001..
011
?
Filters
Analog Output
Analog Input
Slide Adapted from: Haideh Khorramabadi EE247 Class Slides
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Example: A typical Cell Phone
Slide Adapted from: Haideh Khorramabadi EE247 Class Slides
Contains an Integrated form of:• 4 Rx Filters• 4 Tx Filters
• 4 Rx ADCs• 4 Tx DACs
• 3 Auxiliary ADCs• 8 Auxiliary DACs
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Flash ADC
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Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Flash ADC
Encoding Logic
VREFVIN 54.94.84.7
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.
2.52.4
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0.30.20.10.0
4.75
54.94.84.7
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2.52.4
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0.30.20.10.0
4.755
4.9
4.7
4.75 4.754.75
4.754.754.75
4.754.754.75
4.75
Ctotal = (2B - 1) * Ccomparator Ctotal = Comparison count * Ccomparator
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Scan-Flash ADC
Encoding Logic
SwitchControl
Logic
EN
EN
EN
EN
EN
High frequency
clock
VREFVIN
Key Features
• Switched Input• Multi-cycle latching of Thermometer code• Minimum effect on CIN
• Control Logic is Shift-Register based• Implement multi-channel ADCs
Other Features
• Reduces capacitance per comparison• Naturally amenable to optimization alg
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Scan-Flash ADC
Encoding Logic
SwitchControl
Logic
EN
EN
EN
EN
EN
High frequency
clock
VREFVIN
Scan Techniques for B-bit ADC
• Linear Scan [O(2B)]• Very Simple but very inefficient
• Binary Tree Scan [O(B)]• Very efficient but tough to implement so far
• Linear Window Scan [O(K)] • K > B, but be implementation characteristics
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Multi channel-Flash ADC
Encoding Logic
SwitchControl
Logic
EN
EN
EN
EN
EN
High frequency
clock
VREFVIN_K
SwitchControl
Logic
VIN_2
SwitchControl
Logic
VIN_1
K stages
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Target Specifications
• 2 Channels [2-Scan-Flash ADC]• 8 bit per channel • Power Supply: 5V• Power Consumption: 400 mW• DNL/INL: 1 LSB• Area: 1mm2
• Speed: 50 MSPS per channel (100 MSPS aggregate)• Operating Frequency: 100MHz
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Scan-Flash ADCLow Power, High-Throughput AD Converters
Melvin EzePennsylvania State University
eze@cse.psu.edu
QuickTime™ and aTIFF (LZW) decompressor
are needed to see this picture.
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Schedule
• Week 1: Specifications and Initial Simulations• Week 2: Complete SPICE Implementation of Switch• Week 3: Complete Verilog Implementation of Digital Control• Week 4: Schematic Layout of single channel SCAN-FLASH -no
ROM in Cadence Schematic Editor• Week 5: Begin Module layout in Virtuoso and SPICE
simulations• Week 6: More Layout• Week 7: Complete Layout• Week 8: Full System test and Performance Analysis• Week 9: Debug and Complete
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Progress
• Week 1 - Week 4• Initial simulation of 3-bit single channel• Simulation and schematic layout• Initial Floor plan for layout
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Design Verification
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Binary Tree
Input Resistors
Output Registers
Control Registers
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Input Stage
Track and Hold• T_H sampling clock• 1 pF capacitor• 100 MHz bandwidth
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Input StageTrack and Hold
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Tree Stage
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Tree Stage
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
V_switch
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Comparator
Simulation Data
• Max Gain-Bandwidth: 6g• Open Loop Gain: 200• Power: 17mW• Test Voltage: 3.3V
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Comparator
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Output Stage
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Control Registers
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Projected Floorplan
Silicon SubstrateT/H blocks
ComparatorsShift Registers
Analog Input/VDDClock
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Components
Scan/Hold, Unity Gain, Comparator, Resistor Ladder,
D Flip-flop, DC Biasing
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Scan-Flash ADC
Encoding Logic
SwitchControl
Logic
EN
EN
EN
EN
EN
High frequency
clock
VREFVIN
Scan Techniques for B-bit ADC
• Linear Scan [O(2B)]• Very Simple but very inefficient
• Binary Tree Scan [O(B)]• Very efficient but tough to implement so far
• Linear Window Scan [O(K)] • K > B, but be implementation characteristics
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Binary Tree
Input Resistors
Output Registers
Control Registers
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Final Design
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Outputs go to registers
Key Features. Multi-Stage T/H. Two Signal Control. Bussed Stage Output. High Speed, Pipelined
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
8 bit S/F ADC
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Track / Hold
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Unity Gain Buffer
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
T/H Layout
•
Track/Hold Capacitor with Unity Gain Stage for chainingApprox Max freq: 100MHz
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Multi Stage T/H
• 8 stage T/H chain for 8-bit ADC
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Design Details
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Cell Tree Design Features. No Resistor Ladder!. No Thermometer code!. Max Freq determined by timing on last stage
Output Register Features. No Wide OR gates!. Only control: CLOCK. No Decoder
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Cell Module Schematic
Design becomes very modular!
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
D Latch
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
D flip Flop
Simple Master-Slave configuration
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
D Flip Flop Layout
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Comparator
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Cell Layout
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
8 bit S/F ADC
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
3-bitADC Layout
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design
References
• Rezhavi, B: CMOS Analog Circuit Design
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