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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapter 11
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9.1.2009
Low Power System-on-Chip Design
Chapter 11
Tomasz Patyk
Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Chapter 11: Implementing Multi-Voltage, Power Gated
Designs
Design Partitioning
Design Flow Overview
Synthesis
Design Planning
Power Planning
Clock Tree Synthesis
Power Analysis
Timing Analysis
Lower Power Validation
Manufacturing Test
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Unit/Name to be changed on the master page
ARM1176JZF-S – used as
an implementation
example of the multi-
voltage, power gated
design
Three power domanis in
the design An always-on power domain
(VSOC)
A shutdown power domain
(VCPU)
An always-on power domain
(VRAM)
Low Power System-on-Chip Design Chapters 3-4
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Implementation example
Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-Chip
Design”
Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Definitions
Power Domain – collection of design elements that share a primary
power supply (logical entity, created during synthesis phase)
Voltage Area – geographic area of a chip storing logic from the
particular power domain (phisical entity, created during design
planning phase)
One power domain can have multiple voltage areas
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Design Partitioning – logical and phisical hierarchy
Partitioning introduces interfaces (impact on the performance)
Map entire functional units to certain power domain
High correlation between power domain and logical hierarchy
minimizes the number of signals crossing power domain
interfaces
Number of power domains as low as possible
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Design Partitioning – logical and phisical hierarchy cont.
Following objectives are meat:
Dependent on the power mode, we can keep caches powered up
while the cpu is power gated
We can run cpu in several different voltages depending on the
workload. At the same time cache can operate on different
voltages (technology restrictions)
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9.1.2009
Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-Chip
Design”
Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Design Partitioning – critical path timing
Critical path – known in most designs
In case of ARM1176 CP through interfaces between CPU and caches
A rule of thumb: minimize the impact on the critical paths and do not
create any new ones
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Design Flow Overview - differences
Specification of the power intent
Creation of power domains during synthesis
State retention synthesis
Multi-voltage physical design partitioning
Multi-voltage power network synthesis
Power network analysis/validation
Multi-voltage placement optimization
Multi-voltage clock tree synthesis and optimization
Power route network verification
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Synthesis
Power intent – describes power domains and defines how power is
distributed to them (where logic components required; power switch
on/off). Can be captured through:
An explicit definition in the RTL:
hand instantiation of the power logic
HDL pragmas
Tool specific pragmas
Text file in a standard format, e.g. Unified Power Format (UPF)
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Synthesis - UPF
All the low power specific components e.g.: poower domains, isolation
cells insertion, retention registers insertion etc., defined in one file
Example of a power domain specification in the UPF
create_power_domain domain name
[-elements list] # indicates which elements are in domain
[-include scope] # the scope of a domain should be included
[-scope instance_name] # specifies the scope (instance) in which PD is created
UPF web links:
UPF standard :
http://www.unifiedpowerformat.com/images/UPF.v1.0_Standard.pdf
UPF quick reference guide:
http://www.unifiedpowerformat.com/images/UPF_Quick_Reference_Guide.pdf
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Synthesis – Recommendations
Define comprehensive power intent for a design (easily implementable
and verifiable)
Define power domains early
Isolation logic and retentaion as a part of a design - verification
... and synthesis. Should be taken as a integral part of the overall cost
function for the design
Control networks for always-on logic must be buffered using always-
on buffers
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Scan Synthesis
Problem: switching activity in scan mode can be much higher than in
normal operation (max power for the chip may be exceeded)
Additional isolation blocks might be required between power domain
outputs connecting to scan
Recommendations:
Minimize the number of scan chains crossing power domain interfaces
Scan chain reaordering – power domain aware
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Always-on Network Synthesis
Control signals from the power gating controller must remain alive during the
shutdown of certaing power domains
The network of buffers distributing these signals is reffered as always-on
network
Always-on network build of always-on buffers and inverters connected to
always-on power supply
In most EDA tools identifications of these networks performed automaticaly
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Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-Chip
Design”
Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Design Planning
Degradation of QoR by number of factors:
Reduced operating voltage for certain parts of the logic
Added delay introduced by LS and isolation cells
Increased IR drop accross switched networks in the power mesh
Increase congestion caused by the use switch cells and retention flops
Placement restrictions due to physicall bounded voltage areas
Physical design phase starts with determination of the overal topology
of the design
Location of inputs/outpus
Location of memory system and other hard IP
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Design Planning – Creating Voltage Areas
Optimizing the relative location and communication of the functional blocks
Avoiding extensive routing of the power busses
Iterative proces
Performance requirements and possible density as a figures of merit
Ensure proper isolation the voltage areas (guard band)
Splitting power domain into several voltage areas not recommended
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Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-Chip
Design”
Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Inrush Current Management
Power up sequence critical for inrush current
Buffered swithes
Daisy chaining
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Design Planning - Recommendations
Voltage areas should be gard banded
Placement optimization
Cells created during the optimization process must be placed in the
appropriate voltage are and connected to the correct power supply
Isolation cells and level shifters should be placed at the voltage area
boundary
Different switch topologies might be tested to determine to optimal
one
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Power Planning
Different power rails to different power domains
Minimizing the voltage drop acros the rails is the key issue
Book actually recomends using the automated power network
synthesis provided by EDA
Reducing noise between different power supply rails and cells within
same power domain by the insertion of the decoupling capacitors
Inrush current
Normal switching of the block
Impacto of decoupling capacitors on the performance
Latency and area penalty
Violation spots
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Clock Three Synthesis
The impact of the clock tree on the power consumption is significant
Clock signal passing through different voltage areas varies latancy
If clock path buffering and data path buffering are not well balanced
across voltage areas then skew managment is problematic
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Clock Three Synthesis
The impact of the clock tree on the power consumption is significant
Clock signal passing through different voltage areas varies latancy
If clock path buffering and data path buffering are not well balanced
across voltage areas then skew managment is problematic
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Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-Chip
Design”
Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Clock Three Synthesis cont.
EDA tools use bottom-up approach
Clock network constructed in each voltage area to minimize the skew
Low level clock tree structures are joint by the higher level trees to form overall clock
network for design
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9.1.2009
Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-Chip
Design”
Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Routing
Two options when the best route of the net from one part of a design to
another is accross one or many voltage areas
Rout the net through the voltage area(s) adding appropriate LS
Detour the route around the voltage area(s) to the destination
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9.1.2009
Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-Chip
Design”
Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Power Analysis
Power rail analysis
On determine drop spots, sizing the switch cells and power mesh is the
best approach
Checking the inrush current by performing extensive transient analysis
on the design
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Timing Analysis
Verify if our design works under all scenarios it was designed for
Specify these scenarios
Provide necessary libraries to perform analysis
It is recomended to leave a small window of uncertainity to handle
correctly variations in the resistances and capacitances arising from the
fabrication process
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Low Power Validation
Validation of the low power intent provided at the start of
implementation
Gate level logic simulation
Resets cleanly at startup
Can be placed into various sleep modes
Behave correctly during shutdown
Powers-up succesfully after shutdown
Equivalence checking
Rule-based methods
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Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4
Manufacturing Test
In most cases, design will be tested at nominal supply rail voltage
level, which will cose significantly higher power consumpion than
during normal operation
Possible thermal failures of design and package
Power consumption may lead to voltage drop – functional failures
Both functional and test modes need to be considered during the implementation
voltage scaling
Complexity of the design of the test (time vs fault coverage)
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