me mr is tor synthesis

Digital Logic Synthesis for Memristors

MemristorMemristor●One type of new emerging nano-devices●Memory-Resistor postulated by Leon Chua in 1971●First physical implementation found by HP in 2008

Memristor

Memristor in Digital Logic

●Threshold device– Crossing threshold switches the

resistance/conductance of the memristor– Information is stored in the resistive state

●Non-volatile resistance– No refresh needed

●Can switch in nano-seconds with pico-joule energy (cite HP paper)

➔Has the potential for high density, low power logic and memory circuits

Published synthesis methods1.1. Julien Borghetti, Julien Borghetti, Gregory S. Snider, Philip J. Kuekes, J. Joshua Yang, Duncan

R. Stewart, and R. Stanley Williams. R. Stanley Williams. /‘memristive/’ switches enable /‘stateful/’ logic operations via material implication. Nature, 464:873 –876, 4 2010.

2.2. A. Chattopadhyay and Z. RakosiA. Chattopadhyay and Z. Rakosi. Combinational logic synthesis for material implication. In VLSI and System-on-Chip (VLSISoC), 2011 IEEE/IFIP 19th International Conference on, pages 200 –203, Oct. 2011. Different assumptionsDifferent assumptions

3.3. E. Lehtonen and M. LaihoE. Lehtonen and M. Laiho. Stateful implication logic with memristors. In Nanoscale Architectures, 2009. NANOARCH ‘09. IEEE/ACM International Symposium on, pages 33 –36, July 2009.

4.4. E. Lehtonen, J.H. Poikonen, and M. Laiho. E. Lehtonen, J.H. Poikonen, and M. Laiho. Two memristors suffice to compute all boolean functions. Electronics Letters, 46(3):239 –240, 4 2010.

5.5. J.H. Poikonen, E. Lehtonen, and M. Laiho. J.H. Poikonen, E. Lehtonen, and M. Laiho. On synthesis of boolean expressions for memristive devices using sequential implication logic. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 31(7):1129 –1134, July 2012.

6.6. D.B. Strukov, A. Mishchenko, and R. Brayton, D.B. Strukov, A. Mishchenko, and R. Brayton, Maximum Throughput Logic Synthesis for Stateful Logic: A Case Study, preprint. Different assumptionsDifferent assumptions

Material ImplicationMaterial Implication●Conditional logic with multiple interpretations

– If p then q– q follows p– ...

●Paradox of entailment– An argument (p->q) is false, iff the premise (p) is

true and the conclusion (q) is false

p

qp qppq = q = p p q q

IMPLY Logic

●Two memristors can perform material implication with one pulse – IMPLY

●Consider memristors as a switch with two states – Ron, Roff

●Voltage drop over P affects voltage drop over Q

●Result will be stored in Q– Q is input and

output memristor

IMPLY Logic - Notes

●Explains the conditions for Q changing its state●Q is pre-set to “0” (low conductance / high

resistance)●Voltage level V_Rg determines voltage drop over Q●Only if P = “0” V_Rg remains low and allows Q to

change

Material Implication with Memristors

Material Implication - Notes● 5 pulses, 4 input patterns

●First two pulses to show initial input values of P and Q

●Third pulse performs operation (two pulses applied simultaneously to P and Q)

●Fourth and fifth pulses to read resulting values of P and Q

● Note different pulse amplitude during pulse three (V_set, V_cond)

Why are we interested in that?

●CMOS technology scaling is approaching limits●Main limitation in modern CPUs is heat

●2-terminal device of 10nm size– Allow much higher/denser device integration

●Switching between states can be done with pico Joule

Building NAND from IMPLY

●IMPLY & FALSE is a computationally complete set of operators

●2 input memristors and one work memristor can build NAND gate– Having NAND we are creating a link to known

logic synthesis algorithms

Memristors in digital logic

●IMPLY and FALSE is a complete set of operations to perform all boolean logic functions

●3 memristors can perform a NAND operation

p1p1

p2p2 p3p3

Two-input NAND needs three pulses

Examples of implication uses

((ab) 0) = (a’+b’)((ab) (ab)) = (a’+b’) + ab(0 ab) = (ab)(a b) = (a’+b)

ab a + b

a

ba + b

a0

ab ( a + b) = a * b

0

aa + b = (a * b)b

0

All these circuits assume that value of b already exists.If it does not exist, we need two inverters (from IMPLY) to create it.

ab a + b

a

ba + b

a0

ab ( a + b) = a * b

0

a

(a * b)

b0 0

All these circuits assume that value of b already exists.If it does not exist, we need two inverters (from IMPLY) to create it.

Now we assume Now we assume that all inputs that all inputs

must be created must be created with Stateful with Stateful

IMPLY technology IMPLY technology from scratch.from scratch.

NOT & NOT & OROR

NOT & ORNOT & ORNOT OR with two inputs

A

0

B

x

A

Bx

A

0x

A x

B

00

NOT

A

0x

A x

BC

A

0

NOT is a one WM NOT is a one WM gate gate

AA

B

2-input OR is a 2-input OR is a two WM gatetwo WM gate

AA0

B

X=A+BB0

0

A+BA+B

BB

00

BB

2-input OR2-input OR

AABB

00

AA00

00

NAND & AND

NAND NAND & AND& AND

NAND & AND

NAND

A

0

B

x

A

Bx

NAND & ANDNAND & AND

BC

A

0

00

2-input AND is a 2-input AND is a two ancilla gatetwo ancilla gate

2-input NAND is 2-input NAND is a one ancilla a one ancilla

gategate

0 NAND(a,b)

AND(a,b)

00

NAND & ANDNAND & AND

0

b

c

d

Working (memorizing) memristor (ba) =b’+a

(c(ba) c) = (c’+(b’+a)=(bc)’+a

(bcd)’+0

0

y

z

v

(yzv)’ + 0

0

Realization of a Sum Realization of a Sum of positive Productsof positive Products

bcd+yzv

Imply serves as inverter

NAND(b,c,d)

NAND(y,z,v)

1

2

1

2

Two Two Working Working MemristorsMemristors

SOPSOP

Inhibit gate Inhibit gate A * B’ = (A’ + B)’ 2 gates

BC

A

0

00

2-input INHIBIT 2-input INHIBIT is a two WM gateis a two WM gate

A’ A’ Two working bits

B’ B’

A’ + B

00A * B’ = (A’ + B)’

NOR NOR GatesGates

NORNORBC

A

A0 00

0

NOR is a two WM bit NOR is a two WM bit gategate

A A+B

B00

(A+B)’

EXOR EXOR GatesGates

EXOR = EXOR = 8 literals in NAND 8 literals in NAND = 8 IMPLY= 8 IMPLY

B

A

00

EXOR is a EXOR is a three WM gatethree WM gate

00

A’B + A B’

A’A’

A’A’

B’B’

BB

AA

AA A + B’A + B’

00 A’BA’B

00B’B’

BB B + A’B + A’00

SYNTHESIS WITH SYNTHESIS WITH EXORS WITH NO EXORS WITH NO

LIMIT ON LIMIT ON NUMBER OF NUMBER OF

ANCILLA BITSANCILLA BITS

B

A

00

00

A’B + A B’

A’A’

AAA + B’A + B’

00 A’BA’B

00 B’B’

BB B + A’B + A’00

C

00

00

A’B + A B’

A’A’

AAA + B’A + B’

00 A’BA’B

00 B’B’

BB B + A’B + A’00

First Working Memristor

Second Working Memristor

Third Working Memristor

Fourth Working Memristor

This circuit has 4 This circuit has 4 working working memristors and 16 memristors and 16 IMPLY gatesIMPLY gates

16 IMPLY gates, 4 WM16 IMPLY gates, 4 WM

B

A

00

00

A’B + A B’

A’A’

AA A + B’A + B’

00 A’BA’B

00 B’B’

BB B + A’B + A’00

MUXMUX

MUXMUXB

0

MUX is MUX is a three a three ancilla ancilla gategate

00

A

C

(AB)’(AB)’

AB + A’CAB + A’C

AA

A’A’

BB

CC

(A’C)’(A’C)’00

00A’A’

AA

(A+C’)’(A+C’)’

7 WM expected

Circuits from reversible gates versus circuits from memristor material

implications

SimilaritiesNo fanout

In-gate memory exists

DifferencesNo inverter

Different gates

Examples of Examples of typical multi-typical multi-input gatesinput gates

B

0

C

A

A A + B A + B + C = (ABC)

Realization of positive product Realization of positive product (negated) which is (negated) which is multi-input multi-input

NANDNAND

0

A A + B A + B + C

Realization of positive product Realization of positive product (negated) which is (negated) which is multi-input multi-input

ORORAA

BBCC

Area and DelayArea and Delay●Area

– In CMOS: number of gates– Memristive logic: number of input + work memristors

●Delay– In CMOS: number of logic levels– Memristive logic: number of gates + number of

FALSE operations

Our Understanding of Lehtonen’s Our Understanding of Lehtonen’s Algorithm: Algorithm: Synthesis with K-mapsSynthesis with K-maps

Synthesis with K-maps

21 IMPLY gates, 2 WM21 IMPLY gates, 2 WM

Variants of synthesis algorithms

1. Find all groups in every level (Lehtonen).

1. Find only groups corresponding to essential primes and secondary essential primes.

1. Find minimum SOP cover of F and SOP cover of F’ and use groups that correspond to primes from these covers.

1. Use cost heuristics related to best prime selection.

All primesSecondary essential primes in red

Secondary essential primes in red

Kernels of Primary and Secondary essential primes

0 0 0

00

All essential primes of F’ in red

0

All kernels of essential primes of F and F’

01 1

We take kernel of the first level (in red)

We do not take another kernel of the first level because it was not a kernel of an essential implicant

00

X

X

We invert the function

0

X

X

1

11

1

1 1

11

0 0

0

0

0

We select the group being kernel of essential prime of F’

0

X

X

1

11

1

1 1

11

0 0

0

0

0

Do not select this group

0

X

X

1

11

1

1 1

11

0 0

0

0

0

We select the group being kernel of essential prime of F’

0

X

X

1

11

1

1 1

11

0 0

0

0

0

Replace with don’t cares

0

X

X

1

1X

1

1 1

X1

0 0

0

0

0

We invert the function

0X

X

X

X

0X

X

X

X

We select the group being kernel of essential prime of F’

0

X

X

1

1

1

1 1

11

0 0

0

0

We invert the function

X

X

X

X

0X

X

X

X

We select the group being kernel of essential prime of F’

X

X

0

X

X

1

1

1

1 1

11

0 0

0

0

X

X

X

X

0

X

X

1

1

1

X X

1X

0 0

0

0

X

X

X

X

0X

X

X

X

X

X

We invert the function

X X

X

0X

X

X

X

X

X

X X

X

We select the group being kernel of essential prime of F’

0

X

X

1

1

1

X X

1X

0 X

X

0

X

X

X

X

We invert the function

0X

X

X

X

X

X

X X

X

We select the group being kernel of essential prime of F’

X

X

0

X

X

1

1

1

X X

1X

0 X

X

0

X

X

X

X

0

X

X

1

1

1

X X

1X

0 X

X

0

X

X

X

X

Groups selected

Number of levels does not count, number of pulses counts to cost

3 pulses each 4 pulses

2 pulses2 pulses 1 pulse

Our method replaces primes from minimal cover with bigger positive groups

1

0

Groups selected

0

1. We have more groups than in SOP2. But groups have less literals3. We have more inverters for layers4. We have no inverters for primes5. This tradeoff causes big differences between costs of SOP

and our method for various functions6. Interesting research topic

ABC and Automated Logic SynthesisABC and Automated Logic Synthesis

1. Can we use existing tools to perform synthesis?

1. How do we integrate memristor logic to these tools?

1. Are the results valid with respect to memristor logic specifics (area, delay)?

ABC

●From Alan Mishchenko, UC Berkeley●System for synthesis and verification of binary

sequential logic circuits●AIG based

Technology Mapping

IPMPLY in ABC

●Genlib file

●Technology Mapping

ABC Output● Delay is the number of gates + number of

memristor initializations

● Area is the number of input + work memristors– Cannot be controlled from ABC

● One issue that is special in memristor logic: Fanout

pq

p qppq = q = p p q q

NotationNotationp q

p q

Parallel Fanout

Green line – previous node will not be overwritten

Red line – previous node will be overwrittenComputing n9 first, overwrites n8Computing n10 first, overwrites n7

One node (n7 or n8) has to be copied/recomputed

Solving Parallel FanoutWhat is cheaper?

Copy or recompute?Which node is cheaper to recompute?

Copying might require one additional work memristor and two pulses

Recomputing n8 requires one pulseRecomputing n7 requires 4 pulses➔ Recompute n8

Post Processing ABC resultsPost Processing ABC results

●Fanout requires post processing●Two strategies:

– Store each value with fanout in an additional memristor (2 inverter)

– Recompute the whole sub-circuit that caused fanout

●Area/Delay trade-off●Fanout is increasing delay and

likely the area as well

Post Processing

ABC results

BenchmarksBenchmarks

For more results, comparison with other SOP and ESOP based methods see poster by Anika Raghuvanshi

Benchmarks - NotesBenchmarks - Notes● Pulse Count (Anika)

●Solution for minimum number of work memristors (minimum area)

●Follows similar approach as presented with the k-maps

●Pulse count = delay● Gate count

●Number of IMPLY gates as computed by ABC●Can contain fan-out that has to be post-processed●Is not area optimized (more than 2 work

memristors)● Pulse Count (ABC)

●Post processed to avoid harmful fan-out●Still not area optimized

ConclusionsConclusions1. Very little published on synthesis with IMPLY gates

1. Very little published on synthesis with memristors.

1. Although logic synthesis for memristors may seem similar to standard SOP or multi-level combinational synthesis, it is different because of assumption of minimal level number of Working Memristors?

2. We created methods to synthesize circuits with minimum number of working memristors

3. We created methods to synthesize circuits with small but not minimal (3, 4) working memristors.

1. Research question: “how important is this assumption for future memristor technologies?”

Future worksFuture works1. Synthesize for given fixed number of working

memristors

2. Compare various synthesis methods:1. SOP2. ESOP3. TANT4. NAND Tree5. Bi-decomposition6. Ashenhurst-Curtis decomposition

3. Analyze tradeoffs between various methods for various types of functions (symmetric, unate, linear, self-dual, etc).

Future worksFuture works1. Synthesis of pipelined, systolic circuits

2. Synthesis of Finite State Machines and sequential circuits built from blocks.

3. Fuzzy and multiple-valued circuits.

4. Exact synthesis

The important characteristic of a memristor is shown in the graph in Figure 2(b), where the steep curve shows the low resistance, as shown by line AB (the ‘on’ state of the memristor) and the flatter curve shows the high resistance (the ‘off’ state of the memristor) as shown by line interval CD.

Memristor’s state described by interval AB can also be called as ‘closed’ or in binary state definitions as ‘1’ or ‘true’.

Similarly, the state described by line interval CD can also be called ‘open’ or in binary state definitions as ‘0’ or ‘false’.

When voltage is increased beyond certain point, shown as Vopen, the state of the memristor changes from closed to open (transition point B to C in the diagram).

Now as the voltage is decreased and goes through the zero point, the resistance stays the same until the negative voltage exceeds Vclose.

At this point the state changes from open to closed (shown by transition from point D to A).

If the voltage remains between VClose and VOpen, then there is no change in the state of the memristor.

The change from state open to closed and closed to open, allows memristor to act as a binary switch.

And the fact that the state remains the same when the voltage is between Vopen and Vclose provides the important ‘memory’ property.

Even when the voltage is removed, the state will remain the same, and is remembered.

Observe that while a transistor is a three-terminal device, a memristor is only a two-terminal device which simplifies the layout.

Figure 4(a) shows the circuit when the state of memristor P is ‘0’ (open).

P has a high resistance, and can be thought of as disconnected, which implies that the voltage across grounding resistor is zero.

This means that the voltage across the memristor Q is equivalent to Vset.

As shown in Figure 2(b), Vset is greater that Vclose.

The high voltage causes the state of Q to become ‘1’ regardless of Q’s original state (‘0’ or ‘1’).

Figure 4(b) shows the circuit when the state of memristor P is ‘1’.

Figure 4: Workings of IMPLY gate using two Memristors. (a) Output when P=0, (b) Output when P=1

Now P has a low resistance, and can be thought of as a wire, which implies that the voltage across the grounding resistor is now the same as Vcond, the voltage applied at P input.

This means that the voltage across Q is equivalent to Vset-Vcond.

Refering to Figure 2(b) again, the magnitude of Vset-Vcond is less than Vclose, and is not enough to switch the state of Q irrespective of its previous state.

This means that if Q’s state was ‘0’, it will remain ‘0’. If the state was ‘1’, it will remain ‘1’.

Figure 4(b) shows the circuit when the state of memristor P is ‘1’.

Logic Synthesis for Memristors

●Find all product implicants with positive literals only

●Replace with don't care

●Invert●Repeat until

all '1' covered

examples

((abc)’+ (ab))’ + (bcd) =((a’ + b’ + c’) + ab)’ + bcd =(abc) * (ab)’ + bcd =(abc) * (a’ + b’) + bcd =(b’c) + bcd

c, Experimentaldirect-current current–voltage switching characteristics (four-probemethod).

Traces b–f are offset.

Trace a shows a closed-to-open transition,trace b shows stability and trace c shows an open-to-closed transition.

Traces d–f repeat this cycle.

d, Switch toggling by pulsed voltages (2 ms long; VSET525V and VCLEAR519 V). Non-destructive reads at 20.2V test the switch state.

• Figure 2 Illustration of the IMP operation for the four input values of p and q.

• a, IMP is performed by • two simultaneous voltage pulses, VCOND

and VSET, • applied to switches P and Q,

respectively, • to execute conditional toggling on

switch Q depending on the state of switch P.

• b, The truth table for

the operation q’ q’ p p IMP IMP qq. .

p q

Figure 2c, The blue and red curves show the voltagesapplied and the absolute value of the currents read at junctions P and Qbefore and after the IMP voltage pulses.

The measured low- and high-currentvalues reproduce the IMP truth table.