microblaze for linux howto - saanlima for linux howto.pdf · 14. once the top-level hdl source is...

Microblaze for Linux Howto

This tutorial shows how to create a Microblaze system for Linux using Xilinx XPS on Windows.

The design is targeting the Spartan-6 Pipistello LX45 development board using ISE 14.4.

The first step is to download and install the Pipistrello XBD board description files for EDK.

Download the zip file from here: http://www.saanlima.com/download/pipistrello-EDK-

board/Saanlima.zip. Unzip the file and copy the Saanlima directory to

C:\Xilinx\14.4\ISE_DS\EDK\board\

The next step is to create the hardware platform using the Base System Builder. The system

will include a timer, a UART, an SPI controller for Flash memory access, a GPIO controller for the

LEDs, external LPDDR memory, and internal memory to store the ELF bootloader application.

1. Launch Xilinx ISE Design Suite 14.4 and create a new project: File > New Project…

2. Set the project location to a folder with no spaces in the name or path (SDK don’t like

that). Click Next

3. Select Pipistrello LX45 as the Evaluation Development Board and set Verilog or VHDL as

the Preferred Language. Click Next

4. Click Finish

5. Go to Project > New Source… then select Embedded Processor. Type mb_system for the

File name. Click Next. Click Finish.

6. Xilinx Platform Studio (XPS) will start up with a blank project and ask if you want to use

the BSB Wizard. Click Yes.

7. The BSB Wizard will open. Select AXI System and click OK.

8. Base System Builder – AXI flow will open.

Change Board Revision to 2.0 and click Next.

9. Next is the processor configuration. Leave the processor frequency at 100 MHz. Set

local memory size to 32 KB and instruction and data Cache size to 16KB. Add one

instance of axi_timer and enable interrupt. Change the baud rate for the USB_Uart to

115200 and enable interrupt. Enable interrupt for SPI_SD. Click Finish.

10. The system will now be generated.

11. Double-click on microblaze_0, this will bring up the Microblaze Configuration Wizard.

Click on Linux with MMU, this will reconfigure the processor for Linux, then click OK

12. Click on the Ports tab, expand the External Ports section and change SPI_FLASH_HOLDn

and SPI_FLASH_Wn connection to net_vcc. Then close the XPS window.

13. In ISE Project Navigator, double-click on Generate Top HDL Source

14. Once the top-level HDL source is built, expand the mb_system_top section in the

Hierarchy view, click on mb_system_i and then double-click on Export Hardware Design

To SDK with Bitstream in the Processes view. This will build the system, generate the

bit-file and launch SDK. (Get some coffee, this will take a few minutes to finish.)

15. SDK will ask you select a Workspace. Create the Workspace at the project root and click

OK.

16. SDK will open and show the system information contained in the file system.xml.

17. Click on File > New > Board Support Package. Use the default settings and click Finish.

18. The Board Support Package Settings popup window will open. Click OK.

19. Click on File > New > Application Project. Give the project a name (HelloWorld) and

change the Board Support Package to standalone_bsp_0. Click Next.

20. Select the Hello World template and click Finish.

21. Next step is to change the linker script to place the code in on-chip block-ram memory

instead of LPDDR. Right-click on HelloWorld to bring up a menu and click on Generate

Linker Script. Place the code and data in

microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl. Click Generate. Click Yes to

overwrite the existing linker script.

22. Open up a terminal window (putty or similar) using the serial com-port of the Pipistrello,

and set the baud rate to 115200 baud.

23. Click on the Program FPGA ikon (red arrow + green squares)

24. In the Program FPGA popup window, change the Software Configuration to load

HelloWorld.elf. Click Program. This will download the system bit-file with the

HelloWorld code preloaded in block-ram and the board will start executing the program.

25. Success!

26. Repeat steps 19 – 24 but select the template Peripheral Tests instead in step 20.

27. Repeat steps 19 – 24 but select the template Memory Tests instead in step 20.