mips datapath - university of richmondmips steps • get an instruction from memory using the...
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MIPS Datapath
CMSC 301Prof Szajda
Goal
• Build an architecture to support the following instructionsw Arithmetic: add, sub, addi, sltw Memory references: lw, sww Branches: j, beq
Process
1) Design basic framework that is needed by all instructions
2) Build a computer for each operation individually
3) Add MUXs to choose between different operations
4) Add control signals to control the MUXs
MIPS Steps
• Get an instruction from memory using the Program Counter (PC)
• Read one or two registers each instructionw One register: addi, lww Two registers: add, sub, slt, sw, beq
• All instructions use ALU after reading regs• Some instructions also access Memory• Write result to Register file
Get instruction
from memory
Framework
Read from
register file
Get instruction
from memory
Framework
Read from
register file
Use ALU Get instruction
from memory
Framework
Read from
register file
Use ALU Get instruction
from memory
Access memory
Framework
Read from
register file
Use ALU Get instruction
from memory
Access memory
Write register file
Framework
Get Instruction
Where do we store instructions?
Get Instruction
Instruction Memory
Address Data
Where do we store instructions?
Memory
Get Instruction
Instruction Memory
Address Data
How do we know at what address to fetch instruction?
Get Instruction
Instruction Memory
Program Counter (PC)
Data
How do we know at what address to fetch instruction?
Program Counter
Get Instruction
Instruction Memory
Program Counter (PC)
Data
What do we end up with?
Get Instruction
Instruction Memory
Program Counter (PC)
Instruction
What do we end up with?
Instruction
Get Instruction
Instruction Memory
Program Counter (PC)
Instruction
What happens to the PC each instruction?
Get Instruction
Instruction Memory
Program Counter (PC)
Instruction
What happens to the PC each instruction?
Increment by 4B
4
Read from
register file
Use ALU Get instruction
from memory
Write register file
“Add” Instruction
Read from
register file
Use ALU
Write register file
Read Addr Out Data
Instruction Memory
PC
Inst
4
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5
“Add” Instruction
Use ALU
“Add” Instruction
Write register file
Read Addr Out Data
Instruction Memory
PC
Inst
4
Register File
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How many
registers do we need to read?
Use ALU
“Add” Instruction
Write register file
Read Addr Out Data
Instruction Memory
PC
Inst
4
Register File
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How many
registers do we need to read?
2
Use ALU
“Add” Instruction
Write register file
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5
What part of instruction tells us the
register number?
Use ALU
“Add” Instruction
Write register file
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5
What part of instruction tells us the
register number? rs & rt
“Add” Instruction
op/fun rs rt rd imm
Write register file
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5
“Add” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destdata
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5
How do we know which register to
write?
“Add” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5
How do we know which register to
write? rd
“Add” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5
What happens if instruction reads and writes same register?
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 3 0 32 # $3 <- $3 + $5
What happens if instruction reads and writes same register?
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt rd shamt funct # meaning add 3 5 3 0 32 # $3 <- $3 + $5
What would happen if we allowed write to occur at any time?Clock is dependent on longest path (lw)Quick operations may loop twice through machine, getting incorrect result.
Reading/Write Registers
• When does register get written?w At the end of the clock cyclew Edge-triggered circuits
“Addi” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6 What
registers do we read?
“Addi” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6 What
registers do we read?
rs
“Addi” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6 Where do
we get the second input?
“Addi” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
16 bits
32 bits
Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6 Where do we
get the second input?
imm (16 bits)
Sign Extension
• How do we go from 16-bit number to 32-bit number?
• How about 4-bit to 8-bit.w 0111 = 7 = 00000111w 1110 = -2 = 11111110
• Take the top bit and copy it to all the other bits
“Addi” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
16 32 Sign Ext
Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6 Sign extend
immediate value
“Addi” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
16 32 Sign Ext
Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6
How do we know which register to
write?
“Addi” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
16 32 Sign Ext
Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6
How do we know which register to
write? rt
Putting them Together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
16 32 Sign Ext
Putting them Together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
16 32 Sign Ext
Two wires to the same input
Putting them Together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
16 32 Sign Ext
Two wires to the same input Add MUXs
Putting them Together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
16 32 Sign Ext
What determines
which to take?
Putting them Together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
16 32 Sign Ext
What determines
which to take? Op/Func code
Control Unit
RegDest
ALUSrc
ALUOp
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Addr Out Data
Data Memory
In Data
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Addr Out Data
Data Memory
In Data
How many source regs? What part of instruction?
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Addr Out Data
Data Memory
In Data
How many source regs? 1 What part of instruction? rs
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Addr Out Data
Data Memory
In Data
Where do we get the second input?
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Addr Out Data
Data Memory
In Data
16 32 Sign Ext
Where do we get the second input? Sign extended imm
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
16 32 Sign Ext
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
What do we do with the ALU output?
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Addr Out Data
Data Memory
In Data
16 32 Sign Ext
What do we do with the ALU output? Memory Address
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Where do we write the result?
Load Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning lw $5,8($3) 3 5 8 # $5 <- M[$3 + 8]
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Where do we write the result?
rt
Store Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Store Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Addr Out Data
Data Memory
In Data
Address calculation identical to load word
32 Sign Ext
16
Store Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Is $5 read or written?
Which register?
Store Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Is $5 read or written? read
Which register?
Store Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Is $5 read or written? read
Which register? rt
Store Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
What do we do with the value?
Store Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
What do we do with the value?
In Data for memory
Store Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
What do we do with OutData?
Store Operation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning sw $5,8($3) 3 5 8 # M[$3 + 8] <- $5
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
What do we do with OutData?
Nothing.
Putting them together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Control Unit
ALUOp
Putting them together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Control Unit
ALUOp
What do we NOT want it to do for a
store?
Putting them together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Control Unit
ALUOp
What do we NOT want it to do for a store? Write to
destreg
RegWrite
Putting them together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Control Unit
ALUOp
Do we want it to read or write?
RegWrite
Putting them together
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
Control Unit
ALUOp
Do we want it to read or write? Depends on
opcode
RegWrite
MemRd
MemWr
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
What operation?
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
What operation? Subtraction,
compared with 0
Zero?
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
How do we go anywhere?
Zero?
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
How do we go anywhere?
Change the PC
Zero?
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
Where do we want to go?
Zero?
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
Where do we want to go? Advance
imm instructions
Zero?
32 Sign Ext
16
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
Where do we want to go? Advance
imm instructions
Zero?
32 Sign Ext
16 But the PC is in
bytes.
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
Zero?
32 Sign Ext
16
<< 2
But the PC is in bytes. PC = (PC + 4)+ Imm<<2
Where do we want to go? Advance imm
instructions
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
Zero?
32 Sign Ext
16
<< 2
How do we use our Zero bit?
“beq” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation rs rt imm # meaning beq $3,$5,lp 3 5 6 # if ($3 == $5) goto lp
Zero?
32 Sign Ext
16
<< 2
How do we use our Zero bit?
Choose between PC+4 and PC+4+
(Imm<<2)
“j” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation Target address # meaning j loop 0x0174837 # goto loop
Where do we go?
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation Target address # meaning j loop 0x0174837 # goto loop
Where do we go? To this absolute
address
“j” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation Target address # meaning j loop 0x0174837 # goto loop
Where do we go? To this absolute
address But this is only
______ bits, when the PC is _____
bits.
“j” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation Target address # meaning j loop 0x0174837 # goto loop
Where do we go? To this absolute
address But this is only 26 bits, when the PC is 32 bits.
“j” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation Target address # meaning j loop 0x0174837 # goto loop
Where do we go? To this absolute
address But this is only 26 bits, when the PC is 32 bits. Shift left, Concatenate
PC’s upper bits
“j” Instruction
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Operation Target address # meaning j loop 0x0174837 # goto loop
But this is only 26 bits, when the PC is 32 bits. Shift left, Concatenate
current PC’s upper bits
“j” Instruction
4 bits
26 bits
<< 2
28 bits
The Whole Shebang
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
<< 2
<< 2
Control Unit
• Set of control line values cause appropriate actions to be taken at each step
• Finite state machine determines what needs to be done at each stepw Fetchw Decodew Executew Memoryw Writeback
ACTIONS DEPEND ON
OPCODE
Single Cycle Latency
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
<< 2
<< 2
Time Diagram
Cycle Time
• Not all instructions must go through all stepsw add doesn’t need to go to memory
• Single long clock cycle makes add take as long as load
• Can we change this?w Break single instruction execution into
small execution steps
Five Cycle Implementation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
<< 2
<< 2
Five Cycle Implementation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
<< 2
<< 2
FETCH
Five Cycle Implementation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
<< 2
<< 2
DECODE
Five Cycle Implementation
EXECUTE
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
<< 2
<< 2
Five Cycle Implementation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
<< 2
<< 2
MEMORY
Five Cycle Implementation
Read Addr Out Data
Instruction Memory
PC
Inst
4
src1 src1data
src2 src2data Register File
destreg
destdata
op/fun rs rt rd imm
Addr Out Data
Data Memory
In Data
32 Sign Ext
16
<< 2
<< 2
WRITEBACK
How Many Cycles For:
• add• sw• lw• blt• j
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