mixed-signal neuromorphic vlsi devices for spiking neural ... · ning qiao neuromorphic cognitive...

Ning QiaoInstitute of Neuroinformatics

University of Zurich and ETH Zurich

Jun 20, 2018ADAC6 Workshop

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Mixed-signal neuromorphic VLSI devices for spiking neural network

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Outlines

! Brain inspired computing

! Neuromorphic engineering! Analog synapse and neuron circuits

! Multi-core Neuromorphic architectures

! Applications

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l In 2017 > 10 zettabytes of data were produced.

l IT infrastructures and consumer electronics absorbed > 10% of the global electricity supply.

l By 2025, over 50 billion of Internet-of-Things (IoT) devices will be interconnected.

l Over 180 zettabytes of data will be generated annually, potentially leading to a consumption of one-fifth of global electricity.

The cost of current computing technologiesis not sustainable

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Current trends in computing HWs

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Brain-Inspired compuBng

1mg weight1mm3 volume960’000 neurons10e-15 J/spike<100 uW

l Slow, noisy and variable processing elements

l Massively parallel distributed computation,

local connectivity

l Real-time interaction with the environment

l Complex spatio-temporal pattern recognitionl Foraging, navigation, language, and social

behavior

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Neuromorphic Compu?ng vs. Neuromorphic Engineering

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Current trends in neuromorphic processorsNot so radically different aCer-all (not solving the von Neumann boGleneck problem)

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Current trends in neuromorphic processorsNot so radically different aCer-all (not solving the von Neumann boGleneck problem)

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“Listen to the silicon” (original approach)Mixed-signal analog/digital neuromorphic systems

! Analog/digital computation, digital asynchronous

communication.

! Directly emulate the physics of neural systems.

! Massively parallel collections of non-linear circuits.

! Realistic neural and synaptic dynamics

! Distributed memory

! Co-localized memory and computation

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Channel current-voltage rela3onships

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Analog circuitsDirect emula2on of synap2c dynamics

[Bartolozzi and Indiveri, 2007]

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Analog circuitsDirect emulaCon of neuron dynamics

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Spike-based plas3city VLSI implementa3on

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Cor3cal networks: a high degree of clustering

Pyramidal Cell of Layer 3 of Cat Visual Cortex. Dendrites (Green), Axon (Red), Clusters of Boutons (Black) in Layer 3 and 5. Scale bar, 500 µm

[R.J. Douglas and K.A.C. Martin, Neuron, 2007] [Moradi and Indiveri 2014]

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! Two-stage + 2D tree + 2D mesh multi-cast routing schemes using both source-address and destination-address encoding.

! Fully asynchronous hierarchical routers for intra-core (R1), inter-core (R2) and inter-chip (R3) connectivity.

! Embedded asynchronous CAM and SRAM cells distributed across and within cores.

Memory opAmized mulA-core neural architectureHierarchical rouAng with heterogeneous memory structures

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Co-localized memory and computationFD-SOI design, ready for beyond CMOS technology

• Multiple parallel I/O pathways• Multiple distributed asynchronous SRAM

LUTs• Distributed multi-bit TCAM cells• Capacitors for state dynamics and learning

• Ideal for integration with (binary) resistive memories

• Ideal for integration with (learning) memristive devices

• Ideal for integration in 3D VLSI technology

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Latest NP chip specs

A large-scale, multi-core, neuromorphic processor DynapSEL in 28 nm FDSOI, is reported in ISSCC 2018

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Neural dynamicswith appropriate 3me constants

• Radically different from von Neumann architectures.

• Co-localized memory and computation.• No virtual time (time represents itself).• Data/event driven computation.

Paradigm shift

• For interacting with the environment in real-time.• Inherently synchronized with the real-world “natural” events.• To process “natural” sensory signals efficiently (low bandwidth/power).

“Slow” (biologically plausible) time constants

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Event-based convolutional network

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Real-Cme autonomous behaving agents

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Connecting neuromorphic processors to neuromorphicsensors and robots

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Hardware preliminary (state-of-the-art) results

N0 N

1

SOURCE NEURONS

INPUT SIGNAL

RESERVOIRNEURONS

OUTPUT LAYER

INPUT SIGNAL SHAPE

RESERVOIR RASTER PLOT

OUT NEURONS PREDICTED ACTIVITY

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Distributed ArDficial Intelligence

Autonomoussensory-motor systems

embedded systems &emerging memory technologies

Brain Machine Interfaces & prosthetics

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Team Work: InsCtute of NeuroinformaCcs

• Ning Qiao (INI)• Yulia Sandamirskaya (INI)• Lorenz Mu ̈ller (INI)• Melika Payvand (INI)• Elisa Donati (INI)• Dongchen Liang (INI)• Raphaela Kreise (INI)• Moritz Milde (INI)• Marc Osswald (inSightness)

• Dora Sumislawska (GeorgiaTech, USA)• Fabio Stefanini (Columbia Univ., USA)• Jonathan Binas (Univ. Montreal, CA)• Emre Neftci (UC Irvine, USA)• Saber Moradi (Yale, USA)• Hesham Mostafa (UCSD, USA)• Chiara Bartolozzi (IIT, Italy)• Elisabetta Chicca (Univ. Bielefeld, DE)• Stefano Fusi (Columbia Univ., USA)

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Technology-transfer effort to commercialize

• Dr. Ning Qiao• Prof. Giacomo Indiveri• Dr. Kynan Eng• Dr. Dylan Muir• Dr. Sadique Sheik• Dr. Qian Liu• Felix Bauer• Carsten Nielsen• Ole Richter• Anita Tuomi

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The end

Thank you for your attention

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Spiking Neuron Network (SNN)

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Spiking Neuron Network (SNN)

Communication Computation Learning

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• No I/O bottleneck• No memory bottleneck

Intel i7-4960X DYNAP-SEL

Co-localized memory and computationFD-SOI design, ready for beyond CMOS technology

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A closed-loop bi-direcEonal BMI