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University of ŽilinaFaculty of Management Science and Informatics
Modelling of massive memristive networks
Dissertation Thesis
Registration number: 28360020143002
Study program: Applied informatics
Affiliation : Faculty of Management Science and Informatics,
Department of InfoComm networks,
University of Žilina
Supervisor : prof. Ing. Martin Klimo, PhD.
Co-Supervisor : Prof. Dr.-Ing. habil. Peter Husar
Žilina, 2014urn:nbn:de:gbv:ilm1-2014000308 Ing. Milan Frátrik
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Annotation
Type of the work : Dissertation
Academic year : 2013/2014
Title of the work : Modelling of massive memristive networks
Author : Ing. Milan Frátrik
Supervisor : prof. Ing. Martin Klimo, PhD.
Co-Supervisor : Prof. Dr.-Ing. habil. Peter Husar
Language : English
Number of pages : 141
Number of figures : 73
Number of tables : 11
Number of references: 117
Keywords : memristor, comparator, spice, simulation, sorting
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Acknowledgments
First of all, I would like to thank my supervisor prof. Ing. Martin Klimo, PhD.for the support and helpful ideas. Besides my supervisor, I would like to thank toDoc. MSc. Ondrej Šuch, PhD. from the Research center of University of Žilina forfruitful discussions and ideas.
My thanks goes also to Prof. Dr.-Ing. habil. Peter Husar from the Institute ofBiomedical Engineering and Informatics, TU Ilmenau for offering me an internshipand to the people I met there, namely to Dr.-Ing. Adam Williamson and Dipl.-Wirtsch.-Ing. Lars Hiller for development of the TiO sample and introducing me tothe measurements. I would also like to thank Eike Linn from RTWH Aachen forthe development and shipping of the TaO sample.
I am thankful to Ing. Karol Frölich, DrSc., Ing. Peter Jančovič and Ing. MilanŤapajna, PhD. from Slovak Academy of Science, Institute of Electrical Engineeringfor the measurement possibilities in their institution and helpful support.
Last but not least my thanks goes to PhD. students at the department for help-fulness and friendship namely Iveta, Lucie, Renáta, Michal, Jozef, Števo, Stano andalso other colleagues at the department.
Also, I would like to thank my friends Michal, Lukáš, Maťo and finally my familyand my Zuzka for the patience and support during the whole time.
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Statutory declaration
I herewith formally declare that I have written the submitted dissertation indepen-dently. I did not use any outside support except for the quoted literature and othersources mentioned in the dissertation.
In Žilina, 12. April 2014 Ing. Milan Frátrik
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Abstract
Milan Frátrik: Modelling of massive memristive networks (Dissertation thesis)– The University of Žilina, Faculty of Management Science and Informatics, De-partment of InfoComm Networks – Supervisor: prof. Ing. Martin Klimo, PhD.– Qualification level: Doctor of Philosophy in Applied Informatics – EDIS Žilina,April 2014 - 141 pages.
This thesis deals with the problem of modelling memristor and memristive net-works. Memristors offer a variety of possible applications, starting at storage devicesup to neuromorphic applications. A memristor based sorting circuit is proposed inthis thesis. The simulation of the network starts from the basic elements, namelythe comparators. The functionality and behaviour is modelled using a non-lineardynamic memristor model. Sorting is one of the key subroutines required by In-duced Ordered Weighted Averages method (IOWA). IOWA can be used as a speechrecognition method, which is an ongoing research area at our department.Keywords: memristor, comparator, spice, simulation, sorting
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Abstrakt
Milan Frátrik: Modelovanie rozsiahlých memristívnych sietí (dizertačná práca)– Žilinská univerzita v Žiline, Fakulta riadenia a informatiky, Katedra informačnýchsietí – Školiteľ: prof. Ing. Martin Klimo, PhD. – Stupeň odbornej kvalifikácie:philosophiae doctor v odbore Aplikovaná informatika - EDIS Žilina, apríl 2014 - 141pages.
Táto dizertačná práca sa zaoberá problematikou modelovania memristorov amemristorových sietí. Memristory ponúkajú širokú škálu možných aplikácií odjednoduchých pamätí až po neuromorfné aplikácie. V tejto práci je predstavenýnový, doposiaľ neopísaný aparát slúžiaci na triedenie vstupných napätí. Navrhnutýaparát je simulovaný od základného stavebného prvku – komparátora. Jeho funkčnosťje modelovaná využitím nelineárneho dynamického modelu memristora. Triedeniepredstavuje jednu zo základných operácií používaných v metóde vážených priemerov.Táto metóda môže byť použitá na rozpoznávanie reči, čím pokračuje výskum na ka-tedre v oblasti analýzy reči.Kľúčové slová: memristor, komparátor, spice, simulácia, triedenie
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Contents
Introduction 25
Objectives 27
1 Current state 291.1 Electrical elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.1.1 Passive elements . . . . . . . . . . . . . . . . . . . . . . . . . 291.1.2 Active elements . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.2 Interrelation of electrical elements . . . . . . . . . . . . . . . . . . . . 321.3 Memristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3.1 Memristive system . . . . . . . . . . . . . . . . . . . . . . . . 341.3.2 Possible applications . . . . . . . . . . . . . . . . . . . . . . . 35
1.4 Resistive switching mechanism in thin-film devices . . . . . . . . . . . 361.4.1 Types of resistive switching . . . . . . . . . . . . . . . . . . . 38
1.4.1.1 Electrochemical Metallization Memory . . . . . . . . 391.4.1.2 Valence Change Memory . . . . . . . . . . . . . . . . 401.4.1.3 Thermochemical memory . . . . . . . . . . . . . . . 41
1.5 Memristor models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421.5.1 Linear ion drift . . . . . . . . . . . . . . . . . . . . . . . . . . 421.5.2 Linear ion drift window functions . . . . . . . . . . . . . . . . 451.5.3 Simmons Tunnel Barrier Model . . . . . . . . . . . . . . . . . 471.5.4 TEAM model . . . . . . . . . . . . . . . . . . . . . . . . . . . 481.5.5 Exponential model . . . . . . . . . . . . . . . . . . . . . . . . 501.5.6 WOx model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511.5.7 TaOx model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.6 Numerical methods in circuit analysis . . . . . . . . . . . . . . . . . . 551.6.1 ODE solver algorithms . . . . . . . . . . . . . . . . . . . . . . 55
1.6.1.1 Runge-Kutta family methods . . . . . . . . . . . . . 571.6.1.2 Linear multistep methods . . . . . . . . . . . . . . . 58
1.6.2 Root-finding algorithms . . . . . . . . . . . . . . . . . . . . . 581.6.2.1 Newton-Raphson method . . . . . . . . . . . . . . . 59
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1.7 Electrical network analysis methods . . . . . . . . . . . . . . . . . . . 601.7.1 Kirchhoff’s current law . . . . . . . . . . . . . . . . . . . . . . 611.7.2 Kirchhoff’s voltage law . . . . . . . . . . . . . . . . . . . . . . 611.7.3 Sparse tableau analysis . . . . . . . . . . . . . . . . . . . . . . 611.7.4 Modified nodal analysis . . . . . . . . . . . . . . . . . . . . . . 63
1.7.4.1 Non-linear elements using MNA . . . . . . . . . . . . 641.8 Circuit simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.8.1 SPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661.8.1.1 Algorithm overview . . . . . . . . . . . . . . . . . . . 661.8.1.2 Parallelization . . . . . . . . . . . . . . . . . . . . . 68
1.9 Logic circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681.9.1 Boolean logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.9.1.1 Boolean algebra . . . . . . . . . . . . . . . . . . . . . 681.9.1.2 Memristor based implication . . . . . . . . . . . . . . 70
1.9.2 Many-valued logic . . . . . . . . . . . . . . . . . . . . . . . . . 721.9.3 Fuzzy logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
1.9.3.1 Memristor based fuzzy logic . . . . . . . . . . . . . . 74
2 Solutions specification and methods of examination 752.1 Continuity of previous research . . . . . . . . . . . . . . . . . . . . . 752.2 Experimental methods . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.2.1 TiO sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772.2.1.1 Sample description . . . . . . . . . . . . . . . . . . . 772.2.1.2 Measurements . . . . . . . . . . . . . . . . . . . . . . 78
2.2.2 TaO sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782.2.2.1 Sample production . . . . . . . . . . . . . . . . . . . 782.2.2.2 Measurements . . . . . . . . . . . . . . . . . . . . . . 79
2.3 Simulation methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802.3.1 Simulation program . . . . . . . . . . . . . . . . . . . . . . . . 80
2.3.1.1 Used technologies . . . . . . . . . . . . . . . . . . . . 832.3.1.2 User interface . . . . . . . . . . . . . . . . . . . . . . 83
2.3.2 Comparison of the method to SPICE . . . . . . . . . . . . . . 842.3.3 ODE comparison . . . . . . . . . . . . . . . . . . . . . . . . . 87
3 Achieved results 893.1 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.1.1 TiO sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893.1.1.1 Single structures . . . . . . . . . . . . . . . . . . . . 893.1.1.2 Double structures . . . . . . . . . . . . . . . . . . . . 91
3.1.2 TaO sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923.1.2.1 Single structures . . . . . . . . . . . . . . . . . . . . 92
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3.1.2.2 Double structures . . . . . . . . . . . . . . . . . . . . 943.1.3 Single V-I double structures . . . . . . . . . . . . . . . . . . . 97
3.2 Modelling of a single memristor . . . . . . . . . . . . . . . . . . . . . 993.2.1 Fitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.3 Multiple memristors . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033.3.1 Minimum and maximum functions . . . . . . . . . . . . . . . 103
3.3.1.1 Multiple inputs . . . . . . . . . . . . . . . . . . . . . 1033.3.2 Memristor based comparator . . . . . . . . . . . . . . . . . . . 1063.3.3 Argmin and Argmax simulation . . . . . . . . . . . . . . . . . 107
3.4 Sorting circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083.4.1 Sorting networks . . . . . . . . . . . . . . . . . . . . . . . . . 1093.4.2 Implementation using memristors . . . . . . . . . . . . . . . . 1103.4.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4 Summary 1174.1 Contribution of this thesis . . . . . . . . . . . . . . . . . . . . . . . . 1174.2 Future research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184.3 Published papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.3.1 In print papers . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Bibliography 121
Appendices 133
A Sorting networks 135A.1 Odd-even transposition sort . . . . . . . . . . . . . . . . . . . . . . . 135A.2 Batcher odd-even merge sort . . . . . . . . . . . . . . . . . . . . . . . 136
B UML diagram 137
C Compact Disc 141
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List of Figures
1.1 Schematic symbol for a linear and a non-linear resistor . . . . . . . . 301.2 Schematic symbol for a linear capacitor . . . . . . . . . . . . . . . . . 311.3 Schematic symbol for a linear inductor . . . . . . . . . . . . . . . . . 311.4 Schematic symbols for independent sources . . . . . . . . . . . . . . . 321.5 The three fundamental two-terminal circuit elements . . . . . . . . . 331.6 A memristor schematic symbol . . . . . . . . . . . . . . . . . . . . . . 341.7 An analytical pinched hysteresis loop . . . . . . . . . . . . . . . . . . 351.8 Sketches of resistive switching . . . . . . . . . . . . . . . . . . . . . . 381.9 Different switching stages in ECM (Ag/Ge-Se/Pt) . . . . . . . . . . . 391.10 Different switching stages in an VCM . . . . . . . . . . . . . . . . . . 401.11 Common switching behaviours in VCM . . . . . . . . . . . . . . . . . 411.12 Different switching stages in an TCM . . . . . . . . . . . . . . . . . . 421.13 Linear ion drift model . . . . . . . . . . . . . . . . . . . . . . . . . . 431.14 Linear ion drift model behaviour . . . . . . . . . . . . . . . . . . . . . 441.15 The Linear ion drift SPICE model . . . . . . . . . . . . . . . . . . . . 451.16 Window functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461.17 Simmons tunnel barrier model inner structure . . . . . . . . . . . . . 471.18 Simulation of the Simmons tunnel barrier . . . . . . . . . . . . . . . . 491.19 WOx model inner structure . . . . . . . . . . . . . . . . . . . . . . . 521.20 TaOx model inner structure . . . . . . . . . . . . . . . . . . . . . . . 531.21 Simulation of the TaOx model . . . . . . . . . . . . . . . . . . . . . . 541.22 A generalized SPICE implementation . . . . . . . . . . . . . . . . . . 551.23 Discussed electrical network . . . . . . . . . . . . . . . . . . . . . . . 611.24 Diode schematic symbol and its companion model . . . . . . . . . . . 651.25 SPICE algorithm overview . . . . . . . . . . . . . . . . . . . . . . . . 671.26 Implementation of f(a, b, c) = (a+ b) · c+ b . . . . . . . . . . . . . . 701.27 Symbol of IMPLY gate . . . . . . . . . . . . . . . . . . . . . . . . . . 701.28 Memristor based implication . . . . . . . . . . . . . . . . . . . . . . . 711.29 NAND implementation using memristors . . . . . . . . . . . . . . . . 711.30 Graphical interpretation of the membership function . . . . . . . . . 741.31 The fuzzy logic operation implemented using memristors . . . . . . . 74
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2.1 The photo and stack of a TiO structure . . . . . . . . . . . . . . . . . 772.2 Common sample failures . . . . . . . . . . . . . . . . . . . . . . . . . 782.3 The photo and stack of a TaO structure . . . . . . . . . . . . . . . . 792.4 Unknown node example . . . . . . . . . . . . . . . . . . . . . . . . . 812.5 Circuit example used for the comparison . . . . . . . . . . . . . . . . 852.6 LTspice simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852.7 Developed simulator 10 iterations . . . . . . . . . . . . . . . . . . . . 862.8 Developed simulator 50 iterations . . . . . . . . . . . . . . . . . . . . 862.9 ODE comparison on the state variable equation . . . . . . . . . . . . 87
3.1 Characteristics of the MEM_6 2-8 sample . . . . . . . . . . . . . . . 903.2 Square wave input on TiO structure . . . . . . . . . . . . . . . . . . . 903.3 Modified staircase function on TiO structure . . . . . . . . . . . . . . 913.4 TiO double structure measurement . . . . . . . . . . . . . . . . . . . 923.5 Characteristics of the TaO sample . . . . . . . . . . . . . . . . . . . . 933.6 RESET location dependence on the SET . . . . . . . . . . . . . . . . 943.7 Pulse measurements on the TaO sample . . . . . . . . . . . . . . . . 953.8 Minimum measurement on the TaO sample . . . . . . . . . . . . . . . 963.9 Complementary resistive switch [74] . . . . . . . . . . . . . . . . . . . 963.10 Modelling the behaviour of TaO double structure . . . . . . . . . . . 993.11 Modelling the behaviour of HfO double structure . . . . . . . . . . . 993.12 Fitting TiO with the exponential model . . . . . . . . . . . . . . . . . 1003.13 Properties of the used model in next simulations . . . . . . . . . . . . 1013.14 Fitting TaO measured sample . . . . . . . . . . . . . . . . . . . . . . 1023.15 Minimum simulation using the exponential model . . . . . . . . . . . 1043.16 Simulation of the maximum function . . . . . . . . . . . . . . . . . . 1043.17 Simulation of three inputs (1, 2, 3) minimum function . . . . . . . . . 1053.18 Three inputs minimum scheme . . . . . . . . . . . . . . . . . . . . . . 1053.19 Simulation of three inputs (1, 2, 4) minimum function . . . . . . . . . 1053.20 Memristor based comparator circuit . . . . . . . . . . . . . . . . . . . 1063.21 Memristor based comparator behaviour . . . . . . . . . . . . . . . . . 1073.22 Dynamics of the comparator . . . . . . . . . . . . . . . . . . . . . . . 1073.23 Behaviour of a comparator for different inputs . . . . . . . . . . . . . 1083.24 Argmax and argmin simulations . . . . . . . . . . . . . . . . . . . . . 1093.25 Sorting networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103.26 BM4 using the ideal states . . . . . . . . . . . . . . . . . . . . . . . . 1113.27 BM4, where the first layer has opposite states . . . . . . . . . . . . . 1123.28 BM4, where the third layer has opposite states . . . . . . . . . . . . . 1123.29 BM4, the time dependence for L1 and L3 with opposite states . . . . 1133.30 OE4, where the first layer has opposite states . . . . . . . . . . . . . 1133.31 OE4, the worst case (all memristors are oppositely initialized) . . . . 114
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3.32 Sorting failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153.33 Odd-even transposition sort for 8 inputs . . . . . . . . . . . . . . . . 115
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List of Tables
1.1 Volatile and non-volatile memories comparison . . . . . . . . . . . . . 371.2 MNA resistor stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . 641.3 MNA voltage source stamp . . . . . . . . . . . . . . . . . . . . . . . . 641.4 Truth-table example . . . . . . . . . . . . . . . . . . . . . . . . . . . 691.5 Karnaugh map example . . . . . . . . . . . . . . . . . . . . . . . . . 691.6 The implication truth table . . . . . . . . . . . . . . . . . . . . . . . 701.7 The sequence of voltages applied to obtain the NAND operation . . . 711.8 Equivalence of the sequence of operations to NAND . . . . . . . . . . 721.9 Examples of fuzzy operators . . . . . . . . . . . . . . . . . . . . . . . 73
2.1 Simulator options overview . . . . . . . . . . . . . . . . . . . . . . . . 83
3.1 Sorting networks comparison . . . . . . . . . . . . . . . . . . . . . . . 110
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List of Abbreviations
CC Current Compliance
CMOS Complementary Metal-Oxide-Semiconductor
CRS Complementary Resistive Switch
DRAM Dynamic Random-Access Memory
ECM Electrochemical Metallization Memory
FPGA Field Programmable Gate Array
GUI Graphical User Interface
HDD Hard Disk Drive
HRS High Resistance State
KCL Kirchhoff’s Current Law
KVL Kirchhoff’s Voltage Law
LRS Low Resistance State
MIM Metal-Insulator-Metal
MNA Modified Nodal Analysis
N-R Newton-Raphson method
ODE Ordinary Differential Eequation/s
PCM Phase-Change Memory
R the set of real numbers
ReRAM Resistive Random-Access Memory
RHS Right Hand Side
RR Resistance Ratio
SAS Slovak Academy of Sciences
SIMD Single Instruction, Multiple Data
SMU Source-Measuring Unit
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SPICE Simulation Program with Integrated Circuit Emphasis
SRAM Static Random-Access Memory
STA Sparse Tableau Analysis
TCM Thermochemical Memory
TMO Transition Metal Oxides
VCM Valence Change Memory
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Introduction
The memristor science area is complex and multidisciplinary. It touches multiple
research areas such as electronics, system theory, physics, chemistry and last but
not least informatics. The attractiveness of this problem is confirmed by the num-
ber of published papers, workshops and conference events dealing with memristors.
This thesis focuses on only a small part of possible research, namely modelling of
memristive networks. It is divided into following parts:
The first chapter introduces the basic electrical components, interrelation be-
tween them and related laws to the reader. A description of resistive switching
mechanism is explained for different kinds of structures in this chapter. This part
also provides a complex overview of existing memristor models and the methods
used in circuit simulation (containing also the description of numerical methods).
Finally, this part also touches the topic of logic circuits.
The second chapter reviews previous research in this field done at our department
and the methods, which were used to obtain the results. Samples, that were used
and obtained measurements are described in this chapter together with simulation
method. Next, there is a description of the developed simulator and comparison to
existing solutions.
The third chapter describes the experimental results in detail – the measure-
ments as well as the performed simulations. A new memristor based component –
comparator – is introduced in this chapter and its properties are described using a
non-linear memristor model. This component was used as the main building block
in the sorting networks. The implementation of a sorting network is only a small
part of possible applications.
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Objectives
The main aim of this thesis is:
• the development of a new simulation method suitable for modelling of mem-
ristor networks utilizing multiple CPUs and GPU
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Chapter 1
Current state
At the beginning, this chapter introduces the reader into the problem of electrical
elements. It explains the resistive switching mechanism and defines the memristor as
the fourth basic electrical component. Also, known memristor models are described.
Secondly, the circuit simulation methods are described (starting with theorems up
to numerical methods used in circuit simulation). Finally, the overview of memristor
based two value and fuzzy logic is present.
1.1 Electrical elements
Within this work, an element is a two-terminal electrical device. A node is any point
in a circuit where two or more elements meet. A network is a set of elements and
nodes and network can be represented via a graph. Vertices in the graph correspond
to nodes and edges to electrical elements.
1.1.1 Passive elements
According to the definition of a passive device in [83], such device has the property,
that the voltage v across it and the current i through it, are given by the element
equations, in general (1.1):
v = f(i, i′) or i = g(v, v′), (1.1)
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1.1. ELECTRICAL ELEMENTS
where the functions f(·) and g(·) map R onto R and where i′ and v′ are first-order derivatives of i and v respectively. If the element equation does not contain
any derivative, then it is said to be a resistive element, otherwise it is a dynamic
element.
Resistor It is a passive two-terminal resistive element. An ideal resistor is chara-
cterized by its equation (1.2).
v = R · i or i = G · v (1.2)
where R is the resistance [Ω] (Ohm), G is the conductance [S] (Siemens), v is the
voltage across the resistor [V] (Volt) and i is the current [A] (Ampere) flowing
through the resistor. The schematic symbol for a linear resistor is shown in Fig.
1.1a.
R
+ −v
i
(a) Linear resistor
+ −v
if(·)
(b) Nonlinear resistorFigure 1.1: Schematic symbol for a linear and a non-linear resistor
When the element function f(·) is a non-linear function, the resistor becomesnon-linear. If the function f(·) has the form v = f(i), then it is a current-controlledresistor. If the element function has the form i = g(v), it is a voltage-controlled
resistor. The functions f , g have not necessarily the inverse function f−1, g−1
Capacitor A capacitor is a dynamic two-terminal device whose electrical charge
q, is a function of the voltage v applied across it, so that q = f(v). The element
equation is given by (1.3).
q = C · v or i = Cdvdt
(1.3)
When the capacitance C is a function of the voltage, it is said to be a non-linear
capacitor, otherwise it is a linear capacitor. A schematic symbol of a linear capacitor
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CHAPTER 1. CURRENT STATE
is shown in Fig. 1.2
C
+ −v
iFigure 1.2: Schematic symbol for a linear capacitor
Inductor An inductor is a dynamic two-terminal device whose magnetic flux φ,
is a function of current flowing through it, so that φ = f(i). The element equation
given by (1.4).
φ = L · i resp. v = Ldidt
(1.4)
When the inductance L is a function of the current flowing through it, it is a non-
linear inductor. A schematic symbol of a linear inductor is shown in Fig. 1.3
L
+ −v
iFigure 1.3: Schematic symbol for a linear inductor
1.1.2 Active elements
Active elements can be split into two main groups – independent sources and con-
trolled sources. Controlled sources can be either linear or non-linear and for further
reading, they are described in [102], [83]. In this work are used only independent
voltage sources – voltage sources, or independent current sources – current sources.
Independent voltage source In simulations, an independent voltage source has
the property, that the voltage across it is either constant or a function of time:
v = f(t). Schematic symbol for an independent voltage source is shown in Fig.
1.4a.
Independent current source Similar to an independent voltage source is a cur-
rent source, which has the property that the current through it is either constant or
31
-
1.2. INTERRELATION OF ELECTRICAL ELEMENTS
a function of time: i = f(t). Schematic symbol for an independent current source
is shown in Fig. 1.4b.
+
−v(t)
(a) Voltage source
i(t)
(b) Current sourceFigure 1.4: Schematic symbols for independent sources
1.2 Interrelation of electrical elements
As shown in section 1.1 each elementary element has its own relation between two
variables. To explain the relation between the components it is necessary to show
also other physical properties.
Electric charge (charge) q is a physical property of electrons and protons in the
atoms of matter that gives rise to forces between atoms [22]. The SI unit of electric
charge is the coulomb [C].
The electric current (current) i is the flow of electric charge q that is measured
by its flow rate. In other words, current i through a cross section at time t is given
by (1.5) [22].
i =dq
dtor q =
∫ t2
t1
i dt (1.5)
The electric voltage (voltage) v is the electric potential difference between two
points, or the difference in electric potential energy of a unit charge transported
between two points.
The magnetic flux (flux) φ is defined as the time integral of the electric voltage
(1.6).
φ =
∫ t2
t1
v dt or v =dφ
dt(1.6)
Previously described elements are also called fundamental, because they cannot
be replaced by a network of other elements. Putting equations (1.2), (1.3), (1.4),
(1.5) and (1.6) together, it is possible to draw their relation as shown in Fig. 1.5.
32
-
CHAPTER 1. CURRENT STATE
v
i q
φ
dv = R di
dφ = L di
dq = C dv
dφ =?dq
Figure 1.5: The three fundamental two-terminal circuit elements
1.3 Memristor
The missing element in Fig. 1.5 was discovered in 1971 by Leon O. Chua [25] and it
was named memristor, an abbreviation of memory resistor. The charge-controlled
memristor defined by Chua in [25] should implement the missing relation between
the flux φ and the charge q according to (1.7).
dφ = M(q) · dq (1.7)
Differentiating (1.7) with respect to time t, gives the definition (1.8).
v = M(q) · i (1.8)
The term M in (1.7) and (1.8) is called memristance at q and has unit of Ohms [27].
An analogy to charge-controlled memristor is the flux-controlled memristor and its
definition is given by (1.9).
dq = G(φ) · dφ, (1.9)
where G(φ) is called the memconductance at φ and has the unit of condunctance –
Siemens.
In case of a linear time-invariant memristor, in which M from (1.8) is a constant,
the memristance is identical to resistance [97]. A non-constant M yields a non-linear
circuit element — resistive element with memory or a resistor whose resistance
depends on the amount of charge that passed through it.
33
-
1.3. MEMRISTOR
M(·)
− +v
iFigure 1.6: A memristor schematic symbol
1.3.1 Memristive system
The definition of memristor was generalized by Chua and Kang in [29], to a more
general class of dynamical systems. An nth-order current-controlled memristive
one-port is represented by equation (1.10).
ẋ = f(x, i, t)
v = R(x, i, t)(1.10)
Similarly, the nth order voltage-controlled memristive one-port was defined as (1.11).
ẋ = f(x, v, t)
i = G(x, v, t)(1.11)
In (1.10) and (1.11), the x denotes an n-dimensional state of the system – state
variable, and ẋ its time derivative. A charge-controlled memristor defined by equa-
tion (1.8) is a current-controlled time-invariant memristive system, whose state vari-
able has one dimension. Considering (1.10), it is possible to derive the relation for
a charge-controlled memristor (1.12).
v = M(w) · i and ẇ = q̇ = i, (1.12)
where w = q and M(·) is the memristance function.The definitions of a memristor or a memristive system were made 30 years ago.
At first, the memristor was defined by a constitutive charge-flux relation [25]. Few
years after the first definition, the memristor was considered as an element from the
set of higher-order elements [26] and then as a more complex memristive system
[29]. In 2008, HP [97] presented a device, that had the properties of a memristor
(it had memory and typical curve) and its physical operation mechanism was based
34
-
CHAPTER 1. CURRENT STATE
Voltage [V]
Cur
rent
[A]
-3 -2 -1 0 1 2 3-1
0
1
Figure 1.7: An analytical pinched hysteresis loop
on resistive switching and this started the discussion about what should be called
a memristor and what should not. For purposes of this work, all two-terminal non-
volatile memory devices based on resistance switching, regardless of material and
physical operating mechanisms are called memristors, according to [28], [10]. All
those devices exhibit a distinctive “fingerprint” characterized by a pinched hysteresis
loop (crossing itself at the origin) confined to the first and third quadrants of the
V-I plane. An analytical pinched hysteresis loop is shown in Fig. 1.7.
1.3.2 Possible applications
Memristor circuits may be found in multiple applications. Besides the memory appli-
cations, the scientists focus on two main domains. The discrete device applications
use memristors in a manner that takes advantage of their non-linear characteristics
and their controllable resistance changes to enhance the performance of the desired
application. Discrete applications can be analogue and digital. The analogue dis-
crete applications may find the usage as chaotic circuits [79][80], oscillators [46],
variable gain amplifiers [107] and cellular neural networks [68]. Finally, the discrete
digital application are mainly logic operations, digital gates and reconfigurable log-
ical circuits, also discussed in 1.9.1.2.
On the other hand array device applications, not only depend on memristor
properties but are also coupled with the ongoing trend to increase the device density
[78]. The discrete and the crossbar array devices can also be divided into analogue or
digital applications – similar to the discrete applications. A representative analogue
35
-
1.4. RESISTIVE SWITCHING MECHANISM IN THIN-FILM DEVICES
application in a memristor-based crossbar array are the neuromorphic networks [76],
[50] and field programmable analogue arrays [110], where the memristors are used
as a programmable resistor array and as switching elements. The digital crossbar
arrays may be used mainly as a non-volatile memory, discussed in the section 1.4
and as the logic circuits, described in the section 1.9.1.2. It is necessary, for the
purposes of development of such applications, to have a universal modelling tool as
was developed and described in this work.
1.4 Resistive switching mechanism in thin-film de-
vices
The switching process in thin film devices was discovered for the first time in 1968
[2], but the success of silicon-based electronics obscured eventual technological ap-
plications. The research of TMOs focusing on high temperature superconductivity,
in the 90s renewed the interest in resistive switching phenomena.
In this section the switching mechanism in thin-film devices will be described. A
material I is sandwiched between two (possibly different) M conductors – electrodes
in a MIM structure. The material I is composed of an ion or mixed ion-electron
conducting material. Quite remarkably, a huge variety of systems exhibiting resistive
switching were reported in fast succession.
• Phase change chalcogenides such as Ge2Sb2Te5 [54]
• Binary TMO such as Al2O3, SiO2, TiO2, NiO, HfO . . . [114]
• Perovskites such as PrxCa1−xMO3 (PCMO) [3]
• others
In general, MIM structures enable at least two different resistance states [104].
The operation description by a two state device is following: By application of an
appropriate write voltages VWR to a device which is in a high resistance state (OFF),
the device can be SET into a low resistance state (ON). If the device was in a low
resistance state, it is possible to RESET the device back into the HRS (OFF). One of
36
-
CHAPTER 1. CURRENT STATE
the most focused applications is ReRAM as a successor of current RAM memories.
The requirements for correct operation of ReRAM [37] are:
• Write operation: Write voltages should be in range starting 1÷ 5 V (to becompatible with scaled CMOS). The timing of a write operation is typically
< 100 ns
• Read operation: Read voltages should be significantly smaller than write
voltages to prevent unwanted write operation (0.1÷0.5 V). The read operationshould be much faster than the write operation.
• Resistance ratio: The requited ratio ROFF/RON is at least > 10.
• Endurance: The number of write cycles should be up to 107.
• Retention: A data retention time of > 10 years is required for universal non-
volatile memories. This retention must be also kept when thermal stress is
present[93].
A comparison table, from [114], of selected volatile and non-volatile memories is
shown in Tab. 1.1.
ReRAM PCM SRAM DRAM Flash1 HDD
Energy per bit (pJ) 0.1 – 3 2 – 25 0.5× 10−3 5× 10−3 20× 10−6 1 − 10× 109Read time (ns) 1016 > 1016 104 104
Table 1.1: Volatile and non-volatile memories comparison
Based on the polarity, the resistive switching in TMO can be roughly classified
into two types – unipolar and bipolar.
1NAND2as long as voltage applied3as long as capacitors are discharged ≪1 s
37
-
1.4. RESISTIVE SWITCHING MECHANISM IN THIN-FILM DEVICES
OFFOFF
ON
ON
CC
CC
(a) Unipolar switching
OFF
OFF
ON
ON
CC
(b) Bipolar switching
Figure 1.8: Sketches of resistive switching
Unipolar switching operation The switching procedure does not depend on
the polarity of the write signal. The SET voltage is always higher than the RESET
voltage and the RESET current is always higher than the current compliance during
SET operation.
Bipolar switching operation The SET operation occurs at one polarity and the
RESET operation at reversed voltage polarity. In old terminology, bipolar switching
was referred to as “polarized memory switching” [49]. Unipolar and bipolar switching
are shown in Fig. 1.8, where the voltage is depicted on the x-axis and the current
on the y-axis.
1.4.1 Types of resistive switching
The common property in resistive switching memory types described in this section
is, that all of them are based on redox. There is a filament present in all described
kinds of cells. A filament is a local conduction path bridging two electrodes in the
MIM. Conductive filaments are formed after electroforming4 or during the first SET
operation [72].
4A special initial cycle
38
-
CHAPTER 1. CURRENT STATE
1.4.1.1 Electrochemical Metallization Memory
In electrochemical metallization memory (ECM) devices one electrode is made of
an electrochemically active electrode such as Ag or Cu and the second electrode
is an electrochemically inert counter electrode such as Pt, W, Ir or Au [104]. A
conducting ion layer is sandwiched between these electrodes. This I layer is either
a solid electrolyte (e.g. Ag2S, Cu2S) or an insulator (e.g. SiO2, GeS).
Ag Pt
(a) Initial OFF state
Ag+
Ag Pt
(b) SET process
Ag Pt
(c) ON state
Ag+
Ag Pt
(d) RESET process
Figure 1.9: Different switching stages in ECM (Ag/Ge-Se/Pt)
SET and RESET process By applying a positive voltage on the active electrode
the metal atoms are first ionized and then migrate through the electrolyte towards
the cathode, which is grounded, where positively charged ions are reduced and
electrocrystallised on the interface region between the cathode and solid electrolyte
thin film. As one of the fastest growing filaments contacts the active electrode
(anode), the cell gets into a low resistant state (LRS). This process is called a SET
process. The cell is in the LRS so long as the filament exists. With an opposite bias
voltage is applied, the filament begins to be electrochemically dissolved from the
anode and the cell switches into high resistant state (HRS). This is called a RESET
process. The metallisation and dissolution of the electrochemical reaction here can
be expressed by (1.13), where M is either Ag or Cu [72].
Mn+ + en− ⇐⇒ nM (1.13)
Authors in [94] describe an extremely low power consumption for a Ag/Ge-Se/Pt
device. The switching voltages were few hundred mV (220 mV and −60 mV), thewrite currents as low as 1 nA and −0.3 nA for a cell with a diameter of 2.5 µm. Thisstructure shows a bipolar resistive switching with a resistance ratio (RR) 5 orders
the magnitude.
39
-
1.4. RESISTIVE SWITCHING MECHANISM IN THIN-FILM DEVICES
1.4.1.2 Valence Change Memory
A valence change memory (VCM) device consists of an active electrode, where the
switching takes place, a mixed ionic-electronic conducting layer – I and an ohmic
counter electrode. Resistive switching in TMO involves anion migration during
the switching processes. In such materials, the oxygen vacancies have much better
mobility than the transition metal cations [105]. The positively charged oxygen
vacancies drift through the defects under the applied electrical field.
Currently, there are three typical approaches to get a VCM-type MIM system.
These concepts differ in the thin film oxide I layer. Pt, Ir or TiN are often used
as active electrodes and a metal with low work function and high oxygen affinity is
preferred for ohmic electrode.
1. Homogeneous layer concept – the thin layer is composed of TiOx, TaOx,
HfOx or WO.
2. Homogeneous bi-layer concept – between electrodes, there are two layers:
the thinner oxygen deficient layer (close to the active electrode) and the second,
thicker, fully oxidized layer. In [114] were used TiO2/TiO2−x and in [65]
Ta2O5/TaOx
-
CHAPTER 1. CURRENT STATE
SET and RESET process After electroforming, a filament (between electrodes)
is grown in the device. The plug of the filament consists of a conducting mixed
ionic-electronic oxide and the disc of a filament represents a potential barrier.
By applying a negative voltage on the active electrode, while ohmic electrode
is grounded, the oxygen vacancies from the plug are attracted to the barrier. This
results in a significant decrease of the disc height and width due to a local reduction
process and the device switches into ON state. For the RESET, a positive voltage is
applied on the active electrode which repels the oxygen vacancies, leading to a local
re-oxidation and switches the cell into the OFF state. In this case, the switching
polarity is called counter-eight-wise [104]. A typical counter-eight-wise and eight-
wise V-I characteristics are shown in Fig. 1.11.
A
V
(a) Eight-wise switching behaviour
A
V
(b) Counter-eight-wise switching behaviour
Figure 1.11: Common switching behaviours in VCM
1.4.1.3 Thermochemical memory
The thermochemical memory (TCM) effect is attributed to the temperature-induced
change of valence state of transition metal ions. The resistive switching process
shows a unipolar characteristic [103]. Often the same material is used for both
electrodes in these cells. The material for electrodes should be an inert metal such
as Pt or Ru. TCM switching is present in most oxides that show a high resistance
in the most oxidized state and low resistance in reduced state. Some of the oxides
that fit this characteristic are: TiOx, Al2O3, NiO and others.
SET and RESET process Suppose that the device is, after electroforming pro-
cess, in the OFF state. The conductive filament is not completely dissolved, but
41
-
1.5. MEMRISTOR MODELS
(a) ON state (b) RESET process (c) OFF state (d) SET process
Figure 1.12: Different switching stages in an TCM
only ruptured. The applied SET voltage triggers thermochemical process [104]. The
residue conductivity in the OFF state increases the temperature locally, which helps
the drift of the oxygen out of the high temperature locations. This happens because
of the energetically favoured lower valence states of the TMO. The RESET proce-
dure in TCM cells produces current above mA range [72]. This high current results
in high temperature in the metallic filament and when the temperature increases
above the melting point of the filament, the filament breaks.
1.5 Memristor models
Since 2008 until now, several memristor models have been presented. Each kind of
resistive switching should have its own model. We consider two VCM structures
based on Ti and Ta and deterministic models. Stochastic memristor model was
published in [77]. Analogue memristor models were published in [99] and [35]. In
all models, the state variable is denoted by w.
1.5.1 Linear ion drift
A physical memristor model was presented for the first time in [97]. In this model,
the memristor is characterized by an equivalent time-dependent resistor whose re-
sistance is proportional to the quantity of charge q that has passed through it. The
proof-of-concept implementation consisted of a homogeneous bi-layer concept – 5 nm
thick oxide film which initially contained one layer of insulating TiO2 (2 nm) and
one oxygen deficient layer of TiO2−x (3 nm). These layers were sandwiched between
two Pt nanowires. The concept of this device is shown in Fig. 1.13a, where w is the
state variable and D is the total width of the device.
42
-
CHAPTER 1. CURRENT STATE
+
−
Pt
Pt
TiO2−x
TiO2
wDoped
Undoped
(a) Memristor concept by HP
RON w/D ROFF w/D
(b) Simplified HP memristor modelFigure 1.13: Linear ion drift model
The two resistors shown in Fig. 1.13b represent the two boundaries of the device.
When the resistance equals RON , the semiconductor film has a high concentration of
dopants (positive ions) – LRS – and the remainder has a low dopants concentration
and much higher resistance – ROFF – HRS. After applying a bias voltage across
the device, the boundary between the regions moves (the state variable w changes).
This is caused by the drift of charged dopants.
This model assumes a linear ion drift in a uniform field [97], [32], [91]. According
to memristive system definition (1.12) and (1.10), a model was defined by (1.14)
and (1.15).
v =(
RONw
D+ROFF
(
1− wD
))
· i (1.14)
dw
dt= µV
ROND
· i (1.15)
Integrating the equation (1.15) with respect to time t, gives the definition (1.16),
w = µVROND
· q, (1.16)
where µV is the average ion mobility.
Using this model, it is possible to achieve an apparent or “dynamical” negative
differential resistance [11]. The negative differential resistance makes the memristor
to be a locally active device. Such a dynamical effect is a result of the charge-
dependent change in the device resistance and can be identified by a strong depen-
dence on the frequency of the applied voltage [97]. By applying a higher voltage,
the boundaries are reached much faster and the switching is a monotonic function
43
-
1.5. MEMRISTOR MODELSVoltage
[V]
Time [ms]
Curr
ent
[µA
]
0 0.1 0.2
20
−20
0
−1
−0.5
0
0.5
1
(a) Input voltage and current
time [ms]
w
M[kΩ
]
0 0.1 0.20
50
100
0
0.5
1
(b) State variable and memristance
Voltage [V]
Curr
ent
[µA
]
flux ×10−5
charg
e×10−10
f = 10 kHzf = 100 kHz
0 1 2 3
-1 -0.5 0 0.5 1
0
4
820
-20
-10
0
10
(c) V-I loop for linear ion drift model
Figure 1.14: Linear ion drift model behaviour
of current. The current-voltage equation of linear ion drift model was adopted in a
homogeneous bi-layer concept made of Pt/Ta2O5/TaOx/Pt published in [44].
SPICE implementation The SPICE implementation of Linear ion drift model
was first presented in [8] and modified in [11]. The current-voltage relation is slightly
modified and modelled by equation (1.17).
Rmem(w) = ROFF − w∆R, ∆R = ROFF − RON (1.17)
The ROFF resistor in series with a voltage controlled voltage source (E-type source
in SPICE) correspondents to equation (1.17). The terminal voltage of the E-type
source is controlled according to formula −x∆R. The voltage V (w) on the capacitorC(w) is used for the modelling of normalized state variable w. This connection serves
as an integrator of the quantities on the right side of state equation (1.15) [11].
44
-
CHAPTER 1. CURRENT STATE
−∆RV (w)Emem
Imem
ROFF
w
Gw
kImemf(V (w))
w0
Cw
Tp
Tm
Figure 1.15: The Linear ion drift SPICE model
1.5.2 Linear ion drift window functions
Even a small voltage applied in a nanoscale device can yield huge electric fields,
which can produce significant non-linearities in ionic transport [97]. For simulation
of non linearity, when the state variable is close to the bounds, this model was
completed with a window function. After [97] was published, also several other
window functions have been defined and they are named after their inventors. Each
window function completes the state variable function with a non-linear function.
Strukov window The first window function was published together with the
Linear Ion drift model [97]. The equation of this window is in (1.18), where w is the
normalized state variable.
f(w) = w · (1− w) (1.18)
Joglekar window Authors in [51] stated, that the speed of the state variable
should be strongly suppressed only when the state variable reaches the edges (w = 0
resp. w = 1). The window function is symmetric about w = 1/2 and monotonically
increasing over 0 ≤ w ≤ 1/2. The equation (1.19) shows the window function, wherep is an integer value.
f(w) = 1− (2 · w − 1)2p (1.19)
Biolek window If the linear ion drift model, completed with the window function
(1.19), is initially set to RON or ROFF , there is no chance to change its state back
to another value – it would forever remain a linear resistor – this is a consequence
of the zero-value window function in either boundary state [11]. Authors concluded,
45
-
1.5. MEMRISTOR MODELS
that the window function should also consider the direction of the current flowing
through the memristor. The window is defined in (1.20), where i is the current
flowing through the memristor, p is an integer value and stp(i) is a function defined
in (1.21).f(w) = 1− (w − stp(−i))2p (1.20)
stp(i) =
{
1, i ≥ 00, i < 0
(1.21)
Prodromakis window The last window function has been published in [90]. Au-
thors compare existing window functions and propose a window function which
should solve the “terminal state problem” in Joglekar window and be more scalable
than Biolek window. The window function is defined as follows, where j is a scaling
parameter:f(w) = j ·
(
1−[
(w − 0.5)2 + 0.75]p) (1.22)
w
f(w
)
0 0.2 0.4 0.6 0.8 10
0.05
0.1
0.15
0.2
0.25
(a) Strukov windoww
f(w
) p = 1p = 2p = 4p = 8p = 16
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
(b) Joglekar window
w
f(w
)
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
(c) Biolek windoww
f(w
)
j = 0.5, p = 10j = 0.5, p = 100j = 1, p = 10j = 1, p = 100j = 1.5, p = 10j = 1.5, p = 100
0 0.2 0.4 0.6 0.8 10
0.5
1
1.5
(d) Prodromakis window
Figure 1.16: Window functions
46
-
CHAPTER 1. CURRENT STATE
1.5.3 Simmons Tunnel Barrier Model
A more precise model of a VCM device with a homogeneous layer concept Pt/TiO2/Pt
was published in [87], the thickness of respective layers are 15/50/30 nm. This model
assumes non-linear and symmetric switching behaviour due to an exponential de-
pendence on the movement of the ionized dopants – changes in the state variable.
This model is also composed according to the definition of the memristive system –
(1.11). The physical concept of this device is shown in Fig. 1.17.
Pt
Pt
Rs
w
TiO2
+
−
vg
Figure 1.17: Simmons tunnel barrier model inner structure
In this model, there is a resistor (Rs) in series with an electron tunnel barrier.
The state variable w is used for simulating the width of Simmons tunnel barrier.
The Simmons expression for a rectangular barrier with image forces is used as the
current equation. The functional form of the current passing through the device is
given by (1.23). The Simmons expression in final model is slightly modified [1]. The
barrier height φI is in volts instead of electron volts and the time-varying tunnel
barrier width, w, is in nanometres instead of metres.
i =j0Ae
∆w2
{
φI · exp(
−B√
φI
)
− (φI + |vg|) · exp(
−B√
φI + |vg|)}
, (1.23)
where
j0 =e
2πh, w1 =
1.2λw
φ0, ∆w = w2 − w1 (1.24)
φI = φ0 − |vg| ·(
w1 + w2w
)
−(
1.15λw
∆w
)
ln
(
w2(w − w1)w1(w − w2)
)
(1.25)
B =4π∆w · 10−9
√2me
h(1.26)
47
-
1.5. MEMRISTOR MODELS
w2 = w1 + w
(
1− 9.2λ(2.85 + 4λ− 2|vg|)
)
(1.27)
λ =e2 ln(2)
8πκε0w(1.28)
where A is the channel area of the memristors, e is the electron charge, vg is the
voltage across the tunnel barrier, not necessarily equal to the voltage applied to
the device, m is the mass of the electron, h is Planck’s constant, κ is the dielectric
constant and φ0 is the barrier height in electron volts. φI is barrier height in volts.
w is the time varying state variable – barrier width. w1, w2 and ∆w have dimensions
in nm.
The state variable (tunnel barrier width) has been modelled using two equations.
In case of OFF switching (i > 0), equation (1.29) has been used. The second
equation (1.30), has been used in case of ON switching (i < 0).
dw
dt= foff sinh
( |i|ioff
)
exp
(
− exp(
w − aoffwc
− |i|b
)
− wwc
)
(1.29)
dw
dt= −fon sinh
( |i|ion
)
exp
(
− exp(
aon − wwc
− |i|b
)
− wwc
)
(1.30)
This model deals with a lot of errors during simulation. This is caused by extreme
non-linearity of the dynamics with respect to the current magnitude [1]. Authors in
[61] declare this model as the most accurate physical model of a memristor, but also
as very computationally inefficient. In our simulation, the model presented in [1] was
used and the constants were also taken from this paper. The Fig. 1.18a shows the
V-I characteristic, while Fig. 1.18b shows the input voltage and calculated current.
1.5.4 TEAM model
ThrEshold Adaptive Memristor (TEAM) model was published in [61]. TEAM
model is much more computationally convenient compared to the Simmons tunnel
model for a Pt/TiO/Pt device. This model represents the same physical behaviour,
but with simpler mathematical functions. In this model, the memristor current and
48
-
CHAPTER 1. CURRENT STATE
Voltage [V]
Cur
rent
[mA
]
-3 0 3 6-1
0
1
2
(a) V-I characteristic
Vol
tage
[V]
Time [ms]
Cur
rent
[mA
]
0 1 2 3 4 5 6
-1
0
1
2
-3
0
3
6
(b) Input voltage and the current
Figure 1.18: Simulation of the Simmons tunnel barrier
state drift variable have polynomial dependence. For this model, two current-voltage
relations have been proposed – linear (1.31) and exponential (1.32).
v =
[
RON +ROFF − RONwoff − won
(w − won)]
· i (1.31)
v = RON · exp(
λ
woff − won(w − won)
)
· i, (1.32)
where w ∈ 〈won, woff〉, λ is a fitting parameter and RON and ROFF are the equivalentresistances at the bounds.
The memristor can be modelled as a device with threshold currents. This ap-
proximation is similar to the threshold voltage approximation in MOS transistors.
This approximation is justified, since for small changes in the electric tunnel width,
separation of variables can be performed. Therefore the state variable can be mo-
delled by multiplying a function of current and a function of the state variable. The
state variable drift equation in case of i < ioff < i is given by (1.33), in case of
i < ion < 0 is given by (1.34) and in case of ion < i < ioff is the state variable drift
equation given by: dw(t)/dt = 0.
dw
dt= koff ·
(
i(t)
ioff− 1
)αoff
· foff (w) (1.33)
49
-
1.5. MEMRISTOR MODELS
dw
dt= kon ·
(
i(t)
ion− 1
)αon
· fon(w), (1.34)
where koff , kon, αoff and αon are constants, ioff and ion are current thresholds.
The functions foff (w) and fon(w) behave as the window functions. These window
functions are not necessarily equal, because w may be asymmetric. The role of the
state variable w in this model is opposite to that of w in the Linear ion drift model.
In [61], there were also window functions proposed for this model. These are given
by equations (1.35) and (1.36).
foff(w) = exp
[
− exp(
−w − aonwc
)]
(1.35)
fon(w) = exp
[
− exp(
w − aoffwc
)]
(1.36)
1.5.5 Exponential model
Exponential model was published in [113]. The name of this model varies in review
articles. In [61] and [63] this model is called non-linear ion drift, in [32] it is called
exponential model and in [33] it is referred to only by authors’ names. In this work,
this model is referred to as exponential model.
This model has been used for simulations of a Pt/TiO2/Pt device. To increase
the near surface vacancy concentration, a single rutile crystal (TiO2) was annealed
at a high temperature. The top interface became non-ohmic (Schottky-like) and the
bottom interface became ohmic-like. Authors also describe, that the switching in
the device occurs only on the non-ohmic interface and that the switching is bipolar.
The current-voltage equation (1.37) consists of two parts. The first part, sinh(·),is used for modelling the ON state, which is essentially electron tunnelling through
a thin residual barrier. The second term is an approximation for the rectifier, based
on Shockley diode model, [111] and it is active when the device is in OFF state.
This model satisfies both the electronic measurements and the material composition
of the device.
i = wn · β sinh(α · v) + χ (exp(γ · v)− 1) , (1.37)
50
-
CHAPTER 1. CURRENT STATE
where w is the state variable and n, β, α, χ, γ are fitting parameters. v is the
voltage across the memristor.
The state variable drift equation was not presented in the article [113], but in
multiple other articles. Equation (1.38) was proposed in [68] and [64]. Equation
(1.39) was proposed in [32] and the last one, (1.40), was introduced in [33].
dw
dt= a · f(w) · g(v), (1.38)
where a is a constant, f(w) is one of the window functions described in section 1.5.2
and g(v) is a polynomial function of voltage, given by g(v) = vq, for some q ∈ 2N−1.
dw
dt= a · sinh(b · v) · f(w), (1.39)
where a, b are fitting parameters, v is the voltage and f(w) is one of the window
functions from section 1.5.2.
dw
dt= υ · g(v, ρ(w), ϕ0), (1.40)
where v is the voltage, υ is a constant value to identify ON and OFF switching
speeds, w is state variable and ϕ0 is the equilibrium (v ≡ 0) barrier height in eV .The function ρ(w) is given by (1.41). The function g(v, ρ(w), ϕ0) is given as (1.42).
ρ(w) = δ + η(
1− (2w − 1)2p)
, (1.41)
where p is a positive integer value.
g (v, ρ(w), ϕ0) =
(
1− v2ϕ0
)
exp
(
ρ(w)ϕ0
(
1−√
1− v2ϕ0
))
−(
1 +v
2ϕ0
)
exp
(
ρ(w)ϕ0
(
1−√
1 +v
2ϕ0
))
(1.42)
1.5.6 WOx model
All of the models presented in previous sections were used to simulate a device
whose layer I consists of TiOx. Here, we briefly describe a model, which was used
51
-
1.5. MEMRISTOR MODELS
for a Pd/WO3/W device. This model was presented in [21] and authors declare that
electroforming in this device is not needed.
In previous models, the state variable w was used as a length index. In this
model, the growth of w is in parallel with existing conducting paths instead of
series, shown in Fig. 1.19.
+
−
w
Pd
W
Figure 1.19: WOx model inner structure
The current-voltage equation of this model is given by equation (1.43). It in-
cludes the Schottky term exp(·) and the tunnelling term – sinh(·). Similar to theexponential model in section 1.5.5, the Schottky-dominated [112] part is active when
the state variable w = 0 and the tunnelling-dominated part is active while w = 1.
i = (1− w)α [1− exp(−β · v)] + wγ sinh(δ · v), (1.43)
where α, β, γ and δ are positive parameters determined by material properties such
as the barrier height and, for tunnelling, the depletion width in the Schottky barrier
region, the effective tunnelling distance in the conduction region and interface effects.
In practice, they are treated as parameters that need fitting.
In real devices, the state drift equation is determined by the drift of charged
mobile ions such as oxygen vacancies. It has been shown that at relatively high
fields that causes the resistance switching. The ions move at a speed exponentially
dependent on the electric field (1.44) neglecting higher-order effects.
The state drift equation of this model was presented with respect to (1.44) and
it is given by (1.45) without the explicit dependence on w.
dw
dt∝ sinh
(
v/E0d− w
)
, (1.44)
52
-
CHAPTER 1. CURRENT STATE
where d is the total thickness of the film and E0 a characteristic field.
dw
dt= λ [exp(η1 · v)− exp(−η2 · v)] , (1.45)
where η1 and η2 are positive-valued parameters. In case of η1 = η2 = η, it is possible
to rewrite equation (1.45) into (1.46), where the diffusion term (−w/τ , where τ is adiffusion time constant) was added.
dw
dt= λ sinh(η · v)− w
τ(1.46)
1.5.7 TaOx model
The structure of the device presented in [98] was stacked as follows (numbers in
parentheses denote the width of the layer in nm): the top electrode consisted of
Ta(30)/Pt(200), the bottom electrode consisted of Ti(5)/Pt(20) and the I layer was
Ta2O5.
The model for the described device was published in [96]. Similarly to other
models, the equations are based on Chua’s memristive system definition (1.10). The
physical structure of this device is shown in Fig. 1.20. In [96], the state variable
is denoted by y and it should model the height according to y = ATa(O)/Achan. In
following text, w is used instead of y to unify the naming conventions of the state
variable.
+
−Pt
Ta
Ta 2
O5
TaO
x
Achan
ATa(O)
Figure 1.20: TaOx model inner structure
The current-voltage equation of this model is given by (1.47). The first part of
the equation models the metallic (ohmic) state – ON, while the second – OFF state
53
-
1.5. MEMRISTOR MODELS
– is described by a non-linear Frenkel-Poole relationship. The device conductance
is approximated by parallel combination of the two stages.
i = v[
w ·Gm + (1− w)a exp(
b√
|v|)]
, (1.47)
where Gm, a and b are fitting constants.
For modelling the dynamic changes of the device, two equations are used. The
equation (1.48) is used in case of the voltage v < 0, while the second (1.49) is used
in case of v > 0.
dw
dt= A sinh
(
v
σOFF
)
exp
[
−(wOFF
w
)2]
exp
(
1
1 + βp
)
(1.48)
dw
dt= B sinh
(
v
σON
)
exp
[
−(
w
wON
)2]
exp
(
p
σp
)
, (1.49)
where p is the power, v is the voltage, w denotes the state variable and other variables
are free model parameters, held constant during the simulation. The simulation of
the TaOx model is shown in the Fig. 1.21, with parameters taken from [96].
Voltage [V]
Cur
rent
[mA
]
-1.2 -0.8 -0.4 0 0.4 0.8-4
-2
0
2
4
6
(a) V-I characteristic
Vol
tage
[V]
Time [ms]
Cur
rent
[mA
]
0 2 4 6 8 10-4
-2
0
2
4
6
-1.5
-1
-0.5
0
0.5
1
(b) Input voltage and the current
Figure 1.21: Simulation of the TaOx model
All of the models presented in this section have a common property – the current-
voltage equation can be expressed in terms of i = f(v, w) and the state drift variable
in terms dw/dt = f(v, i, w). In SPICE-like simulators this means, that the imple-
mentation of current-voltage expression can be easily modelled using a two-terminal
54
-
CHAPTER 1. CURRENT STATE
voltage-controlled current source (Gmem). The state variable is modelled by the
voltage of a capacitor C, which serves as an integrator. For the implementation of
window functions, auxiliary functions are used. Corresponding scheme is shown in
Fig. 1.22.
w+
-
Gmem
i=f(v)
Gsv
i=dw/dt
C
Figure 1.22: A generalized SPICE implementation
1.6 Numerical methods in circuit analysis
In this section we briefly describe the numerical methods used in circuit analysis.
The described methods can be divided into two categories. In the first category,
there are methods used for solving ordinary differential equations, in literature also
known as numerical integration. These are needed because of simulation of dynam-
ical devices. Many devices are described using a non-linear equation and therefore
numerical methods used for root-finding are also required – the second category.
In the following text we use the terminology from circuit analysis, mainly tran-
sient analysis and DC analysis. Transient analysis computes the transient output
variables as a function of time over a time interval. The DC analysis determines the
DC operating point of a circuit with shorted inductors and opened capacitors. The
initial condition for the transient analysis can be automatically determined by the
DC analysis.
1.6.1 ODE solver algorithms
A dynamic system may be described by a system of first-order differential equations
of state variables. We will limit us on separable state variables, in which, the
55
-
1.6. NUMERICAL METHODS IN CIRCUIT ANALYSIS
differential equation has the form (1.50).
dx
dt= ẋ(t) = f(x, t) (1.50)
In this part, only selected methods are described. The reader can find more
details about these methods in [20]. The basic properties of the described algorithms:
• Step size – The step size is defined by the arguments difference of successive
solution vectors, i.e. the time step hn during the transient analysis with n
being the n-th integration step.
hn = tn+1 − tn (1.51)
• Order – The order, k, of an integration method is defined as follows: With
two successive solution vectors xn+1 and xn given, the successor xn+1 can be
expressed by expanding into a finite Taylor series. The order of an integration
method equals the power of the step size up to which the approximate solution
of the Taylor series differs less than xn from the true solution xn+1.
• Truncation error – The truncation error εT depends on the order k of the
integration method and results from the remainder term of the Taylor series.
The local truncation error is caused by one iteration and the global truncation
error is a cumulative error caused by many iterations.
• Stability – In order to obtain an accurate network solution, integration meth-
ods are required to be stable for a given step size h. The stability determines
the usability of an integration algorithm.
• Single- and multistep methods – Single step methods only use xn in order
to calculate xn+1, multi step methods use xi with 0 ≤ i < n.
• Implicit and explicit methods – When using explicit integration methods,
the evaluation of the integration formula is sufficient for each integration step.
With implicit methods, it is necessary to solve an equation system (with non-
linear problems a non-linear equation system) because for the calculation of
xn+1, apart from xn and ẋn, also ẋn+1 are used.
56
-
CHAPTER 1. CURRENT STATE
1.6.1.1 Runge-Kutta family methods
In general, Runge-Kutta methods are one-step implicit and explicit methods of dif-
ferent order. These methods are essentially based on the Taylor expansion, but the
function derivatives are approximated by the calculation of the function in appro-
priately selected strategic points in the time interval 〈tn, tn+1〉.
Implicit Euler method This method is also called Backward Euler and it is
a first-order single-step method. The right hand side of (1.50) is substituted by
f(xn+1, tn+1) which yields the formula of this method:
xn+1 = xn + hn · f(xn+1, tn+1) (1.52)
Explicit Euler method This method is also called Forward Euler and it is a
first-order single-step method. The formula of this method is given by:
xn+1 = xn + hn · f(xn, tn) (1.53)
Trapezoidal method The method is implicit second-order method and its for-
mula is given by (1.54).
xn+1 = xn +h
2·[
f(xn+1, tn+1) + f(xn, tn)]
(1.54)
4th order Runge-Kutta method The fourth-order Runge-Kutta is given by
(1.55).
xn+1 = xn + 16h(k1 + 2k2 + 2k3 + k4), (1.55)
where
k1 = f(xn, tn)
k2 = f(xn + h
2k1, t
n + 12h)
k3 = f(xn + h
2k2, t
n + 12h)
k4 = f(xn + hk3, t
n + h)
57
-
1.6. NUMERICAL METHODS IN CIRCUIT ANALYSIS
1.6.1.2 Linear multistep methods
Linear multistep methods are a family of ODE solving methods of higher order.
Multistep methods use information from the previous p steps to calculate the next
value. In particular, a linear multistep method uses a linear combination of xi and
f(xi, ti) to calculate the value of x for the desired current step.
In general, a linear multistep method can be written as (1.56).
xn+1 =
p∑
i=0
ai · xn−i + hp
∑
i=−1
bi · f(xn−i, tn−i), (1.56)
where a and b are method coefficients. In case of b−1 6= 0, the method is im-plicit. These methods can be divided into three “families”. The first are Adams-
Bashforth methods (explicit), the second Adams-Moulton (implicit) (1.57) and
the third the Backward Differentiation Formulas (implicit) i.e. Gear
xn+1 = xn + h9
24fn+1 + h
19
24fn − h 5
24fn−1 + h
1
24fn−2 (1.57)
Every implicit method has the property that for its calculation it is necessary to
calculate some approximation of xn+1. This can be done using iterations. The
number of iterations until the solution converges is unknown and that is a disad-
vantage. Compared to the explicit methods, currently, there exist two approaches
[18]. The first approach is to use a fixed number of iterations. The second, more
commonly used approach, is to provide a good initial guess using an explicit integra-
tion method and iterate while the desired tolerance is not reached. This approach
is called predictor-corrector method.
Explicit methods are inexpensive in performance per step but limited in stability
and therefore not used in the field of circuit simulation to obtain a correct and stable
solution. Implicit methods are more expensive in computing capacity per step, have
better stability and therefore suitable for circuit simulation [47].
1.6.2 Root-finding algorithms
These algorithms are used to find a value x such that f(x) = 0, where f is a given
function. Algorithms for root-finding can be divided into two categories: bracke-
58
-
CHAPTER 1. CURRENT STATE
ting and open. Bracketing methods need to work only on specified interval and are
always convergent. Known bracketing methods are: Bisection and False Posi-
tion method. Open methods do not require a bounded interval, but they may not
converge, e.g. Fixed-point iteration (or Function iteration [59]) and Newton-
Raphson method.
Most widely used method in circuit simulation ([82], [30], [101], [102], [22] and
others) is Newton-Raphson. The following section describes this method.
1.6.2.1 Newton-Raphson method
N-R is an iterative root-finding algorithm, that uses the first few terms of the Taylor
series of a function f(x). Suppose, that f(x) is a non-linear function. Its Taylor
series expansion around xk can be written in the form (1.58).
f(x) = f(xk) + (x− xk)f ′(xk) +(x− xk)2
2f ′′(ξ) · · · (1.58)
for some ξ between x and xk. We expect the third term in (1.58) to be very small.
The linearized state is given by (1.59).
f(x) = f(xk) + (x− xk)f ′(xk) (1.59)
For the iteration process, the formula (1.59) is written in form of (1.60).
xk+1 = xk −f(xk)
f ′(xk)(1.60)
The iteration process is repeated until the change between iterations is within desired
tolerance.
|xk+1 − xk| < ǫ (1.61)
For a system of equations, the N-R has following form:
xk+1 = xk − J(xk)−1f(xk), (1.62)
where J(x) is the Jacobian matrix of f . In practice, one does not invert the Jacobian
59
-
1.7. ELECTRICAL NETWORK ANALYSIS METHODS
matrix, but instead a linear system (1.63) is solved.
J(xk)sk = −f(xk), (1.63)
where sk is the N-R step and the next iteration is computed as xk+1 = xk + sk.
Several techniques for solving a linear system are known. There are direct me-
thods and iterative methods. The circuit matrices arise from the N-R applied to
the differential-algebraic equations. It is known, that these matrices are extremely
sparse [31]. The application of direct method to these matrices would transform
them into dense matrices. Dense matrices consume more memory and require more
operations, e.g. by matrix-vector multiplication [38], and therefore iterative methods
designed for sparse matrices are used [83]. A comparison of selected methods in
circuit simulation is available in [31], [23] and [47].
1.7 Electrical network analysis methods
In this section, we briefly describe laws and methods used in network analysis. The
Ohm’s law and the Kirchhoff’s laws can be derived from the Maxwell’s equations
[9]. These laws make the background for the nodal analysis and mesh analysis. The
sparse tableau analysis (STA) presented here is based on the fact, that a circuit
network can be represented as a directed graph, while the modified nodal analysis
is a “happy medium” [83] between the STA and the nodal analysis.
Nodal analysis is based on defining the voltage at each node as a variable [40].
One of the nodes is selected as a reference node (usually ground), and each of the
other node voltages is referenced to this node. In the node voltage method, each
branch current is expressed in terms of one or more node voltages; thus currents
do not explicitly enter the equations. Once each branch current is defined in terms
of the node voltages, Kirchhoff’s current law (KCL) is applied at each node. On
the other hand, the mesh analysis uses mesh currents as the variables. Subsequent
application of Kirchhoff’s voltage law (KVL) around each mesh provides the desired
system of equations.
60
-
CHAPTER 1. CURRENT STATE
1.7.1 Kirchhoff’s current law
At any node in an electrical circuit, the sum of currents flowing into that node in
each time is equal to the sum of currents flowing out of that node.
n∑
k=1
Ik(t) = 0, t ∈ R (1.64)
1.7.2 Kirchhoff’s voltage law
The algebraic sum of the voltages across any set of branches in a closed loop is zero
(1.65), or the voltage (drop) across a branch vb is equal to the difference between
the positive (v+) and the negative (v−) referenced voltages of the nodes on which it
is incident: vb = v+ − v−, [88].n
∑
b=1
vb(t) = 0, t ∈ R (1.65)
1.7.3 Sparse tableau analysis
This method has been proposed in [39]. In [24], this method is declared to be the
most general one, because it simultaneously provides the voltages across all elements,
the currents through all elements and all nodal voltages.
The circuit shown in Fig. 1.23a can be represented using an oriented graph
shown in Fig. 1.23b. The vertices in the graph represent nodes of the circuit and
the edges are the elements. The reference node – usually ground, is also called
the datum. The assignment of the direction on the edges is a free choice, but the
direction on the edges which replaced voltage sources is from plus to minus.
V1 V2
R1 R2
R3
1Ω 100kΩ
1MΩ2V 5V
(a) Circuit
1 4
2 3
5u1
u2
u3
(b) Oriented graph
Figure 1.23: Discussed electrical network
61
-
1.7. ELECTRICAL NETWORK ANALYSIS METHODS
The first step is to write the KCL for the nodes. This can also be summarized in
one matrix equation (1.66) or A · Iel = 0, where A is called an incidence matrix andIel is the vector of currents in branches. It has as many rows as there are ungrounded
nodes, and as many columns as the number of elements. The +1 in any given row
indicates that we expect the current to flow away from the node, −1 means theopposite.
1 1 0 0 0
0 −1 −1 0 10 0 1 1 0
·
IV 1
IR1
IR2
IV 2
IR3
= 0 (1.66)
According to the Fig. 1.23b, it is possible to write a set of equations which couple
the voltages across the elements with the nodal voltages in form Vel −AT ·un = 0,where un are the node voltages. The number of equations is equal to the number of
branches. This system represents the KVL.
VV 1
VR1
VR2
VV 2
VR3
−
1 0 0
1 −1 00 −1 10 0 1
0 1 0
·
u1
u2
u3
= 0 (1.67)
The third step is to write the branch constitutive relations in the form YVel +
ZIel = W. In this case, the branch constitutive equations are given by (1.68).
1 0 0 0 0
0 1 0 0 0
0 0 1 0 0
0 0 0 1 0
0 0 0 0 1
·
VV 1
VR1
VR2
VV 2
VR3
+
0 0 0 0 0
0 −R1 0 0 00 0 −R2 0 00 0 0 0 0
0 0 0 0 −R3
IV 1
IR1
IR2
IV 2
IR3
=
V1
0
0
V2
0
(1.68)
The final step is collecting the KCL, KVL and branch constitutive equations into
one matrix (1.69).
1 0 −AT
Y Z 0
0 A 0
·
Vel
Iel
un
=
0
W
0
(1.69)
62
-
CHAPTER 1. CURRENT STATE
m denotes the number of elements and n the number of nodes. It is obvious,
that the system in (1.69) has 2m+ n− 1 independent equations and the matrix onLHS of the equation is sparse, with no more than 7m−2 non-zero entries [83]. Thisalgorithm was used in earlier circuit simulators like ASTAP in 1973 [106], but it is
possible to find its application in currently developed simulators like [100], as well.
1.7.4 Modified nodal analysis
Authors in [24] and [83] propose to use the modified nodal analysis (MNA) instead
of STA. This method was described in [42] for the first time and it is a an extension
of the nodal analysis. The MNA is based on solving a system of equations given by
A · x = b. The generation of the admittance matrix A and the vector z is doneusing a so-called stamping process. Each element in the circuit is defined by its own
stamp, which is put into them.
Suppose a linear resistor is connected between nodes j and k. The contribution
of this resistor, between these nodes, to KCL is following:
KCL at node j: · · ·+GVj −GVk · · · = 0KCL at node k: · · · −GVk +GVj · · · = 0,
where the Vj and Vk are the nodal voltages at two nodes. The voltage across the
resistor is V = Vj − Vk and G = 1/R. The ellipses (. . . ) denote contribution fromother elements connected to that node. Based on this assumption, the MNA stamp
for the linear resistor is given by Tab. 1.2.
The current through a voltage source connected to the nodes (j is the positive
terminal) j and k (V = Vj − Vk) cannot be written in terms of nodal voltages.In this case, the KCL equations at nodes j and k are listed as:
KCL at node j: · · ·+ Ie · · · = 0KCL at node k: · · · − Ie · · · = 0,
The current Ie is not expressed using voltages, but it is included in the formulation.
This increases the number of unknown variables by one. The circuit stamp for this
element becomes Tab. 1.3. The stamps for other elements can be found in [22].
63
-
1.7. ELECTRICAL NETWORK ANALYSIS METHODS
Matrix A RHSvj vk
j G −Gk −G G
Table 1.2: MNA resistor stamp
Matrix A RHSvl vm Ie
l 1m -1Ie 1 -1 V
Table 1.3: MNA voltage source stamp
Using these formulations, it is possible to set up the system of equations (1.70)
containing the matrix, the RHS vector and the vector of unknowns for the circuit
shown in Fig. 1.23a.
G1 −G1 0 1 0−G1 G1 +G2 +G3 −G2 0 00 −G2 G2 0 11 0 0 0 0
0 0 1 0 0
·
v1
v2
v3
iv1
iv2
=
0
0
0
V1
V2
(1.70)
1.7.4.1 Non-linear elements using MNA
The approach to solving the non-linear circuits is not to solve their non-linear equa-
tions, but instead, to linearize the circuits and build corresponding linear equations.
These equations are solved until convergence is achieved. A diode or a voltage-
controlled non-linear resistor is often used in literature ([83], [30]) to demonstrate
this approach. Suppose, that a diode shown in Fig. 1.24a has its companion model
shown in Fig. 1.24b. The current flowing through the diode (id) is given by the
Shockley diode equation (1.71), where Isat is the reverse bias saturation current, vdis the voltage across the diode, VT is the thermal voltage, and η is the ideality factor.
id = f(vd) = Isat[
evd/(ηVT ) − 1]
(1.71)
The conductance Geq is given by (1.72), while the current Ieq is given by (1.73).
Geq =∂id∂vd
=IsatηVT
evd/(ηVT ) (1.72)
Ieq = id −Geq · vd (1.73)
The modelling of memristors using MNA has been shown in [116], [34] and [6].
64
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CHAPTER 1. CURRENT STATE
D
vd
id
(a) Diode schematic
+
-
1Geq
Ieq
vd
id
(b) Companion modelFigure 1.24: Diode schematic symbol and its companion model
The authors used the constitutive relation of a memristor proposed by Chua. A
memristor defined by i = f(v, w), where f is a non-linear function of the voltage
across the memristor – v and its state variable – w can be understood as a non-linear
voltage-controlled resistor in a single time simulation. In a transient simulation, it
is needed also to consider the addition of the state variable.
A custom memristor simulator, described in [58], should be able to simulate large
memristive arrays. The main cons of this simulator is, that it was primary designed
for simulation of a memristor network containing a linear model – published in [85].
Authors focus on the dynamical properties of the network and not on the non-linear
behaviour of a single device.
1.8 Circuit simulators
This section is dedicated to the circuit simulators. Historically, the simulators can
be roughly divided into two groups. The first group contains simulators, which were
developed before 1975 and the second those developed afterwards. The first ver-
sion of SPICE was released in 1973. It was built on the CANCER [81] (Computer
Analysis of Nonlinear Circuits, Excluding Radiation) simulator, developed using
FORTRAN language. This simulator used nodal analysis to construct the circuit
equations. Several other simulators were also developed before 1975, namely ECAP
[17] and TIME [48], that also used the nodal analysis for the construction of equa-
tions. The simulator ASTAP developed in 1973 [106] used STA as the method for
the generation of circuit equations. In 1975, the second version of SPICE simula-
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1.8. CIRCUIT SIMULATORS
tor was released. This one was also written in FORTRAN language, but used the
MNA to construct the circuit equations. Usage of MNA was the key feature, which
allowed also the usage of floating voltage sources in the circuit. It can be said that
after this release the SPICE has become an industrial standard. Until now, there
have been many commercially developed simulators based on SPICE II or SPICE
III core. Due to the widespread usage of this simulator, the SPICE became an IEEE
milestone in 2011.
1.8.1 SPICE
In the following section we present the algorithm overview and the enhancements
to the methods used in SPICE-like simulators. The next section deals with paral-
lelization techniques proposed in selected papers.
1.8.1.1 Algorithm overview
The commonly used algorithm (without c
top related